AvcModels/TerratecPhase88: phase88-clocking.dot

File phase88-clocking.dot, 1.1 kB (added by ppalmers, 5 years ago)

clocking path only subset of phase88.dot

Line 
1 digraph avcconnections {       
2         "(109) Ext Audio Input SPDIF" [color=slateblue,style=filled];
3         "(6) ASU Ext S/PDIF In" [color=green,style=filled];
4         "(7) ASU Ext Wordclock In" [color=green,style=filled];
5         "(47) S/PDIF Clock" -> "(Selector FB, ID 8)"
6         "(48) Wordclock" -> "(Selector FB, ID 8)"
7         "(Selector FB, ID 8)" ->        "(49) external Clock Source"
8         "(50) internal Clock" -> "(Selector FB, ID 9)"
9         "(51) external Clock" -> "(Selector FB, ID 9)"
10         "(Selector FB, ID 9)" ->        "(52) Clock"
11         "(13) ASU Clocksource" [color=green,style=filled];
12         "(52) Clock" -> "(13) ASU Clocksource"
13         "(49) external Clock Source" -> "(51) external Clock"
14         "(48) Wordclock" [color=yellow,style=filled];
15         "(49) external Clock Source" [color=yellow,style=filled];
16         "(50) internal Clock" [color=yellow,style=filled];
17         "(51) external Clock" [color=yellow,style=filled];
18         "(52) Clock" [color=yellow,style=filled];
19         "(47) S/PDIF Clock" [color=yellow,style=filled];
20         "(7) ASU Ext Wordclock In" -> "(48) Wordclock"
21         "(6) ASU Ext S/PDIF In" -> "(47) S/PDIF Clock"
22         "(109) Ext Audio Input SPDIF" -> "(6) ASU Ext S/PDIF In"
23 }