root/trunk/libffado/doc/rme_notes/rme_config_register_map.txt

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RME: more low-level infrastructure

Line 
1 RME Fireface-400 / Fireface-800 register map
2 ============================================
3
4 Version: 0.6
5 Author: Jonathan Woithe
6 Date: 27 March 2009
7
8
9 Definitions
10 -----------
11
12 CBA = Command Buffer Address
13 FF800 = Fireface-800
14 FF400 = Fireface-400
15
16 Multi-byte values sent to/from the Fireface are generally little endian.
17
18
19 Device address space location
20 -----------------------------
21
22 While some register addresses are common between the two interfaces, the
23 absolute addresses of the settings and control differ.  These are defined
24 relative to the device "command buffer" address:
25
26   FF800: command buffer address (CBA) = 0xfc88f000
27   FF400: command buffer address (CBA) = 0x80100500
28
29 The location of the configuration (settings) registers relative to the
30 command buffer is consistent across devices:
31
32   conf reg 1 address = command buffer address + 5*4
33
34 For a FF800 this equates to 0xfc88f014.
35
36
37 Controlling sample rate (DDS)
38 -----------------------------
39
40 Sample rate is controlled by writing the desired sample rate in Hz to the
41 sample rate control register located at offset 0 from the command buffer
42 address (0xfc88f000 on a FF800).  Rates which have been observed are 32k,
43 44.056k, 44.144k, 44.1k, 45.937k, 46.080k, 47.952k, 48k and 48.048k, along
44 with corresponding 2x and 4x rates.
45
46 Nowhere is there any evidence of register 0xfc88f000 being read by the PC.
47 It seems that the PC explicitly sets the device to its desired sample rate
48 and then caches the sample rate locally.
49
50 In terms of multipliers the RME treats sample rates greater than 112000 Hz
51 as 4x rates, with rates greater than 56000 Hz as 2x rates.  Rates less than
52 30000 Hz and greater than 210000 Hz are invalid.
53
54
55 Configuration registers 1, 2 and 3
56 ----------------------------------
57
58 Most RME device configuration is done using configuration registers 1, 2
59 and 3.  For the ff800 these are:
60
61   config1 = configuration register 1 (FF800: 0xfc88f014, FF400: 0x80100514)
62   config2 = configuration register 2 (FF800: 0xfc88f018, FF400: 0x80100518)
63   config3 = configuration register 3 (FF800: 0xfc88f01c, FF400: 0x8010051c)
64
65 In essence the configuration registers start at CBA+5*4 for both interfaces.
66
67 When making a configuration change these registers are always written in a
68 block of 12 bytes starting at 0xfc88f014 with a block write operation.
69
70 Configuration register 1 (FF800: 0xfc88f014, FF400: 0x8010014):
71
72   bits 31-18: unknown, set to 0
73   bits 17-16: Phones level:
74     00 = +4 dBu
75     01 = -10 dBV
76     10 = hi-gain
77   bits 15-14: unknown, set to 0
78   bits 13-11: Output level control (part 1 of 2: FPGA LED drive):
79     001 = hi-gain
80     010 = +4dBU
81     100 = -10dBV
82   bit 10: Instrument option: Drive (part 1 of 2: FPGA LED drive) (active = 1)
83   bit 9: unknown, set to 0
84   bit 8: Phantom power, mic 10 (active = 1)
85   bit 7: Phantom power, mic 8 (active = 1)
86   bit 6: unknown, set to 0
87   bits 5-3: Input level control (part 1 of 2: FPGA LED drive):
88     001 = lo-gain
89     010 = +4dBU
90     100 = -10dbV
91   bit 2: Instrument option: speaker emulation (part 1 of 2: FPGA LED drive)
92     (active = 1)
93   bit 1: Phantom power, mic 9 (active = 1)
94   bit 0: Phantom power, mic 7 (active = 1)
95
96 Configuration register 2 (FF800: 0xfc88f018, FF400: 0x80100518):
97
98   bits 31-12: unknown, set to 0
99   bit 11: Input #1 front switch (active = 1)
100   bit 10: unknown, set to 0
101   bit 9: Instrument option: Drive (part 2 of 2: CPLD function) (active = 0)
102   bit 8: Input #8 rear switch (active = 1)
103   bit 7: Input #8 front switch (active = 1)
104   bit 6: Input #7 rear switch (active = 1)
105   bit 5: Input #7 front switch (active = 1)
106   bits 4-3: Output level control (part 2 of 2: CPLD function):
107     00 = undefined
108     01 = -10dBV
109     10 = hi-gain
110     11 = +4dBU
111   bit 2: Input #1 rear switch (active = 1)
112   bits 1-0: Input level control (part 2 of 2: CPLD function):
113     00 = lo-gain
114     01 = undefined
115     10 = +4dBU
116     11 = -10dbV
117
118 Configuration register 3 (FF800: 0xfc88f01c, FF400: 0x8010051c):
119   bit 31: "Drop and stop": always set to 1
120   bit 30: Unit option: TMS (active = 1)
121   bits 29-27: set to 0
122   bit 26: set to 1 for FF400, 0 for FF800
123   bits 25-17: set to 0
124   bit 16: P12DB_AN0 (normally set to 0)
125   bit 15: set to 0
126   bit 14: Toggle TCO (normally set to 0)
127   bit 13: Word clock single speed: 0 = off, 1 = on
128   bits 12-10: Sync reference source:
129     000 = ADAT1
130     001 = ADAT2
131     011 = SPDIF
132     100 = Word clock
133     101 = TCO
134   bit 9: SPDIF input source: 0 = coax, 1 = ADAT2 port
135   bit 8: SPDIF output option: ADAT2
136   bit 7: SPDIF output option: non-audio
137   bit 6: SPDIF output option: emphasis
138   bit 5: SPDIF output option: professional
139   bit 4: QS control (set to 1)
140   bit 3: DS control (set to 1)
141   bit 2: Freq1 control (set to 1)
142   bit 1: Freq0 control (set to 1)
143   bit 0: Clock mode: 0 = Master, 1 = Autosync
144
145
146 Interfacing to device flash
147 ---------------------------
148
149 To preserve the device's settings across power cycles the settings are
150 stored in a flash memory on the device.  This is read during driver
151 initialisation to ensure the driver's status agrees with that of the device.
152
153 There are several classes of things stored in flash: operational settings,
154 volumes (ie: the mixer status) and configuration/firmware.  Device settings
155 start at address 0x3000f0000 on the FF800 and 0x00060000 on the FF400.
156
157 Mixer (volume) data starts at 0x3000e0000 on the FF800 and 0x00060000 on the
158 FF400.  Mixer volumes are written in 64-quadlet (256-byte) blocks, one per
159 hardware channel.  There are 28 hardware channels for the FF800 and 18 for
160 the FF400.
161
162 There are several control groups in the mixer:
163   0xe0000 (FF800): "mixer shadow", FF800 only, meaning unclear
164   0xe2000 (FF800) / 0x70000 (FF400), 0x0800 bytes: 16-bit volume array
165   0xe2800 (FF800) / 0x70800 (FF400), 0x0800 bytes: 16-bit pan array
166   0xe3000 (FF800) / 0x71000 (FF400), 0x0040 bytes: 16-bit "vol3" array +
167     "enable MIDI" + "submix" + zero padding to 64 bytes
168 The third row are the "hardware output volumes".
169
170 The meaning of the "mixer shadow" section of the mixer flash is not
171 understood at present.
172
173
174 Reading the flash
175
176 For the FF800 the entire buffer is read directly from flash as a single block.
177 Polling for "device not busy" should commence after a wait of 5 ms.
178
179 For the FF400, the buffer is read in 32-quadlet sub-blocks.  A partial block
180 is read at the end if the total buffer size is not a multiple of
181 32-quadlets.  To read a sub-block, the address is placed in register
182 0x80100288 and the sub-block size (in bytes) in 0x8010028c.  A 0x02 is
183 then written to CBA+(8*4) to initiate the read.  Polling for "device not
184 busy" should commence after a wait of 2 ms.
185
186
187 Writing the flash
188
189 For the FF800, the entire buffer is written to flash as a single block.
190 Polling for "device not busy" should commence after a wait of 5 ms.
191
192 For the FF400, the buffer is written in 32-quadlet (128-byte) sub-blocks via
193 a bounce buffer.  If the final sub-block is not 32-quadlets the write is
194 only as big as the sub-block (that is, no padding takes place).  The
195 sub-block data to be written is sent to the block starting at 0x80100290.
196 The 2-quadlet register at 0x80100288 is set with the flash address to write
197 the block to and the size (in bytes) of the data block.  Finally, a 0x1 is
198 written to CBA+(8*4) to initiate the write.  Polling for "device not busy"
199 should commence after a wait of 2 ms.
200
201
202 Erasing the flash
203
204 The flash is divided into sections and it is possible to erase each section
205 separately.  Therefore one only has to erase section of interest when
206 changing something.
207
208 On the FF400, erasure is controlled by writing a special magic number to
209 the the flash control register (CBA+8*4):
210   Erase volume: write 0xe
211   Erase settings: write 0xd
212   Erase configuration (firmware): write 0xc
213
214 On the FF800, erasing is controlled by writing 0 to the applicable register:
215   Erase volume: register is 0x3fffffff4
216   Erase settings: register is 0x3fffffff0
217   Erase firmware: register is 0x3fffffff8
218   Erase configuration: register is 0x3fffffffc
219
220 It's not clear what the distinction between "configuration" and "firmware"
221 is.  The FF400 appears to only support "configuration" but treats this as
222 "firmware".  The FF800 supports both as distinct options.
223
224 After issuing the erase command one should wait for 500 ms before polling
225 the device for the "not busy" status.
226
227
228 Waiting for flash
229
230 When interacting with the device's flash memory one must wait for the
231 completion of an operation before attempting another.  The location of the
232 "device busy" flag differs between the FF400 and FF800.
233
234 On the FF800 is part of the quadlet register at 0x801c0004 (part of the
235 read-only status register block beginning at 0x801c0000).  The device is
236 ready to accept another command when bit 30 is set.
237
238 On the FF400 the wait state is found by reading a quadlet from CBA+8*4.
239 If this quadlet is zero the FF400 is ready to accept another command.
240
241 Most device flash operations have a minimum time to complete.  There's no
242 point in polling the device busy flag until at least this much time has
243 elapsed.
244
245
246 Device settings format
247 ----------------------
248
249 The device settings are stored in flash as an array of 32 bit unsigned
250 integers.  These are:
251   - Device ID
252   - Device revision
253   - ASIO latency
254   - Samples per frame
255   SPDIF input mode (0=coax?, 1=optical?)
256   SPDIF output emphasis active
257   SPDIF output is "professional" (ie: AES/EBU)
258   Clock mode (0=master?, 1=autosync?)
259   SPDIF output is non-audio (eg: AC3 passthrough)
260   Sync reference
261   SPDIF output mode (0=coax?, 1=optical?)
262   - Check input
263   - Status
264   - Register[4]
265   - Iso receive channel
266   - Iso transmit channel
267   - Timecode
268   - Number of devices
269   - TMS
270   - Speed
271   - Channels available (high)
272   - Channels available (low)
273   Limit bandwidth setting
274   - Bandwidth allocated
275   - Stop on dropout
276   Input level
277   Output level
278   Mic level [0] - FF400:Phoneslevel-1 / F800:AnalogInput[1]* ???
279   Mic level [1] - AnalogInput[2] ???
280   Mic phantom power [4]
281   Instrument - AnalogInput[0]-1 ???
282   Filter (aka speaker emulation)
283   Fuzz (aka drive)
284   Sync align
285   - Device index
286   - Advanced dialog
287   Sample rate
288   - Interleaved
289   - Sn
290   Word clock single speed
291   - Number of channels
292   - Dropped samples
293   p12db_an[0] - Limiter==0&&AnalogInput[0]==2*: 1 else 0 ???
294   - p12db_an[1-9]
295
296 "-" = elements not used
297
298
299 Streaming control registers
300 ---------------------------
301
302 There appears to be a number of registers involved in the setup of device
303 streaming.
304
305 Device (streaming) initialisation register (FF800: 0x20000001c, FF400: CBA)
306
307 This register comprises the 3 quadlets starting at address 0x20000001c on
308 the FF800 and the CBA on the FF400.  The first quadlet contains the sample
309 rate in Hz.  The second quadlet is mapped as follows:
310   bits 31-11 = number of audio channels
311   bits 10-0  = iso tx channel (PC to interface)
312 In all local tests with a FF800 the value of this quadlet was always equal
313 to 0x0000e000 (28 channels, PC transmits on iso channel 0).
314
315 The third quadlet is mapped as follows.
316   bits 10-0 = number of audio channels
317   bit 11    = speed flag; set to 1 if firewire bus is at 800 Mbps
318 In local tests with a FF800 the value of this register was always 0x0000001c
319 (28 channels, 400 Mbps firewire bus).
320
321 After this register is configured, 4 quadlets are read starting from
322 0x801c0000.  The numbers returned don't appear to bear any relationship to
323 those written to this same location later on.
324
325 Device (streaming) start register (FF800: 0x200000028, FF400: CBA+0x1c):
326
327 The start of streaming differs between the FF400 and FF800 in more than just
328 the address of the relevant register.  On the FF800 this register is mapped
329 as follows:
330   bits 10-0 = number of audio channels
331   bit 11    = bus speed flag; set to 1 if firewire bus is at 800 Mbps
332 On a FF400 the register is as follows:
333   bits 4-0  = number of audio channels
334   bits 9-5  = iso tx channel (PC to interface)
335 During initial testing with a FF800 the value of this register was always
336 0x0000001c (28 audio channels, PC tx on iso channel 0).
337
338 Channel mute setup register (write to 0x801c0000):
339
340 After writing to the streaming start register, 0x70 bytes (28 quadlets) are
341 written starting at 0x801c0000.  Each quadlet represents one channel on the
342 Fireface800.  A value of 1 mutes the respective channel - indeed on closing
343 down streaming each quadlet is set to 1.  During startup some values are set
344 to zero - the ones set to zero may be determined by the channels which have
345 active software data sources although this is yet to be confirmed with more
346 testing.  Irrespective of the setting of these registers it appears that
347 data for all channels is always sent to/from the Fireface-800.
348
349 Note that when register 0x801c0000 is read it functions as the device status
350 register.  It is read during streaming setup, but obviously it bears no
351 relationship to the channel mute status.
352
353 Streaming end register (FF800: 0x200000034, FF400: CBA+0x4):
354
355 On the FF800, streaming is stopped by writing 3 zeroed quadlets to
356 consecutive registers starting at address 0x200000034.  For the FF400 one
357 writes 3 zeroed quadlets to consecutive registers from CBA+0x4, followed
358 by a 0x00000001 to CBA+0x10 (making a 4-quadlet write in total).
359
360
361 Iso data
362 --------
363
364 Audio/midi data is sent and received on isochronous channels previously
365 configured by the driver.  On a dedicated bus with nothing else present, the
366 stream to the fireface is sent on iso channel 0 while data from the fireface
367 is sent on iso channel 1.
368
369 No CIP header is included in the iso data packet.  Fireface data follows
370 immediately after the standard 2-quadlet firewire iso packet header.
371
372 Each iso packet contains a number of samples across all 28 device channels.
373 For 1x rates, 7 samples per channel seem to be sent.  Thus the size of
374 the data portion of a 1x iso packet is 28*4*7 = 784, with a total packet
375 size being 784 + 8 = 792.
376
377 The data is sent with one audio channel per quadlet.  The audio data is a 24
378 bit integer stored in the most-significant 3 bytes of a quadlet.  The LSB
379 (low byte) of certain channels in the stream sent by the Fireface is used to
380 send synchronising information:
381
382   Low byte of channel 6 = current frame
383   Low byte of channel 7 = phase
384   Low byte of channel 1 = rx sample counter, low byte
385   Low byte of channel 4 = rx sample counter, high byte
386   Low byte of channel 0 = tx buffer size, low byte
387   Low byte of channel 5 = tx buffer size, high byte
388   Low byte of channel 2 & 3 = unknown (midi?)
389
390 The low byte data from channels 0-7 is repeated in channels 8-15 and 16-23
391 respectively, with channels 24-27 containing the low byte data from channels
392 0-3.  This repetition holds for the low bytes of channels 2-3 in all data
393 seen so far, it might not necessarily be the case in general - it depends
394 what the low byte data from channels 2 and 3 are used for.
395
396 The rx sample counter appears to be used to detect missed samples.  The
397 current frame and phase from a received packet is used in conjunction with
398 the stored values of these from the previous frame to track the phase of
399 the audio clock.
400
401 A "frame" consists of a fixed number of samples across all channels of the
402 device.  At 1x rates this appears to be 7, but it might not be fixed.  Even
403 though this is the same as the number of samples per channel per packet, a
404 given packet can experience a change in the "current frame" part way
405 through.  In other words, the "current frame" is not necessarily constant
406 for all samples in a packet.
407
408
409 Mixer controls
410 --------------
411
412 The matrix mixer on the Fireface-800 is controlled using a block of
413 registers starting at 0x80080000.  A 28x28 matrix mixer is implemented
414 allowing any device input to be sent to any device output.  The pan controls
415 are synthesised by manipulating the "left/right" controls.
416
417 In each sub-block, the order of channels is in fireface numeric order.  That
418 is, Analog 1-10, SPDIF, ADAT1 1-8, ADAT2 1-8.
419
420 0x80080000 - 0x8008006c: input channel sends to Analog 1 output.
421 0x80080080 - 0x800800ec: playback channel sends to Analog 1 output.
422 0x80080100 - 0x8008016c: input channel sends to Analog 2 output.
423 0x80080180 - 0x800801ec: playback channel sends to Analog 2 output.
424 :
425 0x80081b00 - 0x80081b6c: input channel sends to ADAT2-8 output.
426 0x80081b80 - 0x80081bec: playback channel sends to ADAT2-8 output.
427
428 0x80081f80: matrix mixer analog 1 output fader
429 0x80081f84: matrix mixer analog 2 output fader
430 :
431 0x80081fec: maxtrix mixer ADAT2-8 output fader
432
433 Each fader control ranges from 0x00000000 (-inf) through 0x00008000 (0.0dB)
434 and up to a maximum setting of 0x00010000 (+6.5dB).
435
436 Mute is synthesised by setting the respective send value to -inf (0).
437 Conversely, solo is synthesised by muting all sends to the selected bus
438 except the send being soloed.
439
440
441 Metering values
442 ---------------
443
444 The Fireface-800 appears to provide hardware support for metering.  The RME
445 mixer application periodically sends block read requests for register
446 0x80100000 with a size of 0x3f8.  What is returned is a set of two
447 datablocks with data in little-endian (least significant bit/word first)
448 format.  The first block contains arrays of 64-bit floating point numbers
449 representing channel amplitude with decay, presumedly useful for metering
450 display.  Arrays are:
451
452   28-element array for input channel amplitude with decay
453   28-element array for playback amplitudes with decay (educated guess)
454   28-element array for output amplitudes with decay
455
456 The second data block contains signed 32 bit integers representing the input
457 amplitudes without decay.  Valid range is 0 - 0x7ffffff.  Again there are 3
458 arrays:
459
460   28-element array for input channel ampltude
461   28-element array for playback amplitudes (educated guess)
462   28-element array for output amplitudes
463
464 At the end of this second block are two zero quadlets.  Their purpose is
465 unknown at this stage.
466
467 In each 28-element array the channel data appears in standard fireface
468 order.
469
470
471 Host LED
472 --------
473
474 The "host" LED of the FF800 is controlled by a dedicated register at
475 0x200000324.  Note that this register address goes beyond the 32-bit
476 boundary.
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