root/trunk/libffado/doc/rme_notes/rme_config_register_map.txt

Revision 1570, 22.7 kB (checked in by jwoithe, 15 years ago)

RME: add more details to device initialisation code. The basic structure is now in place.
RME: update documentation.

Line 
1 RME Fireface-400 / Fireface-800 register map
2 ============================================
3
4 Version: 0.10
5 Author: Jonathan Woithe
6 Date: 29 May 2009
7
8
9 Definitions
10 -----------
11
12 CBA = Command Buffer Address
13 FF800 = Fireface-800
14 FF400 = Fireface-400
15
16 Multi-byte values sent to/from the Fireface in async packets are generally
17 little endian - that is, the device interprets quadlets in asynchronous
18 packets as little endian even though the bus definition is big-endian.  If
19 writing a driver for use on a little endian machine, this means that a lack
20 of byte swapping (to account for the bus endianness standard) will cause bit
21 0 on the host to be bit 0 on the device.
22
23 By default, FFADO however adheres to the bus standards and byteswaps on
24 little endian machines.  Under this regime, bit 0 on the host will in fact
25 be read by the device as the least significant bit in the most significant
26 byte.
27
28 In order to retain consistency with device documentation, the FFADO RME
29 driver currently sends async packet data in the little endian format which
30 the RME device expects.  Although this is technically wrong (in so far as
31 the Firewire standard is concerned), at this stage it is considered that
32 introducing an endianness difference between the FFADO driver and the
33 documentation is likely to result in maintenance issues down the track.
34
35 The bit maps in this document regarding the configuration registers are
36 written from the device's point of view.  That is, the values quoted should
37 be sent to the device in little endian format unless otherwise stated.
38
39 Curiously enough, preliminary investigations suggest that audio data appears
40 to be sent on the bus in big endian format (although this is to be
41 confirmed).
42
43 The FF800 includes a number of instrument options for input 1 which are
44 described using several different terms interchangeably:
45  - "Drive" (also referred to as "fuzz") activates 25 dB extra gain
46  - "Speaker emulation" (also referred to as "filter") removes LF noise and
47    some HF
48  - "Limiter" activates a soft-limiter with a threshold of -10 dBFS.  This
49    can only be switched off if the Front input is used for channel 1.
50
51
52 Device address space location
53 -----------------------------
54
55 While some register addresses are common between the two interfaces, the
56 absolute addresses of the settings and control differ.  These are defined
57 relative to the device "command buffer" address:
58
59   FF800: command buffer address (CBA) = 0xfc88f000
60   FF400: command buffer address (CBA) = 0x80100500
61
62 The location of the configuration (settings) registers relative to the
63 command buffer is consistent across devices:
64
65   conf reg 1 address = command buffer address + 5*4
66
67 For a FF800 this equates to 0xfc88f014.
68
69
70 Controlling sample rate (DDS)
71 -----------------------------
72
73 Sample rate is controlled by writing the desired sample rate in Hz to the
74 sample rate control register located at offset 0 from the command buffer
75 address (0xfc88f000 on a FF800).  Rates which have been observed are 32k,
76 44.056k, 44.144k, 44.1k, 45.937k, 46.080k, 47.952k, 48k and 48.048k, along
77 with corresponding 2x and 4x rates.  This assumes the DDS has been enabled.
78 If DDS is not active it seems the audio system assumes a frequency of 44.1
79 kHz which cannot be changed.  The value of disabling the DDS is therefore
80 not entirely understood.
81
82 The PC does not appear to request the device's current sample rate; in fact,
83 it doesn't appear to be available from the device itself (except from the
84 flash device setting record in the case where the DDS has been enabled).
85 When requesting the device status, the sample rate returned is based on the
86 PC's audio engine sample rate so long as the device status has been read
87 without error (if an error occurs the sample rate is hardcoded to 44.1 kHz).
88 It therefore seems that when DDS is in use the PC explicitly sets the device
89 to its desired sample rate and then caches the sample rate locally.  If DDS
90 is not active it appears at this stage that the only internally generated
91 sample rate available is 44.1 kHz.
92
93 When using an external clock without DDS it's not clear how the PC works out
94 what sample rate to use.  Presumedly it remains at 44.1 kHz.
95
96 In terms of multipliers the RME treats sample rates greater than 112000 Hz
97 as 4x rates, with rates greater than 56000 Hz as 2x rates.  Rates less than
98 30000 Hz and greater than 210000 Hz are invalid.
99
100 It is not yet known how the driver works out that the DDS is active since
101 the device flash settings are not read and in any case, if the device flash
102 settings have not been set they won't indicate anything useful about the
103 current device state.
104
105
106 Configuration registers 1, 2 and 3
107 ----------------------------------
108
109 Most RME device configuration is done using configuration registers 1, 2
110 and 3.  For the ff800 these are:
111
112   config1 = configuration register 1 (FF800: 0xfc88f014, FF400: 0x80100514)
113   config2 = configuration register 2 (FF800: 0xfc88f018, FF400: 0x80100518)
114   config3 = configuration register 3 (FF800: 0xfc88f01c, FF400: 0x8010051c)
115
116 In essence the configuration registers start at CBA+5*4 for both interfaces.
117
118 When making a configuration change these registers are always written in a
119 block of 12 bytes starting at 0xfc88f014 with a block write operation.
120
121 Configuration register 1 (FF800: 0xfc88f014, FF400: 0x8010014):
122
123   bits 31-18: unknown, set to 0
124   bits 17-16: Phones level:
125     00 = +4 dBu
126     01 = -10 dBV
127     10 = hi-gain
128   bits 15-13: unknown, set to 0
129   bits 12-10: Output level control (part 1 of 2: FPGA LED drive):
130     001 = hi-gain
131     010 = +4dBU
132     100 = -10dBV
133   bit 9: Instrument option: Drive (part 1 of 2: FPGA LED drive) (active = 1)
134   bit 8: Phantom power, mic 10 (active = 1)
135   bit 7: Phantom power, mic 8 (active = 1)
136   bit 6: unknown, set to 0
137   bits 5-3: Input level control (part 1 of 2: FPGA LED drive):
138     001 = lo-gain
139     010 = +4dBU
140     100 = -10dbV
141   bit 2: Instrument option: speaker emulation (part 1 of 2: FPGA LED drive)
142     (active = 1)
143   bit 1: Phantom power, mic 9 (active = 1)
144   bit 0: Phantom power, mic 7 (active = 1)
145
146 Configuration register 2 (FF800: 0xfc88f018, FF400: 0x80100518):
147
148   bits 31-12: unknown, set to 0
149   bit 11: Input #1 front switch (active = 1)
150   bit 10: unknown, set to 0
151   bit 9: Instrument option: Drive (part 2 of 2: CPLD function) (active = 0)
152   bit 8: Input #8 rear switch (active = 1)
153   bit 7: Input #8 front switch (active = 1)
154   bit 6: Input #7 rear switch (active = 1)
155   bit 5: Input #7 front switch (active = 1)
156   bits 4-3: Output level control (part 2 of 2: CPLD function):
157     00 = undefined
158     01 = -10dBV
159     10 = hi-gain
160     11 = +4dBU
161   bit 2: Input #1 rear switch (active = 1)
162   bits 1-0: Input level control (part 2 of 2: CPLD function):
163     00 = lo-gain
164     01 = undefined
165     10 = +4dBU
166     11 = -10dbV
167
168 Configuration register 3 (FF800: 0xfc88f01c, FF400: 0x8010051c):
169   bit 31: "Drop and stop": always set to 1
170   bit 30: Unit option: TMS (active = 1)
171   bits 29-27: set to 0
172   bit 26: set to 1 for FF400, 0 for FF800
173   bits 25-17: set to 0
174   bit 16: P12DB_AN0 (normally set to 0)
175   bit 15: set to 0
176   bit 14: Toggle TCO (normally set to 0)
177   bit 13: Word clock single speed: 0 = off, 1 = on
178   bits 12-10: Sync reference source:
179     000 = ADAT1
180     001 = ADAT2
181     011 = SPDIF
182     100 = Word clock
183     101 = TCO
184   bit 9: SPDIF input source: 0 = coax, 1 = ADAT2 port
185   bit 8: SPDIF output option: ADAT2
186   bit 7: SPDIF output option: non-audio
187   bit 6: SPDIF output option: emphasis
188   bit 5: SPDIF output option: professional
189   bit 4: QS control (set to 1)
190   bit 3: DS control (set to 1)
191   bit 2: Freq1 control (set to 1)
192   bit 1: Freq0 control (set to 1)
193   bit 0: Clock mode: 0 = Master, 1 = Autosync
194
195 On the FF400, writing to these registers with valid values for the first
196 time after power up has the side effect of extingishing the "Host" LED.
197
198
199 Interfacing to device flash
200 ---------------------------
201
202 To preserve the device's settings across power cycles the settings are
203 stored in a flash memory on the device.  This is read during driver
204 initialisation to ensure the driver's status agrees with that of the device.
205
206 There are several classes of things stored in flash: operational settings,
207 volumes (ie: the mixer status) and configuration/firmware.  Device settings
208 start at address 0x3000f0000 on the FF800 and 0x00060000 on the FF400.
209
210 Mixer (volume) data starts at 0x3000e0000 on the FF800 and 0x00060000 on the
211 FF400.  Mixer volumes are written in 64-quadlet (256-byte) blocks, one per
212 hardware channel.  There are 28 hardware channels for the FF800 and 18 for
213 the FF400.
214
215 There are several control groups in the mixer:
216   0xe0000 (FF800): "mixer shadow", FF800 only, meaning unclear
217   0xe2000 (FF800) / 0x70000 (FF400), 0x0800 bytes: 16-bit volume array
218   0xe2800 (FF800) / 0x70800 (FF400), 0x0800 bytes: 16-bit pan array
219   0xe3000 (FF800) / 0x71000 (FF400), 0x0040 bytes: 16-bit "vol3" array +
220     "enable MIDI" + "submix" + zero padding to 64 bytes
221 The third row are the "hardware output volumes".
222
223 The meaning of the "mixer shadow" section of the mixer flash is not
224 understood at present.
225
226
227 Reading blocks from the flash (flash command 0x2)
228
229 For the FF800 the entire buffer is read directly from flash as a single block.
230 Polling for "device not busy" should commence after a wait of 5 ms.
231
232 For the FF400, the buffer is read in 32-quadlet sub-blocks.  A partial block
233 is read at the end if the total buffer size is not a multiple of
234 32-quadlets.  To read a sub-block, the address is placed in register
235 0x80100288 and the sub-block size (in bytes) in 0x8010028c.  A 0x02 is
236 then written to CBA+(8*4) to initiate the read.  Polling for "device not
237 busy" should commence after a wait of 2 ms.  Once not busy the data is
238 available for reading from 0x80100290.
239
240
241 Writing blocks to the flash (flash command 1)
242
243 For the FF800, the entire buffer is written to flash as a single block.
244 Polling for "device not busy" should commence after a wait of 5 ms.
245
246 For the FF400, the buffer is written in 32-quadlet (128-byte) sub-blocks via
247 a bounce buffer.  If the final sub-block is not 32-quadlets the write is
248 only as big as the sub-block (that is, no padding takes place).  The
249 sub-block data to be written is sent to the block starting at 0x80100290.
250 The 2-quadlet register at 0x80100288 is set with the flash address to write
251 the block to and the size (in bytes) of the data block.  Finally, a 0x1 is
252 written to CBA+(8*4) to initiate the write.  Polling for "device not busy"
253 should commence after a wait of 2 ms.
254
255
256 Getting other data from flash
257
258 There are a few other commands issued to the flash memory system for
259 obtaining data about the connected interface:
260
261  * Device revision
262
263    On the FF800 this is read directly from register 0x200000100.
264
265    On the FF400, 0xf is written to CBA+(8*4).  Poll for "not busy" after a
266    wait of 2ms.  Once not busy the revision is read from register
267    0x80100290.
268
269
270 Erasing the flash
271
272 The flash is divided into sections and it is possible to erase each section
273 separately.  Therefore one only has to erase section of interest when
274 changing something.
275
276 On the FF400, erasure is controlled by writing a special magic number to
277 the the flash control register (CBA+8*4):
278   Erase volume: write 0xe
279   Erase settings: write 0xd
280   Erase configuration (firmware): write 0xc
281
282 On the FF800, erasing is controlled by writing 0 to the applicable register:
283   Erase volume: register is 0x3fffffff4
284   Erase settings: register is 0x3fffffff0
285   Erase firmware: register is 0x3fffffff8
286   Erase configuration: register is 0x3fffffffc
287
288 It's not clear what the distinction between "configuration" and "firmware"
289 is.  The FF400 appears to only support "configuration" but treats this as
290 "firmware".  The FF800 supports both as distinct options.
291
292 After issuing the erase command one should wait for 500 ms before polling
293 the device for the "not busy" status.
294
295
296 Waiting for flash
297
298 When interacting with the device's flash memory one must wait for the
299 completion of an operation before attempting another.  The location of the
300 "device busy" flag differs between the FF400 and FF800.
301
302 On the FF800 is part of the quadlet register at 0x801c0004 (part of the
303 read-only status register block beginning at 0x801c0000).  The device is
304 ready to accept another command when bit 30 is set.
305
306 On the FF400 the wait state is found by reading a quadlet from CBA+8*4.
307 If this quadlet is zero the FF400 is ready to accept another command.
308
309 Most device flash operations have a minimum time to complete.  There's no
310 point in polling the device busy flag until at least this much time has
311 elapsed.
312
313
314 Device settings format
315 ----------------------
316
317 The device settings are stored in flash as an array of 59 32-bit unsigned
318 integers.  These are:
319   0 - Device ID (FF400=0x77e1f4ea)
320   1 - Device revision (FF400=0x004af3d8)
321   2 - ASIO latency (FF400=0x00000001)
322   3 - Samples per frame (FF400 default is 0x30)
323   4 SPDIF input mode (2=coax?, 1=optical?)
324   5 SPDIF output emphasis active
325   6 SPDIF output is "professional" (ie: AES/EBU)
326   7 Clock mode (2=master?, 1=autosync?)
327   8 SPDIF output is non-audio (eg: AC3 passthrough)
328   9 Sync reference
329  10 SPDIF output mode (0=coax?, 1=optical?)
330  11 - Check input
331  12 - Status (FF400 idle=0x77e691d0)
332  13 - Register[4] (FF400 = 0x004adbc8,0x001377c0,0x000301ee,0x00000001)
333  17 - Iso receive channel (FF400=0x7ffde000)
334  18 - Iso transmit channel (FF400=0x77f43664)
335  19 - Timecode (FF400 example: 0x004b35c8)
336  20 - Device type (FF400=0x00000001)
337  21 - Number of devices (FF400=0x77f43664)
338  22 TMS (FF400=0x00000000)
339  23 - Speed (FF400=0x00000000)
340  24 - Channels available (high) (FF400=0x0012f2e4)
341  25 - Channels available (low) (FF400=0x00000000)
342  26 Limit bandwidth setting (0=full bandwidth)
343  27 - Bandwidth allocated (FF400=0x00000000)
344  28 Stop on dropout (FF400=0x00000000)
345  29 Input level (0=default, 1=lo-gain, 2=+4dBU, 3=-10dBV ???)
346  30 Output level (0=default, 1=hi-gain, 2=+4dBU, 3=-10dBV ???)
347  31 Mic level [0] - FF400:Phoneslevel-1 / F800:AnalogInput[1]* ???
348  32 Mic level [1] - AnalogInput[2] ???
349  33 Mic phantom power [4]
350  37 Instrument - AnalogInput[0]-1 ???
351  38 Filter (aka speaker emulation)
352  39 Fuzz (aka drive)
353  40 - Sync align
354  41 - Device index (FF400=0x77e24d0d)
355  42 - Advanced dialog (FF400=0x000201f8) [but might be related to TCO control)
356  43 Sample rate (eg: 0x0000ac44) [set to 0x00000000 unless DDS enabled]
357  44 - Interleaved (FF400=0x00000000)
358  45 - Sn (FF400=0x77e14925)
359  46 Word clock single speed (1=single speed)
360  47 - Number of channels (FF400=0x000000f0)
361  48 - Dropped samples
362  49 p12db_an[0] - Disable limiter, settable only if input 1 front jack active
363  50 - p12db_an[1-9]
364
365 "-" = elements not used (under MacOSX at least)
366
367 Total size: 59 quadlets
368
369 The default state of these quadlets is 0xffffffff, which is taken to
370 indicate that the respective setting has not been written to flash. This in
371 turn causes the driver to assume its own default value.  While these
372 settings can be changed in real time by writing to the relevant control
373 registers, these are not persistent across device power cycles.  To make
374 them persistent it is necessary to store them into the flash.
375
376
377 Streaming control registers
378 ---------------------------
379
380 There appears to be a number of registers involved in the setup of device
381 streaming.
382
383 Device (streaming) initialisation register (FF800: 0x20000001c, FF400: CBA)
384
385 This register comprises the 3 quadlets starting at address 0x20000001c on
386 the FF800 and the CBA on the FF400.  The first quadlet contains the sample
387 rate in Hz.  The second quadlet is mapped as follows:
388   bits 31-11 = number of audio channels
389   bits 10-0  = iso tx channel (PC to interface)
390 In all local tests with a FF800 the value of this quadlet was always equal
391 to 0x0000e000 (28 channels, PC transmits on iso channel 0).
392
393 The third quadlet is mapped as follows.
394   bits 10-0 = number of audio channels
395   bit 11    = speed flag; set to 1 if firewire bus is at 800 Mbps
396 In local tests with a FF800 the value of this register was always 0x0000001c
397 (28 channels, 400 Mbps firewire bus).
398
399 After this register is configured, 4 quadlets are read starting from
400 0x801c0000.  The numbers returned don't appear to bear any relationship to
401 those written to this same location later on.
402
403 Device (streaming) start register (FF800: 0x200000028, FF400: CBA+0x1c):
404
405 The start of streaming differs between the FF400 and FF800 in more than just
406 the address of the relevant register.  On the FF800 this register is mapped
407 as follows:
408   bits 10-0 = number of audio channels
409   bit 11    = bus speed flag; set to 1 if firewire bus is at 800 Mbps
410 On a FF400 the register is as follows:
411   bits 4-0  = number of audio channels
412   bits 9-5  = iso tx channel (PC to interface)
413 During initial testing with a FF800 the value of this register was always
414 0x0000001c (28 audio channels, PC tx on iso channel 0).
415
416 Channel mute setup register (write to 0x801c0000):
417
418 After writing to the streaming start register, 0x70 bytes (28 quadlets) are
419 written starting at 0x801c0000.  Each quadlet represents one channel on the
420 Fireface800.  A value of 1 mutes the respective channel - indeed on closing
421 down streaming each quadlet is set to 1.  During startup some values are set
422 to zero - the ones set to zero may be determined by the channels which have
423 active software data sources although this is yet to be confirmed with more
424 testing.  Irrespective of the setting of these registers it appears that
425 data for all channels is always sent to/from the Fireface-800.
426
427 Note that when register 0x801c0000 is read it functions as the device status
428 register.  It is read during streaming setup, but obviously it bears no
429 relationship to the channel mute status.
430
431 Streaming end register (FF800: 0x200000034, FF400: CBA+0x4):
432
433 On the FF800, streaming is stopped by writing 3 zeroed quadlets to
434 consecutive registers starting at address 0x200000034.  For the FF400 one
435 writes 3 zeroed quadlets to consecutive registers from CBA+0x4, followed
436 by a 0x00000001 to CBA+0x10 (making a 4-quadlet write in total).
437
438
439 Iso data
440 --------
441
442 Audio/midi data is sent and received on isochronous channels previously
443 configured by the driver.  On a dedicated bus with nothing else present, the
444 stream to the fireface is sent on iso channel 0 while data from the fireface
445 is sent on iso channel 1.
446
447 No CIP header is included in the iso data packet.  Fireface data follows
448 immediately after the standard 2-quadlet firewire iso packet header.
449
450 Each iso packet contains a number of samples across all 28 device channels.
451 For 1x rates, 7 samples per channel seem to be sent.  Thus the size of
452 the data portion of a 1x iso packet is 28*4*7 = 784, with a total packet
453 size being 784 + 8 = 792.
454
455 The data is sent with one audio channel per quadlet.  The audio data is a 24
456 bit integer stored in the most-significant 3 bytes of a quadlet.  The LSB
457 (low byte) of certain channels in the stream sent by the Fireface is used to
458 send synchronising information:
459
460   Low byte of channel 6 = current frame
461   Low byte of channel 7 = phase
462   Low byte of channel 1 = rx sample counter, low byte
463   Low byte of channel 4 = rx sample counter, high byte
464   Low byte of channel 0 = tx buffer size, low byte
465   Low byte of channel 5 = tx buffer size, high byte
466   Low byte of channel 2 & 3 = unknown (midi?)
467
468 The low byte data from channels 0-7 is repeated in channels 8-15 and 16-23
469 respectively, with channels 24-27 containing the low byte data from channels
470 0-3.  This repetition holds for the low bytes of channels 2-3 in all data
471 seen so far, it might not necessarily be the case in general - it depends
472 what the low byte data from channels 2 and 3 are used for.
473
474 The rx sample counter appears to be used to detect missed samples.  The
475 current frame and phase from a received packet is used in conjunction with
476 the stored values of these from the previous frame to track the phase of
477 the audio clock.
478
479 A "frame" consists of a fixed number of samples across all channels of the
480 device.  At 1x rates this appears to be 7, but it might not be fixed.  Even
481 though this is the same as the number of samples per channel per packet, a
482 given packet can experience a change in the "current frame" part way
483 through.  In other words, the "current frame" is not necessarily constant
484 for all samples in a packet.
485
486
487 Mixer controls
488 --------------
489
490 The matrix mixer on the Fireface-800 is controlled using a block of
491 registers starting at 0x80080000.  A 28x28 matrix mixer is implemented
492 allowing any device input to be sent to any device output.  The pan controls
493 are synthesised by manipulating the "left/right" controls.
494
495 In each sub-block, the order of channels is in fireface numeric order.  That
496 is, Analog 1-10, SPDIF, ADAT1 1-8, ADAT2 1-8.
497
498 0x80080000 - 0x8008006c: input channel sends to Analog 1 output.
499 0x80080080 - 0x800800ec: playback channel sends to Analog 1 output.
500 0x80080100 - 0x8008016c: input channel sends to Analog 2 output.
501 0x80080180 - 0x800801ec: playback channel sends to Analog 2 output.
502 :
503 0x80081b00 - 0x80081b6c: input channel sends to ADAT2-8 output.
504 0x80081b80 - 0x80081bec: playback channel sends to ADAT2-8 output.
505
506 0x80081f80: matrix mixer analog 1 output fader
507 0x80081f84: matrix mixer analog 2 output fader
508 :
509 0x80081fec: maxtrix mixer ADAT2-8 output fader
510
511 Each fader control ranges from 0x00000000 (-inf) through 0x00008000 (0.0dB)
512 and up to a maximum setting of 0x00010000 (+6.5dB).
513
514 Mute is synthesised by setting the respective send value to -inf (0).
515 Conversely, solo is synthesised by muting all sends to the selected bus
516 except the send being soloed.
517
518 Note that a different scale is used when writing mixer settings into flash.
519 Fader values are stored as 16 bit numbers, with 803 (0x0323) seemingly
520 representing 0 dB.  Other details of the scale used are still to be deduced.
521
522
523 Metering values
524 ---------------
525
526 The Fireface-800 appears to provide hardware support for metering.  The RME
527 mixer application periodically sends block read requests for register
528 0x80100000 with a size of 0x3f8.  What is returned is a set of two
529 datablocks with data in little-endian (least significant bit/word first)
530 format.  The first block contains arrays of 64-bit floating point numbers
531 representing channel amplitude with decay, presumedly useful for metering
532 display.  Arrays are:
533
534   28-element array for input channel amplitude with decay
535   28-element array for playback amplitudes with decay (educated guess)
536   28-element array for output amplitudes with decay
537
538 The second data block contains signed 32 bit integers representing the input
539 amplitudes without decay.  Valid range is 0 - 0x7ffffff.  Again there are 3
540 arrays:
541
542   28-element array for input channel ampltude
543   28-element array for playback amplitudes (educated guess)
544   28-element array for output amplitudes
545
546 At the end of this second block are two zero quadlets.  Their purpose is
547 unknown at this stage.
548
549 In each 28-element array the channel data appears in standard fireface
550 order.
551
552
553 Host LED
554 --------
555
556 The "host" LED of the FF800 is controlled by a dedicated register at
557 0x200000324.  Note that this register address goes beyond the 32-bit
558 boundary.
559
560 On the FF400 the host LED is controlled internally.  On power up it is
561 turned on.  Once the host PC programs the configuration registers with
562 valid values the host LED will automatically turn off.
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