root/trunk/libffado/doc/rme_notes/rme_config_register_map.txt

Revision 2802, 36.9 kB (checked in by jwoithe, 3 years ago)

Cosmetic: "Firewire" becomes "FireWire?".

Officially both the "F" and "W" were capitalised in the FireWire? name, so
reflect this throughout FFADO's source tree. This mostly affects comments.

This patch originated from pander on the ffado-devel mailing list. To
maintain consistency, the committed version has been expanded to include
files not originally included in the original patch.

Line 
1 RME Fireface-400 / Fireface-800 register map
2 ============================================
3
4 Version: 0.26
5 Author: Jonathan Woithe
6 Date: 11 April 2013
7
8
9 Definitions
10 -----------
11
12 CBA = Command Buffer Address
13 FF800 = Fireface-800
14 FF400 = Fireface-400
15
16 Multi-byte values sent to/from the Fireface in async packets are generally
17 little endian - that is, the device interprets quadlets in asynchronous
18 packets as little endian even though the bus definition is big-endian.  If
19 writing a driver for use on a little endian machine, this means that a lack
20 of byte swapping (to account for the bus endianness standard) will cause bit
21 0 on the host to be bit 0 on the device.
22
23 By default, FFADO however adheres to the bus standards and byteswaps on
24 little endian machines.  Under this regime, bit 0 on the host will in fact
25 be read by the device as the least significant bit in the most significant
26 byte.
27
28 In order to retain consistency with device documentation, the FFADO RME
29 driver currently sends async packet data in the little endian format which
30 the RME device expects.  Although this is technically wrong (in so far as
31 the FireWire standard is concerned), at this stage it is considered that
32 introducing an endianness difference between the FFADO driver and the
33 documentation is likely to result in maintenance issues down the track.
34
35 The bit maps in this document regarding the configuration registers are
36 written from the device's point of view.  That is, the values quoted should
37 be sent to the device in little endian format unless otherwise stated.
38
39 Curiously enough, preliminary investigations suggest that audio data appears
40 to be sent on the bus in big endian format (although this is to be
41 confirmed).
42
43 The FF800 includes a number of instrument options for input 1 which are
44 described using several different terms interchangeably:
45  - "Drive" (also referred to as "fuzz") activates 25 dB extra gain
46  - "Speaker emulation" (also referred to as "filter") removes LF noise and
47    some HF
48  - "Limiter" activates a soft-limiter with a threshold of -10 dBFS.  This
49    can only be switched off if the Front input is used for channel 1.
50
51
52 Device address space location
53 -----------------------------
54
55 While some register addresses are common between the two interfaces, the
56 absolute addresses of the settings and control differ.  These are defined
57 relative to the device "command buffer" address:
58
59   FF800: command buffer address (CBA) = 0xfc88f000
60   FF400: command buffer address (CBA) = 0x80100500
61
62 The location of the configuration (settings) registers relative to the
63 command buffer is consistent across devices:
64
65   conf reg 1 address = command buffer address + 5*4
66
67 For a FF800 this equates to 0xfc88f014.
68
69
70 Controlling sample rate (DDS)
71 -----------------------------
72
73 Sample rate is controlled by writing the desired sample rate in Hz to the
74 sample rate control register located at offset 0 from the command buffer
75 address (0xfc88f000 on a FF800).  The hardware DDS allows a wide range of
76 frequencies to be requested (possibly anything from 30 kHz up to 210 kHz).
77 The more common rates are of course 32k, 44.1k, 48k, the pull-up/down rates
78 (44.056k, 44.144k, 45.937k, 46.080k, 47.952k, 48.048k) and the corresponding
79 2x and 4x rates.
80
81 Software connecting to the Fireface device is restricted to the normal rates
82 of 32k, 44.1k, 48k and the related 2x and 4x rates.
83
84 If the device is in master clock mode and the user has not made an explicit
85 DDS setting, the hardware DDS will be determined by the sampling rate
86 requested by the application opening the device.  If a DDS frequency has
87 been requested by the user the actual rate used by the device will be that
88 DDS frequency regardless of what the application has asked for.  In this
89 case a device open will only succeed if the software has requested a speed
90 whose multiplier matches the DDS configuration.
91
92 If the device is locked to an external clock, a device open will succeed
93 only if the multiplier of the requested sampling rate matches that of the
94 external rate.
95
96 The device status registers allow the PC to determine the sampling rate when
97 an external clock is in use.  However, there is no way to read the sampling
98 rate when in master clock mode.  It is therefore necessary to cache this in
99 the driver so it can be provided when requested.
100
101 In terms of multipliers the RME treats sample rates greater than 112000 Hz
102 as 4x rates, with rates greater than 56000 Hz as 2x rates.  Rates less than
103 30000 Hz and greater than 210000 Hz are invalid.
104
105
106 Configuration registers 1, 2 and 3
107 ----------------------------------
108
109 Most RME device configuration is done using configuration registers 1, 2
110 and 3.  For the ff800 these are:
111
112   config1 = configuration register 1 (FF800: 0xfc88f014, FF400: 0x80100514)
113   config2 = configuration register 2 (FF800: 0xfc88f018, FF400: 0x80100518)
114   config3 = configuration register 3 (FF800: 0xfc88f01c, FF400: 0x8010051c)
115
116 In essence the configuration registers start at CBA+5*4 for both interfaces.
117
118 When making a configuration change these registers are always written in a
119 block of 12 bytes starting at 0xfc88f014 with a block write operation.
120
121 Configuration register 1 (FF800: 0xfc88f014, FF400: 0x80100514):
122
123   bits 31-18: unknown, set to 0
124   bits 17-16: Phones level:
125     00 = +4 dBu
126     01 = -10 dBV
127     10 = hi-gain
128   bits 15-13: unknown, set to 0
129   bits 12-10: Output level control (part 1 of 2: FPGA LED drive):
130     001 = hi-gain
131     010 = +4dBU
132     100 = -10dBV
133   bit 9: FF800: Instr option: Drive (part 1 of 2: FPGA LED drive) (active = 1)
134          FF400: Channel 3 "instrument" switch
135   bit 8: FF800: Phantom power, mic 10 (active = 1)
136          FF400: Channel 3 "pad" switch
137   bit 7: Phantom power, mic 8 (active = 1)
138   bit 6: unknown, set to 0
139   bits 5-3: Input level control (part 1 of 2: FPGA LED drive):
140     001 = lo-gain
141     010 = +4dBU
142     100 = -10dbV
143   bit 2: FF800: Instrument option: speaker emulation (aka "filter") (part 1
144            of 2: FPGA LED drive) (active = 1)
145          FF400: Channel 4 "instrument" switch
146   bit 1: FF800: Phantom power, mic 9 (active = 1)
147          FF400: Channel 4 "pad" switch
148   bit 0: Phantom power, mic 7 (active = 1)
149
150 Configuration register 2 (FF800: 0xfc88f018, FF400: 0x80100518):
151
152   bits 31-12: unknown, set to 0
153   bit 11: Input #1 front switch (active = 1)
154   bit 10: unknown, set to 0
155   bit 9: Instrument option: Drive (part 2 of 2: CPLD function) (active = 0)
156   bit 8: Input #8 rear switch (active = 1)
157   bit 7: Input #8 front switch (active = 1)
158   bit 6: Input #7 rear switch (active = 1)
159   bit 5: Input #7 front switch (active = 1)
160   bits 4-3: Output level control (part 2 of 2: CPLD function):
161     00 = undefined
162     01 = -10dBV
163     10 = hi-gain
164     11 = +4dBU
165   bit 2: Input #1 rear switch (active = 1)
166   bits 1-0: Input level control (part 2 of 2: CPLD function):
167     00 = lo-gain
168     01 = undefined
169     10 = +4dBU
170     11 = -10dbV
171
172 Configuration register 3 (FF800: 0xfc88f01c, FF400: 0x8010051c):
173   bit 31: "Drop and stop": always set to 1
174   bit 30: Unit option: TMS (active = 1)
175   bits 29-27: set to 0
176   bit 26: set to 1 for FF400, 0 for FF800
177   bits 25-17: set to 0
178   bit 16: P12DB_AN0 (normally set to 0)
179   bit 15: set to 0
180   bit 14: Toggle TCO (normally set to 0)
181   bit 13: Word clock single speed: 0 = off, 1 = on
182   bits 12-10: Sync reference source:
183     000 = ADAT1
184     001 = ADAT2
185     011 = SPDIF
186     100 = Word clock
187     101 = TCO
188   bit 9: SPDIF input source: 0 = coax, 1 = ADAT2 port
189   bit 8: SPDIF output option: ADAT2
190   bit 7: SPDIF output option: non-audio
191   bit 6: SPDIF output option: emphasis
192   bit 5: SPDIF output option: professional
193   bit 4: QS control (set to 1)
194   bit 3: DS control (set to 1)
195   bit 2: Freq1 control (set to 1)
196   bit 1: Freq0 control (set to 1)
197   bit 0: Clock mode: 0 = Master, 1 = Autosync
198
199 On the FF400, writing to these registers with valid values for the first
200 time after power up has the side effect of extingishing the "Host" LED.
201
202
203 Device status registers
204 -----------------------
205
206 There are up to 4 read-only device status registers available, starting at
207 address 0x801c0000.  There seems to be a slight difference in the mapping of
208 status register 0 depending on the size of the read.  If only 2 registers
209 (quadlets) are read the "general" layout is assumed.  If on the other hand 4
210 registers are used (used when determining the status of the device's
211 streaming system) the layout of register 0 is slightly different.
212
213 Status register 0:
214   bits 9-0: on a 2-quadlet read these bits are all zero
215   bits 9-0: on a 4-quadlet read when in autosync mode, these bits contain
216             SR/250, where SR is the sample rate to be passed to the
217             streaming subsystem when starting streaming.
218   bit 10: ADAT1 lock achieved
219   bit 11: ADAT2 lock achieved
220   bit 12: Device is synced to ADAT1
221   bit 13: Device is synced to ADAT2
222   bits 17-14: SPDIF frequency:
223     0000 = undefined    0101 = 88.2k
224     0001 = 32k          0110 = 96k
225     0010 = 44.1k        0111 = 128k
226     0011 = 48k          1000 = 176.4k
227     0100 = 64k          1001 = 192k
228   bit 18: Device is synced to SPDIF
229   bit 19: Over detected
230   bit 20: SPDIF lock achieved
231   bit 21: undefined (read as zero)
232   bits 24-22: Primary sync source:
233     000 = ADAT1         100 = Word clock
234     001 = ADAT2         101 = TCO
235     011 = SPDIF
236   bits 28-25: autosync (external) frequency (defined as for SPDIF frequency)
237   bit 29: Device is synced to word clock
238   bit 30: Word clock lock achieved
239   bit 31: undefined (read as zero)
240
241 Status register 1:
242   bit 0: master clock mode active
243   bits 21-1: undefined
244   bit 22: Device is synced to TCO
245   bit 23: TCO lock achieved
246   bits 31-24: undefined
247
248 Status register 2:
249   bits 31-0: (FF800 only) firewire iso channel used for data from FF800 to PC
250
251 Status register 3:
252   bits 31-0: unused
253
254
255 Interfacing to device flash
256 ---------------------------
257
258 To preserve the device's settings across power cycles the settings are
259 stored in a flash memory on the device.  This is read during driver
260 initialisation to ensure the driver's status agrees with that of the device.
261
262 There are several classes of things stored in flash: operational settings,
263 volumes (ie: the mixer status) and configuration/firmware.  Device settings
264 start at address 0x3000f0000 on the FF800 and 0x00060000 on the FF400; mixer
265 data starts at 0x3000e0000 on the FF800 and 0x00070000 on the
266 FF400.
267
268
269 Reading blocks from the flash (flash command 0x2)
270
271 For the FF800 the entire buffer is read directly from flash as a single
272 block if the block is less than a sector (256 bytes, 64 quadlets).  Polling
273 for "device not busy" should commence after a wait of 5 ms.  For anything
274 larger, writes are split into sector-sized sub-blocks.
275
276 For the FF400, the buffer is read in 32-quadlet sub-blocks.  A partial block
277 is read at the end if the total buffer size is not a multiple of
278 32-quadlets.  To read a sub-block, the address is placed in register
279 0x80100288 and the sub-block size (in bytes) in 0x8010028c.  A 0x02 is
280 then written to CBA+(8*4) to initiate the read.  Polling for "device not
281 busy" should commence after a wait of 2 ms.  Once not busy the data is
282 available for reading from 0x80100290.
283
284
285 Writing blocks to the flash (flash command 1)
286
287 For the FF800, the buffer is written to flash in 256-byte (64 quadlet)
288 sectors.  Polling for "device not busy" should commence after a wait of 5
289 ms.  A write request for a length less than a sector will be honoured by the
290 device (this is done when writing device settings).
291
292 For the FF400, the buffer is written in 32-quadlet (128-byte) sub-blocks via
293 a bounce buffer.  If the final sub-block is not 32-quadlets the write is
294 only as big as the sub-block (that is, no padding takes place).  The
295 sub-block data to be written is sent to the block starting at 0x80100290.
296 The 2-quadlet register at 0x80100288 is set with the flash address to write
297 the block to and the size (in bytes) of the data block.  Finally, a 0x1 is
298 written to CBA+(8*4) to initiate the write.  Polling for "device not busy"
299 should commence after a wait of 2 ms.
300
301
302 Getting other data from flash
303
304 There are a few other commands issued to the flash memory system for
305 obtaining data about the connected interface:
306
307  * Device revision
308
309    On the FF800 this is read directly from register 0x200000100.
310
311    On the FF400, 0xf is written to CBA+(8*4).  Poll for "not busy" after a
312    wait of 2ms.  Once not busy the revision is read from register
313    0x80100290.
314
315
316 Erasing the flash
317
318 The flash is divided into sections and it is possible to erase each section
319 separately.  Therefore one only has to erase section of interest when
320 changing something.
321
322 On the FF400, erasure is controlled by writing a special magic number to
323 the the flash control register (CBA+8*4):
324   Erase volume: write 0xe
325   Erase settings: write 0xd
326   Erase configuration (firmware): write 0xc
327
328 On the FF800, erasing is controlled by writing 0 to the applicable register:
329   Erase volume: register is 0x3fffffff4
330   Erase settings: register is 0x3fffffff0
331   Erase firmware: register is 0x3fffffff8
332   Erase configuration: register is 0x3fffffffc
333
334 It's not clear what the distinction between "configuration" and "firmware"
335 is.  The FF400 appears to only support "configuration" but treats this as
336 "firmware".  The FF800 supports both as distinct options.
337
338 After issuing the erase command one should wait for 500 ms before polling
339 the device for the "not busy" status.
340
341
342 Waiting for flash
343
344 When interacting with the device's flash memory one must wait for the
345 completion of an operation before attempting another.  The location of the
346 "device busy" flag differs between the FF400 and FF800.
347
348 On the FF800 is part of the quadlet register at 0x801c0004 (part of the
349 read-only status register block beginning at 0x801c0000).  The device is
350 ready to accept another command when bit 30 is set.
351
352 On the FF400 the wait state is found by reading a quadlet from CBA+8*4.
353 If this quadlet is zero the FF400 is ready to accept another command.
354
355 Most device flash operations have a minimum time to complete.  There's no
356 point in polling the device busy flag until at least this much time has
357 elapsed.
358
359
360 Device settings format
361 ----------------------
362
363 The device settings are stored in flash as an array of 59 32-bit unsigned
364 integers.  These are:
365   0 - Device ID (FF400=0x77e1f4ea)
366   1 - Device revision (FF400=0x004af3d8)
367   2 - ASIO latency (FF400=0x00000001)
368   3 - Samples per frame (FF400 default is 0x30)
369   4 SPDIF input mode (1=coax, 0=optical)
370   5 SPDIF output emphasis active
371   6 SPDIF output is "professional" (ie: AES/EBU)
372   7 Clock mode (0=master, 1=autosync)
373   8 SPDIF output is non-audio (eg: AC3 passthrough)
374   9 Sync reference
375  10 SPDIF output mode (0=coax only, 1=coax+optical)
376  11 - Check input
377  12 - Status (FF400 idle=0x77e691d0)
378  13 - Register[4] (FF400 = 0x004adbc8,0x001377c0,0x000301ee,0x00000001)
379  17 - Iso receive channel (FF400=0x7ffde000)
380  18 - Iso transmit channel (FF400=0x77f43664)
381  19 - Timecode (FF400 example: 0x004b35c8)
382  20 - Device type (FF400=0x00000001)
383  21 - Number of devices (FF400=0x77f43664)
384  22 TMS (FF400=0x00000000)
385  23 - Speed (FF400=0x00000000)
386  24 - Channels available (high) (FF400=0x0012f2e4)
387  25 - Channels available (low) (FF400=0x00000000)
388  26 Limit bandwidth setting (0=all channels on, 1=no adat2, 2=analog+spdif
389       only, 3=analog only)
390  27 - Bandwidth allocated (FF400=0x00000000)
391  28 Stop on dropout (FF400=0x00000000)
392  29 Input level (0=lo-gain, 2=+4dBU, 1=-10dBV)
393  30 Output level (2=hi-gain, 1=+4dBU, 0=-10dBV)
394  31 Mic level [0] - FF400: Phoneslevel-1
395                     FF800: Channel 7 front/rear select (0=rear, 1=front,
396                            2=front+rear)
397  32 Mic level [1] - FF400: unused
398                     FF800: Channel 8 front/rear select (0=rear, 1=front,
399                            2=front+rear)
400  33 Mic phantom power [4]
401  37 Instrument - FF400: unused
402                  FF800: Channel 1 front/rear selector (0=rear, 1=front,
403                         2=front+rear)
404  38 Filter (aka speaker emulation)
405  39 Fuzz (aka drive)
406  40 - Sync align
407  41 - Device index (FF400=0x77e24d0d)
408  42 - Advanced dialog (FF400=0x000201f8) [but might be related to TCO control)
409  43 Sample rate (eg: 0x0000ac44) [set to 0x00000000 unless DDS enabled]
410  44 - Interleaved (FF400=0x00000000)
411  45 - Sn (FF400=0x77e14925)
412  46 Word clock single speed (1=single speed)
413  47 - Number of channels (FF400=0x000000f0)
414  48 - Dropped samples
415  49 p12db_an[0] - Disable limiter, settable only if channel 1 front jack active
416  50 - p12db_an[1-9]
417
418 "-" = elements not used (under MacOSX at least)
419
420 Total size: 59 quadlets
421
422 The default state of these quadlets is 0xffffffff, which is taken to
423 indicate that the respective setting has not been written to flash. This in
424 turn causes the driver to assume its own default value.  While these
425 settings can be changed in real time by writing to the relevant control
426 registers, these are not persistent across device power cycles.  To make
427 them persistent it is necessary to store them into the flash.
428
429
430 Flash mixer settings layout
431 ---------------------------
432
433 Mixer (volume) data starts at 0x3000e0000 on the FF800 and 0x00070000 on the
434 FF400.  There are several control groups in the mixer:
435   0xe0000 (FF800): "mixer shadow", FF800 only
436   0xe2000 (FF800) / 0x70000 (FF400), 0x0800 bytes: 16-bit volume array
437   0xe2800 (FF800) / 0x70800 (FF400), 0x0800 bytes: 16-bit pan array
438   0xe3000 (FF800) / 0x71000 (FF400), 0x0040 bytes: 16-bit "vol3" array +
439     "enable MIDI control" + "submix" + zero padding to 64 quadlets
440
441 All group allocations are written in their entirety (that is, 0x0800 bytes),
442 with zero padding on the end as needed.  Each write is grouped in sectors,
443 with each sector being 256 bytes (64 quadlets).
444
445 It is not known why the "mixer shadow" is stored in the case of the FF800.
446 It comprises a copy of the 32-bit matrix mixer settings (see "Fireface-800
447 mixer controls" below), and the information is essentially a duplicate of
448 what's in the "volume" and "pan" arrays.  In any case, what's done is done.
449 The "mixer shadow" values are written in 64-quadlet (256-byte) blocks, one
450 per hardware output channel.  The FF800 has 28 hardware input channels (I)
451 and 28 software playback channels (P).  Each output has a 64-quadlet block
452 formatted as follows:
453
454   Faders for physical inputs 1..I, zero pad to 32-quadlet boundary
455   Faders for software playbacks 1..P, zero pad to 32-quadlet boundary
456
457 There are 28 hardware input/output channels on the FF800 and 18 for the
458 FF400.
459
460 The "volume" and "pan" arrays are arranged in blocks of N (32 for FF800, 18
461 for FF400) 16-bit elements.  Each block contains the volume/pan value for
462 each of N possible physical inputs or playbacks when sent to one of the N/2
463 physical stereo output pairs.  Elements are ordered in the standard Fireface
464 channel index order.  The arrangement of the blocks are as follows:
465
466   Inputs 1..N to output pair 1+2
467   Playbacks 1..N to output pair 1+2
468   Inputs 1..N to output pair 3+4
469   Playbacks 1..N to output pair 3+4
470   :
471   Inputs 1..N to output pair N/2-1 and N/2
472   Playbacks 1..N to output pair N/2-1 and N/2
473
474 In the case of the FF800, N (32) is greater than the number of physical
475 inputs and mono outputs available (28).  Array elements corresponding to
476 non-existent inputs, outputs or playbacks are filled with zeros.
477
478 The "vol3" array represents the hardware output volume settings.  The 16-bit
479 volume data for each of the hardware output channels is included in the
480 standard Fireface channel index order.  The array has room for 30 outputs
481 while the FF400/FF800 has only 18/28 outputs; elements corresponding to
482 outputs not physically present are set to zero.  In addition, a boolean
483 indicating whether MIDI control is enabled is stored in zero-based array
484 index 30 while a submix index is stored in array index 31 (array elements
485 are considered 16-bit here).  The meaning of the submix index isn't known;
486 it's thought that the GUI mixer applications in other systems use this as a
487 convenient place to store the submix index that the user was last editting
488 (assuming they were editting in submix mode).
489
490 All 16-bit values are written in little endian byte order.
491
492 The "volume" and "vol3" values are unsigned 16-bit values:
493   0x0000 = -inf  (minimum)
494   0x0255 = -6 dB
495   0x0323 =  0 dB
496   0x03ff =  6 dB (maximum)
497
498 When panned hard left or right, the value F written to the flash as a
499 channel's volume given a fader value of V (0..0x10000) appears to be:
500
501   F = (1023.0/3) * ln( V*(exp(3)-1)/65536 + 1)
502
503 F is rounded to the nearest integer value.
504
505 The "pan" values are unsigned 16-bit values.  0x0000 is hard left, 0x0080 is
506 centre and 0x0100 is hard right.  Therefore if the pan value is represented
507 as a floating point number Pf from 0.0 (hard left) to 1.0 (hard right), the
508 pan value Pv written to flash will be
509
510   Pv = 0x0100 * Pf
511
512 In the hardware, each channel of a stereo pair is controlled independently
513 the mixer registers.  It is therefore necessary to convert bidirectionally
514 between fader value pairs and the volume/pan pair as used in the flash.  Let
515 V0 and V1 be the fader value (0..0x10000) for each of the two channels.  The
516 volume (V) and pan (P) values can be calculated as follows.
517
518    V = V0 + V1
519
520   Pf = V1 / (V0 + V1)
521
522    P = 0x0100 * Pf
523
524 V is then transformed into the equivalent flash value F according to
525 the expression given previously:
526
527   F = (1023.0/3) * ln( V*(exp(3)-1)/65536 + 1)
528
529 When starting with the volume/pan pair, V is first calculated from F by
530 rearranging the above equation.  Pf is then calculated:
531
532   Pf = P / 0x100
533
534 This allows V0 and V1 to be found:
535
536   V0 = V * (1 - Pf)
537
538   V1 = V * Pf
539
540 Careful attention to round-off is required to ensure that flash and fader
541 values remain unchanged through fader-flash-fader and flash-fader-flash
542 round trips.
543
544 User interfaces under other operating systems include a "pan law" control
545 which sets the gain when panned to centre.  This setting is not sent to the
546 device at any time; the default in the mixer software is -6 dB.  Other
547 options are -4.5 dB, -3 dB and 0 dB.  Changing these affects the values sent
548 to the individual mixer registers (and hense the "mixer shadow"), but not
549 the values stored in the "volume" and "pan" flash arrays.  In the case of
550 the FF400, the power on state obtained from flash is therefore independent
551 of the pan law control (the FF800 stores the mixer shadow data and could
552 make use of it if it wanted to).  Experimentation shows that when powering
553 up, the FF400 assumes a pan law of -6 dB when mapping from the volume/pan
554 flash arrays to individual mixer element registers.  Tests are still to be
555 done on the FF800 to see if it uses the "mixer shadow" values instead of the
556 volume/pan arrays.
557
558
559 TCO (TimeCode Option)
560 ---------------------
561
562 The TCO is an optional card for the FF800 which adds video timecode
563 generation and clock locking capabilities to the FF800.  It is controlled by
564 writing a block of 4 quadlets to register 0x810f0020 while its status can be
565 retrieved by reading a block of 4 quadlets from register 0x801f0000.
566
567 The configuration space is as follows.
568
569 Quadlet 0 (written to register 0x810f0020):
570   bit 31: MTC active if set to 1
571   bits 30-0: reserved (equal zero)
572
573 Quadlet 1 (written to register 0x810f0024):
574   bits 31-12: reserved (equal to zero)
575   bits 11-10: LTC format (00=24fps, 01=25fps, 10=29.97fps, 11=30fps)
576   bit 9: dropframe active
577   bit 8: set timecode request
578   bit 7: reserved (set to 0)
579   bit 6: PAL format video input
580   bit 5: NTSC format video input
581   bit 4-3: reserved (set to 0)
582   bits 2-1: word clock input rate (00=1x, 01=2x, 10=4x)
583   bit 0: reserved (set to 0)
584
585 Quadlet 2 (written to register 0x810f0028):
586   bit 31: set sampling frequency from application
587   bits 30-29: input select (00=wordclock, 01=video, 10=LTC)
588   bit 28: input termination active
589   bit 27: Base frequency (0=44.1 kHz, 1=48 kHz)
590   bit 26: Pull up flag
591   bit 25: Pull down flag
592   bit 24: Pull up/down amount (0=0.1%, 1=4.0%)
593   bit 23: reserved (set to 0)
594   bit 22: Flywheel select
595   bit 21: Jam sync select
596   bits 20-19: dropframes select (unused, set to 0)
597   bits 18-17: word clock conversion (00=1:1, 01=44.1->48, 10=48->44.1)
598   bit 16: set TC run
599   bits 15-0: reserved, set to 0.
600
601 Quadlet 3:
602   bits 31-0: reserved, set to 0
603
604 The 4 quadlets returned by a TCO status query are mapped as follows.
605
606 Quadlet 0:
607   bit 31: set to 1
608   bits 30-24: LTC, hours field in BCD(*)
609   bit 23: set to 1
610   bits 22-16: LTC, minutes field in BCD
611   bit 15: set to 1
612   bits 14-8: LTC, seconds field in BCD
613   bit 7: set to 1
614   bits 6-0: LTC, frames field in BCD
615
616 Quadlet 1:
617   bit 31: set to 1
618   bits 30-24: reserved (equal to zero)
619   bit 23: set to 1
620   bits 22-16: reserved (equal to zero)
621   bit 15: set to 1
622   bits 14-12: reserved (equal to zero)
623   bits 11-10: LTC format (00=24fps, 01=25fps, 10=29.97fps, 11=30fps)
624   bit 9: dropframe active
625   bit 8: reserved (read as zeros)
626   bit 7: set to 1
627   bit 6: PAL format video input
628   bit 5: NTSC format video input
629   bit 4: Word clock input valid (0=invalid, 1=valid)
630   bit 3: LTC input valid (0=invalid, 1=valid)
631   bits 2-1: reserved (read as zeros)
632   bit 0: TCO lock flag (0=no lock, 1=locked)
633
634 Quadlet 2
635   bit 31: set to 1
636   bits 30-24: reserved (equal to zero)
637   bit 23: set to 1
638   bits 22-16: reserved (equal to zero)
639   bit 15: set to 1
640   bits 14-8: upper 7 bits of PLL phase
641   bit 7: set to 1
642   bits 6-0: the lower 7 bits of the PLL phase
643
644 Quadlet 3:
645   bit 31: set to 1
646   bits 30-16: reserved
647   bit 15: set to 1
648   bits 14-0: set to 0
649
650 Notes:
651  (*) BCD is Binary Coded Decimal.  The high nibble (which is only 3 bits in
652      these cases) contains the "tens" digit while the lower nibble contains
653      the "units" digit.
654
655 The calculation of the PLL phase from quadlet 2 (q2) is as follows:
656
657   phase = (q2 & 0x7f) + ((q2 & 0x7f00) >> 1)
658
659 which then allows the incoming frequency to be calculated using
660
661   freq = (25000000 * 16) / phase
662
663 To detect the presence of a TCO in a FF800, read the 4 TCO status quadlets.
664 If a TCO is present:
665   - bits 31, 23, 15 and 7 in quadlets 0, 1 and 2 will be 1, AND
666   - bits 31 and 15 in quadlet 3 will be 1, AND
667   - bits 14 to 0 in quadlet 3 will be 0
668
669
670 Streaming control registers
671 ---------------------------
672
673 There appears to be a number of registers involved in the setup of device
674 streaming.
675
676 Device (streaming) initialisation register (FF800: 0x20000001c, FF400: CBA)
677
678 This register comprises the 3 quadlets starting at address 0x20000001c on
679 the FF800 and the 5 quadlets starting at the CBA on the FF400.  The first
680 quadlet contains the sample rate in Hz.  The second quadlet is mapped as
681 follows:
682   bits 31-11 = number of audio channels
683   bits 10-0  = iso tx channel (PC to interface)
684 In all local tests with a FF800 the value of this quadlet was always equal
685 to 0x0000e000 (28 channels, PC transmits on iso channel 0).
686
687 The third quadlet is mapped as follows.
688   bits 10-0 = number of audio channels
689   bit 11    = speed flag; set to 1 if firewire bus is at 800 Mbps
690 In local tests with a FF800 the value of this register was always 0x0000001c
691 (28 channels, 400 Mbps firewire bus).
692
693 The forth and fifth quadlets (used only by the FF400) are zero.
694
695 After this register is configured, 4 quadlets are read starting from
696 0x801c0000.  When read, these are the device status registers.
697
698 Device (streaming) start register (FF800: 0x200000028, FF400: CBA+0x0c):
699
700 The start of streaming differs between the FF400 and FF800 in more than just
701 the address of the relevant register.  On the FF800 this register is mapped
702 as follows:
703   bits 10-0 = number of audio channels
704   bit 11    = bus speed flag; set to 1 if firewire bus is at 800 Mbps
705 On a FF400 the register is as follows:
706   bits 4-0  = number of audio channels
707   bits 9-5  = iso tx channel (PC to interface)
708 During initial testing with a FF800 the value of this register was always
709 0x0000001c (28 audio channels, PC tx on iso channel 0).
710
711 Channel mute setup register (write to 0x801c0000):
712
713 After writing to the streaming start register, 0x70 bytes (28 quadlets) are
714 written starting at 0x801c0000.  Each quadlet represents one channel on the
715 Fireface800.  A value of 1 mutes the respective channel - indeed on closing
716 down streaming each quadlet is set to 1.  During startup some values are set
717 to zero - the ones set to zero may be determined by the channels which have
718 active software data sources although this is yet to be confirmed with more
719 testing.  Irrespective of the setting of these registers it appears that
720 data for all channels is always sent to/from the Fireface-800.
721
722 Note that when register 0x801c0000 is read it functions as the device status
723 register.  It is read during streaming setup, but obviously it bears no
724 relationship to the channel mute status.
725
726 Streaming end register (FF800: 0x200000034, FF400: CBA+0x4):
727
728 On the FF800, streaming is stopped by writing 3 zeroed quadlets to
729 consecutive registers starting at address 0x200000034.  For the FF400 one
730 writes 3 zeroed quadlets to consecutive registers from CBA+0x4, followed
731 by a 0x00000001 to CBA+0x10 (making a 4-quadlet write in total).
732
733
734 Iso data
735 --------
736
737 Audio/midi data is sent and received on isochronous channels previously
738 configured by the driver.  On a dedicated bus with nothing else present, the
739 stream to the fireface is sent on iso channel 0 while data from the fireface
740 is sent on iso channel 1.
741
742 No CIP header is included in the iso data packet.  Fireface data follows
743 immediately after the standard 2-quadlet firewire iso packet header.
744
745 Each iso packet contains a number of samples across all 28 device channels
746 (18 channels in the case of the ff400).  For 1x rates, 7 samples per channel
747 seem to be sent.  Thus the size of the data portion of a 1x iso packet is
748 28*4*7 = 784, with a total packet size being 784 + 8 = 792.
749
750 The data is sent with one audio channel per quadlet.  The audio data is a 24
751 bit integer stored in the most-significant 3 bytes of a quadlet.  The LSB
752 (low byte) of certain channels in the stream sent by the Fireface is used to
753 send synchronising information:
754
755   Low byte of channel 6 = current frame
756   Low byte of channel 7 = phase
757   Low byte of channel 1 = rx sample counter, low byte
758   Low byte of channel 4 = rx sample counter, high byte
759   Low byte of channel 0 = tx buffer size, low byte
760   Low byte of channel 5 = tx buffer size, high byte
761   Low byte of channel 2 & 3 = unknown (midi?)
762
763 The low byte data from channels 0-7 is repeated in channels 8-15 and 16-23
764 respectively, with channels 24-27 containing the low byte data from channels
765 0-3.  This repetition holds for the low bytes of channels 2-3 in all data
766 seen so far, it might not necessarily be the case in general - it depends
767 what the low byte data from channels 2 and 3 are used for.
768
769 The rx sample counter appears to be used to detect missed samples.  The
770 current frame and phase from a received packet is used in conjunction with
771 the stored values of these from the previous frame to track the phase of
772 the audio clock.
773
774 A "frame" consists of a fixed number of samples across all channels of the
775 device.  At 1x rates this appears to be 7, but it might not be fixed.  Even
776 though this is the same as the number of samples per channel per packet, a
777 given packet can experience a change in the "current frame" part way
778 through.  In other words, the "current frame" is not necessarily constant
779 for all samples in a packet.
780
781 With the number of samples per channel contained in each iso packet it is
782 not necessary for the RME to send audio data in every iso cycle.  When it is
783 deemed that a cycle can be skipped the RME simply doesn't send any packet at
784 all in that cycle.  This contrasts with other devices which tend to send
785 empty "placeholder" packets when the need arises.  This means that a cycle
786 without a packet from the RME is not necessarily an error condition.  To
787 detect dropped packets one must instead rely on the rx sample counter
788 embedded in the audio data stream.
789
790
791 Input preamp / output amp gain control
792 --------------------------------------
793
794 On the Fireface-400 the gain of the mic/instrument preamps and output
795 amplifiers can be set.  Mic channel gain is in steps of 1 dB from 10 dB up to
796 65 dB, with 0dB also available.  Instrument input gain ranges from 0 dB to
797 18 dB in 0.5 dB steps.  Output gains range from +6 dB down to -53 dB (a 58
798 dB range) in steps of 1 dB, with compete "mute" also available.
799
800 The gains are set using the register at 0x801c0180.
801
802   bits 31-24: unknown (set to 0)
803   bits 23-16: channel being set (see below)
804   bits 15-8: unknown (set to 0)
805   bits 7-0: the gain value
806
807 For mic channels the gain value is the dB value.  For instrument channels, a
808 value of 2G is written for a gain value of G (thereby allowing a stepsize of
809 0.5 dB).  For output gain, 0 = +6 dB, 0x3b = -53 dB, 0x3f = mute.
810
811 The definition of the "channel being set" is as follows.
812   0 = mic input 1 gain
813   1 = mic input 2 gain
814   2 = instrument input 3 gain
815   3 = instrument input 4 gain
816   4-9 = analog outputs 1-6 level
817   10-11 = phones output level
818   12-13 = SPDIF output level
819   14-21 = ADAT outputs 1-8 level
820
821
822 Firefice-400 mixer controls
823 ---------------------------
824
825 The Fireface-400 matrix mixer is controlled using a block of registers
826 starting at 0x80080000.  An 18x18 matrix mixer is implemented allowing any
827 hardware input to be sent to any device output.  Pan control is effected by
828 manipulating the "left/right" controls within an output pair.
829
830 For each input channel block the order of channels is Analog 1-8, SPDIF 1-2,
831 ADAT 1-8.
832
833 0x80080000 - 0x80080044: input channel sends to Analog 1 output.
834 0x80080048 - 0x8008008c: playback channel sends to Analog 1 output.
835 0x80080090 - 0x800800d4: input channel sends to Analog 2 output.
836 0x800800d8 - 0x8008011c: playback channel sends to Analog 2 output.
837 :
838 0x80080990 - 0x800809d4: input channel sends to ADAT 8 output.
839 0x800809d8 - 0x80080a1c: playback channel sends to ADAT 8 output.
840
841 0x80080f80: matrix mixer analog 1 output fader
842 0x80080f84: matrix mixer analog 2 output fader
843 :
844 0x80080fc4: matrix mixer ADAT 8 output fader
845
846 Each fader control ranges from 0x00000000 (-inf) through 0x00008000 (0.0 dB)
847 up to a maximum of 0x00010000 (+6.0 dB).  -52.7 dB appears to correspond to
848 a value of 0x0000004c, -46.6 dB is 0x00000099.  From this we can see that if
849 v is the value being written, the dB gain applied can be found using
850
851   dB = 20.log10(v/32768)
852
853 Alternatively, to set the gain to G dB, one calculates the value to send to
854 the device (v) using
855
856   v = 32768 * exp10(G/20)
857
858 When setting the output fader controls, the associated output amplifier
859 gain control (see previous section) are generally kept in sync.  That is, if
860 register 0x80080f80 (analog 1 output fader) is set to 0 dB, so is the analog
861 output 1 level via register 0x801c0180.
862
863
864 Fireface-800 mixer controls
865 ---------------------------
866
867 The matrix mixer on the Fireface-800 is controlled using a block of
868 registers starting at 0x80080000.  A 28x28 matrix mixer is implemented
869 allowing any device input to be sent to any device output.  The pan controls
870 are synthesised by manipulating the "left/right" controls.
871
872 In each sub-block, the order of channels is in fireface numeric order.  That
873 is, Analog 1-10, SPDIF, ADAT1 1-8, ADAT2 1-8.
874
875 0x80080000 - 0x8008006c: input channel sends to Analog 1 output.
876 0x80080080 - 0x800800ec: playback channel sends to Analog 1 output.
877 0x80080100 - 0x8008016c: input channel sends to Analog 2 output.
878 0x80080180 - 0x800801ec: playback channel sends to Analog 2 output.
879 :
880 0x80081b00 - 0x80081b6c: input channel sends to ADAT2-8 output.
881 0x80081b80 - 0x80081bec: playback channel sends to ADAT2-8 output.
882
883 0x80081f80: matrix mixer analog 1 output fader
884 0x80081f84: matrix mixer analog 2 output fader
885 :
886 0x80081fec: maxtrix mixer ADAT2-8 output fader
887
888 Each fader control ranges from 0x00000000 (-inf) through 0x00008000 (0.0 dB)
889 and up to a maximum setting of 0x00010000 (+6.0 dB).  As for the
890 Fireface-400, if v is the value being written, the dB gain applied can be
891 found using
892
893   dB = 20.log(v/32768)
894
895 Mute is synthesised by setting the respective send value to -inf (0).
896 Conversely, solo is synthesised by muting all sends to the selected bus
897 except the send being soloed.
898
899 Note that a different scale is used when writing mixer settings into flash.
900 Refer to the "Flash mixer settings layout" section for further details.
901
902
903 Metering values
904 ---------------
905
906 The Fireface-800 appears to provide hardware support for metering.  The RME
907 mixer application periodically sends block read requests for register
908 0x80100000 with a size of 0x3f8.  What is returned is a set of two
909 datablocks with data in little-endian (least significant bit/word first)
910 format.  The first block contains arrays of 64-bit floating point numbers
911 representing channel amplitude with decay, presumedly useful for metering
912 display.  Arrays are:
913
914   28-element array for input channel amplitude with decay
915   28-element array for playback amplitudes with decay (educated guess)
916   28-element array for output amplitudes with decay
917
918 The second data block contains signed 32 bit integers representing the input
919 amplitudes without decay.  Valid range is 0 - 0x7ffffff.  Again there are 3
920 arrays:
921
922   28-element array for input channel ampltude
923   28-element array for playback amplitudes (educated guess)
924   28-element array for output amplitudes
925
926 At the end of this second block are two zero quadlets.  Their purpose is
927 unknown at this stage.
928
929 In each 28-element array the channel data appears in standard fireface
930 order.
931
932
933 Host LED
934 --------
935
936 The "host" LED of the FF800 is controlled by a dedicated register at
937 0x200000324.  Note that this register address goes beyond the 32-bit
938 boundary.
939
940 On the FF400 the host LED is controlled internally.  On power up it is
941 turned on.  Once the host PC programs the configuration registers with
942 valid values the host LED will automatically turn off.
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