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/* |
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* Copyright (C) 2005-2008 by Pieter Palmers |
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* |
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* This file is part of FFADO |
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* FFADO = Free FireWire (pro-)audio drivers for linux |
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* |
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* FFADO is based upon FreeBoB |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 2 of the License, or |
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* (at your option) version 3 of the License. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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* |
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*/ |
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|
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#ifndef DICEDEFINES_H |
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#define DICEDEFINES_H |
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|
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// #define DICE_VER_1_0_4_0 |
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#define DICE_VER_1_0_7_0 |
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|
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#define DICE_INVALID_OFFSET 0xFFFFF00000000000ULL |
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|
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/* |
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* This header is based upon the DICE II driver specification |
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* version 1.0.7.0 and: |
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* dicedriverExtStatus.h,v 1.2 2006/09/27 20:35:45 |
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* dicedriverInterface.h,v 1.1.1.1 2006/08/10 20:00:57 |
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* |
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*/ |
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|
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// Register addresses & offsets |
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| 41 |
// DICE_PRIVATE_SPACE registers |
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#define DICE_REGISTER_BASE 0x0000FFFFE0000000ULL |
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|
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#define DICE_REGISTER_GLOBAL_PAR_SPACE_OFF 0x0000 |
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#define DICE_REGISTER_GLOBAL_PAR_SPACE_SZ 0x0004 |
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#define DICE_REGISTER_TX_PAR_SPACE_OFF 0x0008 |
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#define DICE_REGISTER_TX_PAR_SPACE_SZ 0x000C |
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#define DICE_REGISTER_RX_PAR_SPACE_OFF 0x0010 |
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#define DICE_REGISTER_RX_PAR_SPACE_SZ 0x0014 |
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#define DICE_REGISTER_UNUSED1_SPACE_OFF 0x0018 |
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#define DICE_REGISTER_UNUSED1_SPACE_SZ 0x001C |
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#define DICE_REGISTER_UNUSED2_SPACE_OFF 0x0020 |
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#define DICE_REGISTER_UNUSED2_SPACE_SZ 0x0024 |
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|
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// GLOBAL_PAR_SPACE registers |
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#define DICE_REGISTER_GLOBAL_OWNER 0x0000 |
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#define DICE_REGISTER_GLOBAL_NOTIFICATION 0x0008 |
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#define DICE_REGISTER_GLOBAL_NICK_NAME 0x000C |
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#define DICE_REGISTER_GLOBAL_CLOCK_SELECT 0x004C |
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#define DICE_REGISTER_GLOBAL_ENABLE 0x0050 |
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#define DICE_REGISTER_GLOBAL_STATUS 0x0054 |
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#define DICE_REGISTER_GLOBAL_EXTENDED_STATUS 0x0058 |
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#define DICE_REGISTER_GLOBAL_SAMPLE_RATE 0x005C |
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#define DICE_REGISTER_GLOBAL_VERSION 0x0060 |
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#define DICE_REGISTER_GLOBAL_CLOCKCAPABILITIES 0x0064 |
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#define DICE_REGISTER_GLOBAL_CLOCKSOURCENAMES 0x0068 |
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|
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// TX_PAR_SPACE registers |
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#define DICE_REGISTER_TX_NB_TX 0x0000 |
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#define DICE_REGISTER_TX_SZ_TX 0x0004 |
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|
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#define DICE_REGISTER_TX_ISOC_BASE 0x0008 |
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#define DICE_REGISTER_TX_NB_AUDIO_BASE 0x000C |
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#define DICE_REGISTER_TX_MIDI_BASE 0x0010 |
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#define DICE_REGISTER_TX_SPEED_BASE 0x0014 |
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#define DICE_REGISTER_TX_NAMES_BASE 0x0018 |
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#define DICE_REGISTER_TX_AC3_CAPABILITIES_BASE 0x0118 |
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#define DICE_REGISTER_TX_AC3_ENABLE_BASE 0x011C |
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|
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#define DICE_REGISTER_TX_PARAM(size, i, offset) \ |
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( ((i) * (size) ) + (offset) ) |
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|
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// RX_PAR_SPACE registers |
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#define DICE_REGISTER_RX_NB_RX 0x0000 |
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#define DICE_REGISTER_RX_SZ_RX 0x0004 |
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|
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#ifdef DICE_VER_1_0_4_0 |
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#define DICE_REGISTER_RX_ISOC_BASE 0x0008 |
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#define DICE_REGISTER_RX_SEQ_START_BASE 0x0014 |
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#define DICE_REGISTER_RX_NB_AUDIO_BASE 0x000C |
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#define DICE_REGISTER_RX_MIDI_BASE 0x0010 |
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#define DICE_REGISTER_RX_NAMES_BASE 0x0018 |
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#define DICE_REGISTER_RX_AC3_CAPABILITIES_BASE 0x0118 |
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#define DICE_REGISTER_RX_AC3_ENABLE_BASE 0x011C |
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#endif |
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|
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#ifdef DICE_VER_1_0_7_0 |
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#define DICE_REGISTER_RX_ISOC_BASE 0x0008 |
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#define DICE_REGISTER_RX_SEQ_START_BASE 0x000C |
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#define DICE_REGISTER_RX_NB_AUDIO_BASE 0x0010 |
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#define DICE_REGISTER_RX_MIDI_BASE 0x0014 |
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#define DICE_REGISTER_RX_NAMES_BASE 0x0018 |
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#define DICE_REGISTER_RX_AC3_CAPABILITIES_BASE 0x0118 |
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#define DICE_REGISTER_RX_AC3_ENABLE_BASE 0x011C |
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#endif |
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|
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#define DICE_REGISTER_RX_PARAM(size, i, offset) \ |
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( ((i) * (size) ) + (offset) ) |
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|
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// Register Bitfields |
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// GLOBAL_PAR_SPACE registers |
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// OWNER register defines |
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#define DICE_OWNER_NO_OWNER 0xFFFF000000000000LLU |
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|
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// NOTIFICATION register defines |
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#define DICE_NOTIFY_RX_CFG_CHG_BIT (1UL << 0) |
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#define DICE_NOTIFY_TX_CFG_CHG_BIT (1UL << 1) |
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#define DICE_NOTIFY_DUP_ISOC_BIT (1UL << 2) |
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#define DICE_NOTIFY_BW_ERR_BIT (1UL << 3) |
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#define DICE_NOTIFY_LOCK_CHG_BIT (1UL << 4) |
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#define DICE_NOTIFY_CLOCK_ACCEPTED (1UL << 5) |
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|
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// bits 6..15 are RESERVED |
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// FIXME: |
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// diceDriverInterface.h defines the following bitfield |
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// that is undocumented by spec 1.0.7.0 |
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#define DICE_INTERFACE_CHG_BIT (1UL << 6) |
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|
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// FIXME: |
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// The spec 1.0.7.0 defines these as USER notifications |
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// however diceDriverInterface.h defines these as |
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// 'reserved bits for future system wide use'. |
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#define DICE_NOTIFY_RESERVED1 (1UL << 16) |
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#define DICE_NOTIFY_RESERVED2 (1UL << 17) |
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#define DICE_NOTIFY_RESERVED3 (1UL << 18) |
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#define DICE_NOTIFY_RESERVED4 (1UL << 19) |
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|
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// FIXME: |
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// The spec 1.0.7.0 does not specify anything about |
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// the format of the user messages |
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// however diceDriverInterface.h indicates: |
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// "When DD_NOTIFY_MESSAGE is set DD_NOTIFY_USER4 through |
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// DD_NOTIFY_USER11 are defined as an 8 bit message so |
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// you can have 256 seperate messages (like gray encoder |
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// movements)." |
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#define DICE_NOTIFY_MESSAGE (1UL << 20) |
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#define DICE_NOTIFY_USER1 (1UL << 21) |
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#define DICE_NOTIFY_USER2 (1UL << 22) |
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#define DICE_NOTIFY_USER3 (1UL << 23) |
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#define DICE_NOTIFY_USER4 (1UL << 24) |
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#define DICE_NOTIFY_USER5 (1UL << 25) |
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#define DICE_NOTIFY_USER6 (1UL << 26) |
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#define DICE_NOTIFY_USER7 (1UL << 27) |
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#define DICE_NOTIFY_USER8 (1UL << 28) |
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#define DICE_NOTIFY_USER9 (1UL << 29) |
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#define DICE_NOTIFY_USER10 (1UL << 30) |
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#define DICE_NOTIFY_USER11 (1UL << 31) |
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#define DICE_NOTIFY_USER_IS_MESSAGE(x) \ |
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( ((x) & DICE_NOTIFY_MESSAGE) != 0 ) |
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#define DICE_NOTIFY_USER_GET_MESSAGE(x) \ |
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( ((x) >> 24 ) & 0xFF ) |
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// NICK_NAME register |
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// NOTE: in bytes |
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#define DICE_NICK_NAME_SIZE 64 |
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// CLOCK_SELECT register |
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// Clock sources supported |
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#define DICE_CLOCKSOURCE_AES1 0x00 |
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#define DICE_CLOCKSOURCE_AES2 0x01 |
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#define DICE_CLOCKSOURCE_AES3 0x02 |
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#define DICE_CLOCKSOURCE_AES4 0x03 |
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#define DICE_CLOCKSOURCE_AES_ANY 0x04 |
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#define DICE_CLOCKSOURCE_ADAT 0x05 |
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#define DICE_CLOCKSOURCE_TDIF 0x06 |
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#define DICE_CLOCKSOURCE_WC 0x07 |
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#define DICE_CLOCKSOURCE_ARX1 0x08 |
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#define DICE_CLOCKSOURCE_ARX2 0x09 |
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#define DICE_CLOCKSOURCE_ARX3 0x0A |
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#define DICE_CLOCKSOURCE_ARX4 0x0B |
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#define DICE_CLOCKSOURCE_INTERNAL 0x0C |
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#define DICE_CLOCKSOURCE_COUNT (DICE_CLOCKSOURCE_INTERNAL+1) |
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#define DICE_CLOCKSOURCE_MASK 0x0000FFFFLU |
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#define DICE_GET_CLOCKSOURCE(reg) (((reg) & DICE_CLOCKSOURCE_MASK)) |
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#define DICE_SET_CLOCKSOURCE(reg,clk) (((reg) & ~DICE_CLOCKSOURCE_MASK) | ((clk) & DICE_CLOCKSOURCE_MASK)) |
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|
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// Supported rates |
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#define DICE_RATE_32K 0x00 |
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#define DICE_RATE_44K1 0x01 |
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#define DICE_RATE_48K 0x02 |
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#define DICE_RATE_88K2 0x03 |
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#define DICE_RATE_96K 0x04 |
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#define DICE_RATE_176K4 0x05 |
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#define DICE_RATE_192K 0x06 |
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#define DICE_RATE_ANY_LOW 0x07 |
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#define DICE_RATE_ANY_MID 0x08 |
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#define DICE_RATE_ANY_HIGH 0x09 |
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#define DICE_RATE_NONE 0x0A |
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#define DICE_RATE_MASK 0x0000FF00LU |
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#define DICE_GET_RATE(reg) (((reg) & DICE_RATE_MASK) >> 8) |
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#define DICE_SET_RATE(reg,rate) (((reg) & ~DICE_RATE_MASK) | (((rate) << 8) & DICE_RATE_MASK) ) |
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|
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// ENABLE register |
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#define DICE_ISOSTREAMING_ENABLE (1UL << 0) |
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#define DICE_ISOSTREAMING_DISABLE (0) |
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// CLOCK_STATUS register |
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#define DICE_STATUS_SOURCE_LOCKED (1UL << 0) |
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#define DICE_STATUS_RATE_CONFLICT (1UL << 1) |
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#define DICE_STATUS_GET_NOMINAL_RATE(x) ( ((x) >> 8 ) & 0xFF ) |
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// EXTENDED_STATUS register |
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#define DICE_EXT_STATUS_AES0_LOCKED (1UL << 0) |
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#define DICE_EXT_STATUS_AES1_LOCKED (1UL << 1) |
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#define DICE_EXT_STATUS_AES2_LOCKED (1UL << 2) |
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#define DICE_EXT_STATUS_AES3_LOCKED (1UL << 3) |
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#define DICE_EXT_STATUS_AES_ANY_LOCKED ( 0x0F) |
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#define DICE_EXT_STATUS_ADAT_LOCKED (1UL << 4) |
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#define DICE_EXT_STATUS_TDIF_LOCKED (1UL << 5) |
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#define DICE_EXT_STATUS_ARX1_LOCKED (1UL << 6) |
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#define DICE_EXT_STATUS_ARX2_LOCKED (1UL << 7) |
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#define DICE_EXT_STATUS_ARX3_LOCKED (1UL << 8) |
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#define DICE_EXT_STATUS_ARX4_LOCKED (1UL << 9) |
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|
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// FIXME: this one is missing in dicedriverExtStatus.h |
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#define DICE_EXT_STATUS_WC_LOCKED (1UL << 10) |
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|
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#define DICE_EXT_STATUS_AES0_SLIP (1UL << 16) |
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#define DICE_EXT_STATUS_AES1_SLIP (1UL << 17) |
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#define DICE_EXT_STATUS_AES2_SLIP (1UL << 18) |
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#define DICE_EXT_STATUS_AES3_SLIP (1UL << 19) |
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#define DICE_EXT_STATUS_ADAT_SLIP (1UL << 20) |
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#define DICE_EXT_STATUS_TDIF_SLIP (1UL << 21) |
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#define DICE_EXT_STATUS_ARX1_SLIP (1UL << 22) |
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#define DICE_EXT_STATUS_ARX2_SLIP (1UL << 23) |
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#define DICE_EXT_STATUS_ARX3_SLIP (1UL << 24) |
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#define DICE_EXT_STATUS_ARX4_SLIP (1UL << 25) |
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|
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// FIXME: does this even exist? |
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#define DICE_EXT_STATUS_WC_SLIP (1UL << 26) |
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|
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// SAMPLE_RATE register |
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// nothing here |
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|
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// VERSION register |
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#define DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,y) \ |
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( ( (x) >> (y)) & 0xFF ) |
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|
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#define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_A(x) \ |
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DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,24) |
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|
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#define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_B(x) \ |
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DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,16) |
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|
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#define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_C(x) \ |
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DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,8) |
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|
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#define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_D(x) \ |
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DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,0) |
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|
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// CLOCKCAPABILITIES register |
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#define DICE_CLOCKCAP_RATE_32K (1UL << 0) |
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#define DICE_CLOCKCAP_RATE_44K1 (1UL << 1) |
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#define DICE_CLOCKCAP_RATE_48K (1UL << 2) |
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#define DICE_CLOCKCAP_RATE_88K2 (1UL << 3) |
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#define DICE_CLOCKCAP_RATE_96K (1UL << 4) |
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#define DICE_CLOCKCAP_RATE_176K4 (1UL << 5) |
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| 277 |
#define DICE_CLOCKCAP_RATE_192K (1UL << 6) |
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| 278 |
#define DICE_CLOCKCAP_SOURCE_AES1 (1UL << 16) |
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| 279 |
#define DICE_CLOCKCAP_SOURCE_AES2 (1UL << 17) |
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| 280 |
#define DICE_CLOCKCAP_SOURCE_AES3 (1UL << 18) |
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| 281 |
#define DICE_CLOCKCAP_SOURCE_AES4 (1UL << 19) |
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| 282 |
#define DICE_CLOCKCAP_SOURCE_AES_ANY (1UL << 20) |
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| 283 |
#define DICE_CLOCKCAP_SOURCE_ADAT (1UL << 21) |
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| 284 |
#define DICE_CLOCKCAP_SOURCE_TDIF (1UL << 22) |
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| 285 |
#define DICE_CLOCKCAP_SOURCE_WORDCLOCK (1UL << 23) |
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| 286 |
#define DICE_CLOCKCAP_SOURCE_ARX1 (1UL << 24) |
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| 287 |
#define DICE_CLOCKCAP_SOURCE_ARX2 (1UL << 25) |
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| 288 |
#define DICE_CLOCKCAP_SOURCE_ARX3 (1UL << 26) |
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| 289 |
#define DICE_CLOCKCAP_SOURCE_ARX4 (1UL << 27) |
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| 290 |
#define DICE_CLOCKCAP_SOURCE_INTERNAL (1UL << 28) |
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| 291 |
|
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| 292 |
// CLOCKSOURCENAMES |
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| 293 |
// note: in bytes |
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| 294 |
#define DICE_CLOCKSOURCENAMES_SIZE 256 |
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| 295 |
|
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| 296 |
// TX_PAR_SPACE registers |
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| 297 |
// note: in bytes |
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| 298 |
#define DICE_TX_NAMES_SIZE 256 |
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| 299 |
|
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| 300 |
// RX_PAR_SPACE registers |
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| 301 |
// note: in bytes |
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| 302 |
#define DICE_RX_NAMES_SIZE 256 |
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| 303 |
|
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| 304 |
#endif // DICEDEFINES_H |
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