root/trunk/libffado/src/dice/dice_defines.h

Revision 436, 11.3 kB (checked in by pieterpalmers, 15 years ago)

- fixed verbose level setting
- debugged DICE code, works with EVM

Line 
1 /* dice_defines.h
2  * Copyright (C) 2007 by Pieter Palmers
3  *
4  * This file is part of FreeBob.
5  *
6  * FreeBob is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  * FreeBob is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with FreeBob; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18  * MA 02111-1307 USA.
19  */
20 #ifndef DICEDEFINES_H
21 #define DICEDEFINES_H
22
23 #define DICE_VER_1_0_4_0
24 // #define DICE_VER_1_0_7_0
25
26
27 #define DICE_INVALID_OFFSET                  0xFFFFF00000000000ULL
28
29 /*
30  * This header is based upon the DICE II driver specification
31  * version 1.0.7.0 and:
32  *  dicedriverExtStatus.h,v 1.2 2006/09/27 20:35:45
33  *  dicedriverInterface.h,v 1.1.1.1 2006/08/10 20:00:57
34  *
35  */
36
37 // Register addresses & offsets
38 //  DICE_PRIVATE_SPACE registers
39 #define DICE_REGISTER_BASE                  0x0000FFFFE0000000ULL
40
41 #define DICE_REGISTER_GLOBAL_PAR_SPACE_OFF  0x0000
42 #define DICE_REGISTER_GLOBAL_PAR_SPACE_SZ   0x0004
43 #define DICE_REGISTER_TX_PAR_SPACE_OFF      0x0008
44 #define DICE_REGISTER_TX_PAR_SPACE_SZ       0x000C
45 #define DICE_REGISTER_RX_PAR_SPACE_OFF      0x0010
46 #define DICE_REGISTER_RX_PAR_SPACE_SZ       0x0014
47 #define DICE_REGISTER_UNUSED1_SPACE_OFF     0x0018
48 #define DICE_REGISTER_UNUSED1_SPACE_SZ      0x001C
49 #define DICE_REGISTER_UNUSED2_SPACE_OFF     0x0020
50 #define DICE_REGISTER_UNUSED2_SPACE_SZ      0x0024
51
52 //  GLOBAL_PAR_SPACE registers
53 #define DICE_REGISTER_GLOBAL_OWNER              0x0000
54 #define DICE_REGISTER_GLOBAL_NOTIFICATION       0x0008
55 #define DICE_REGISTER_GLOBAL_NICK_NAME          0x000C
56 #define DICE_REGISTER_GLOBAL_CLOCK_SELECT       0x004C
57 #define DICE_REGISTER_GLOBAL_ENABLE             0x0050
58 #define DICE_REGISTER_GLOBAL_STATUS             0x0054
59 #define DICE_REGISTER_GLOBAL_EXTENDED_STATUS    0x0058
60 #define DICE_REGISTER_GLOBAL_SAMPLE_RATE        0x005C
61 #define DICE_REGISTER_GLOBAL_VERSION            0x0060
62 #define DICE_REGISTER_GLOBAL_CLOCKCAPABILITIES  0x0064
63 #define DICE_REGISTER_GLOBAL_CLOCKSOURCENAMES   0x0068
64
65 //  TX_PAR_SPACE registers
66 #define DICE_REGISTER_TX_NB_TX                  0x0000
67 #define DICE_REGISTER_TX_SZ_TX                  0x0004
68
69 #define DICE_REGISTER_TX_ISOC_BASE              0x0008
70 #define DICE_REGISTER_TX_NB_AUDIO_BASE          0x000C
71 #define DICE_REGISTER_TX_MIDI_BASE              0x0010
72 #define DICE_REGISTER_TX_SPEED_BASE             0x0014
73 #define DICE_REGISTER_TX_NAMES_BASE             0x0018
74 #define DICE_REGISTER_TX_AC3_CAPABILITIES_BASE  0x0118
75 #define DICE_REGISTER_TX_AC3_ENABLE_BASE        0x011C
76
77 #define DICE_REGISTER_TX_PARAM(size, i, offset) \
78             ( ((i) * (size) ) + (offset) )
79
80 //  RX_PAR_SPACE registers
81 #define DICE_REGISTER_RX_NB_RX                  0x0000
82 #define DICE_REGISTER_RX_SZ_RX                  0x0004
83
84 #ifdef DICE_VER_1_0_4_0
85     #define DICE_REGISTER_RX_ISOC_BASE              0x0008
86     #define DICE_REGISTER_RX_SEQ_START_BASE         0x0014
87     #define DICE_REGISTER_RX_NB_AUDIO_BASE          0x000C
88     #define DICE_REGISTER_RX_MIDI_BASE              0x0010
89     #define DICE_REGISTER_RX_NAMES_BASE             0x0018
90     #define DICE_REGISTER_RX_AC3_CAPABILITIES_BASE  0x0118
91     #define DICE_REGISTER_RX_AC3_ENABLE_BASE        0x011C
92 #endif
93
94 #ifdef DICE_VER_1_0_7_0
95     #define DICE_REGISTER_RX_ISOC_BASE              0x0008
96     #define DICE_REGISTER_RX_SEQ_START_BASE         0x000C
97     #define DICE_REGISTER_RX_NB_AUDIO_BASE          0x0010
98     #define DICE_REGISTER_RX_MIDI_BASE              0x0014
99     #define DICE_REGISTER_RX_NAMES_BASE             0x0018
100     #define DICE_REGISTER_RX_AC3_CAPABILITIES_BASE  0x0118
101     #define DICE_REGISTER_RX_AC3_ENABLE_BASE        0x011C
102 #endif
103
104 #define DICE_REGISTER_RX_PARAM(size, i, offset) \
105             ( ((i) * (size) ) + (offset) )
106
107 // Register Bitfields
108 //  GLOBAL_PAR_SPACE registers
109 //   OWNER register defines
110 #define DICE_OWNER_NO_OWNER 0xFFFF000000000000LLU
111
112 //   NOTIFICATION register defines
113 #define DICE_NOTIFY_RX_CFG_CHG_BIT      (1UL << 0)
114 #define DICE_NOTIFY_TX_CFG_CHG_BIT      (1UL << 1)
115 #define DICE_NOTIFY_DUP_ISOC_BIT        (1UL << 2)
116 #define DICE_NOTIFY_BW_ERR_BIT          (1UL << 3)
117 #define DICE_NOTIFY_LOCK_CHG_BIT        (1UL << 4)
118 #define DICE_NOTIFY_CLOCK_ACCEPTED      (1UL << 5)
119
120 // bits 6..15 are RESERVED
121
122 // FIXME:
123 // diceDriverInterface.h defines the following bitfield
124 // that is undocumented by spec 1.0.7.0
125 #define DICE_INTERFACE_CHG_BIT          (1UL << 6)
126
127 // FIXME:
128 // The spec 1.0.7.0 defines these as USER notifications
129 // however diceDriverInterface.h defines these as
130 // 'reserved bits for future system wide use'.
131 #define DICE_NOTIFY_RESERVED1           (1UL << 16)
132 #define DICE_NOTIFY_RESERVED2           (1UL << 17)
133 #define DICE_NOTIFY_RESERVED3           (1UL << 18)
134 #define DICE_NOTIFY_RESERVED4           (1UL << 19)
135
136 // FIXME:
137 // The spec 1.0.7.0 does not specify anything about
138 // the format of the user messages
139 // however diceDriverInterface.h indicates:
140 // "When DD_NOTIFY_MESSAGE is set DD_NOTIFY_USER4 through
141 //  DD_NOTIFY_USER11 are defined as an 8 bit message so
142 //  you can have 256 seperate messages (like gray encoder
143 //  movements)."
144
145 #define DICE_NOTIFY_MESSAGE             (1UL << 20)
146 #define DICE_NOTIFY_USER1               (1UL << 21)
147 #define DICE_NOTIFY_USER2               (1UL << 22)
148 #define DICE_NOTIFY_USER3               (1UL << 23)
149 #define DICE_NOTIFY_USER4               (1UL << 24)
150 #define DICE_NOTIFY_USER5               (1UL << 25)
151 #define DICE_NOTIFY_USER6               (1UL << 26)
152 #define DICE_NOTIFY_USER7               (1UL << 27)
153 #define DICE_NOTIFY_USER8               (1UL << 28)
154 #define DICE_NOTIFY_USER9               (1UL << 29)
155 #define DICE_NOTIFY_USER10              (1UL << 30)
156 #define DICE_NOTIFY_USER11              (1UL << 31)
157
158 #define DICE_NOTIFY_USER_IS_MESSAGE(x) \
159                 ( ((x) & DICE_NOTIFY_MESSAGE) != 0 )
160
161 #define DICE_NOTIFY_USER_GET_MESSAGE(x) \
162                 ( ((x) >> 24 ) & 0xFF )
163                
164 //   NICK_NAME register
165
166 // NOTE: in bytes
167 #define DICE_NICK_NAME_SIZE             64
168
169 //   CLOCK_SELECT register
170 // Clock sources supported
171 #define DICE_CLOCKSOURCE_AES1           0x00
172 #define DICE_CLOCKSOURCE_AES2           0x01
173 #define DICE_CLOCKSOURCE_AES3           0x02
174 #define DICE_CLOCKSOURCE_AES4           0x03
175 #define DICE_CLOCKSOURCE_AES_ANY        0x04
176 #define DICE_CLOCKSOURCE_ADAT           0x05
177 #define DICE_CLOCKSOURCE_TDIF           0x06
178 #define DICE_CLOCKSOURCE_WC             0x07
179 #define DICE_CLOCKSOURCE_ARX1           0x08
180 #define DICE_CLOCKSOURCE_ARX2           0x09
181 #define DICE_CLOCKSOURCE_ARX3           0x0A
182 #define DICE_CLOCKSOURCE_ARX4           0x0B
183 #define DICE_CLOCKSOURCE_INTERNAL       0x0C
184
185 #define DICE_CLOCKSOURCE_MASK           0x0000FFFFLU
186 #define DICE_GET_CLOCKSOURCE(reg)       (((reg) & DICE_CLOCKSOURCE_MASK))
187 #define DICE_SET_CLOCKSOURCE(reg,clk)   (((reg) & ~DICE_CLOCKSOURCE_MASK) | ((clk) & DICE_CLOCKSOURCE_MASK))
188
189 // Supported rates
190 #define DICE_RATE_32K                   0x00
191 #define DICE_RATE_44K1                  0x01
192 #define DICE_RATE_48K                   0x02
193 #define DICE_RATE_88K2                  0x03
194 #define DICE_RATE_96K                   0x04
195 #define DICE_RATE_176K4                 0x05
196 #define DICE_RATE_192K                  0x06
197 #define DICE_RATE_ANY_LOW               0x07
198 #define DICE_RATE_ANY_MID               0x08
199 #define DICE_RATE_ANY_HIGH              0x09
200 #define DICE_RATE_NONE                  0x0A
201
202 #define DICE_RATE_MASK                  0x0000FF00LU
203 #define DICE_GET_RATE(reg)              (((reg) & DICE_RATE_MASK) >> 8)
204 #define DICE_SET_RATE(reg,rate)         (((reg) & ~DICE_RATE_MASK) | (((rate) << 8) & DICE_RATE_MASK) )
205
206 //   ENABLE register
207 #define DICE_ISOSTREAMING_ENABLE        (1UL << 0)
208 #define DICE_ISOSTREAMING_DISABLE       (0)
209
210
211 //   CLOCK_STATUS register
212 #define DICE_STATUS_SOURCE_LOCKED       (1UL << 0)
213 #define DICE_STATUS_RATE_CONFLICT       (1UL << 1)
214
215 #define DICE_STATUS_GET_NOMINAL_RATE(x) ( ((x) >> 8 ) & 0xFF )
216
217 //   EXTENDED_STATUS register
218 #define DICE_EXT_STATUS_AES0_LOCKED         (1UL << 0)
219 #define DICE_EXT_STATUS_AES1_LOCKED         (1UL << 1)
220 #define DICE_EXT_STATUS_AES2_LOCKED         (1UL << 2)
221 #define DICE_EXT_STATUS_AES3_LOCKED         (1UL << 3)
222 #define DICE_EXT_STATUS_ADAT_LOCKED         (1UL << 4)
223 #define DICE_EXT_STATUS_TDIF_LOCKED         (1UL << 5)
224 #define DICE_EXT_STATUS_ARX1_LOCKED         (1UL << 6)
225 #define DICE_EXT_STATUS_ARX2_LOCKED         (1UL << 7)
226 #define DICE_EXT_STATUS_ARX3_LOCKED         (1UL << 8)
227 #define DICE_EXT_STATUS_ARX4_LOCKED         (1UL << 9)
228
229 // FIXME: this one is missing in dicedriverExtStatus.h
230 #define DICE_EXT_STATUS_WORDCLOCK_LOCKED    (1UL << 10)
231
232 #define DICE_EXT_STATUS_AES0_SLIP           (1UL << 16)
233 #define DICE_EXT_STATUS_AES1_SLIP           (1UL << 17)
234 #define DICE_EXT_STATUS_AES2_SLIP           (1UL << 18)
235 #define DICE_EXT_STATUS_AES3_SLIP           (1UL << 19)
236 #define DICE_EXT_STATUS_ADAT_SLIP           (1UL << 20)
237 #define DICE_EXT_STATUS_TDIF_SLIP           (1UL << 21)
238 #define DICE_EXT_STATUS_ARX1_SLIP           (1UL << 22)
239 #define DICE_EXT_STATUS_ARX2_SLIP           (1UL << 23)
240 #define DICE_EXT_STATUS_ARX3_SLIP           (1UL << 24)
241 #define DICE_EXT_STATUS_ARX4_SLIP           (1UL << 25)
242
243 //   SAMPLE_RATE register
244 // nothing here
245
246 //   VERSION register
247 #define DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,y) \
248             ( ( (x) >> (y)) & 0xFF )
249
250 #define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_A(x) \
251             DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,24)
252
253 #define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_B(x) \
254             DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,16)
255
256 #define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_C(x) \
257             DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,8)
258
259 #define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_D(x) \
260             DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,0)
261
262 //   CLOCKCAPABILITIES register
263 #define DICE_CLOCKCAP_RATE_32K          (1UL << 0)
264 #define DICE_CLOCKCAP_RATE_44K1         (1UL << 1)
265 #define DICE_CLOCKCAP_RATE_48K          (1UL << 2)
266 #define DICE_CLOCKCAP_RATE_88K2         (1UL << 3)
267 #define DICE_CLOCKCAP_RATE_96K          (1UL << 4)
268 #define DICE_CLOCKCAP_RATE_176K4        (1UL << 5)
269 #define DICE_CLOCKCAP_RATE_192K         (1UL << 6)
270 #define DICE_CLOCKCAP_SOURCE_AES1       (1UL << 16)
271 #define DICE_CLOCKCAP_SOURCE_AES2       (1UL << 17)
272 #define DICE_CLOCKCAP_SOURCE_AES3       (1UL << 18)
273 #define DICE_CLOCKCAP_SOURCE_AES4       (1UL << 19)
274 #define DICE_CLOCKCAP_SOURCE_AES_ANY    (1UL << 20)
275 #define DICE_CLOCKCAP_SOURCE_ADAT       (1UL << 21)
276 #define DICE_CLOCKCAP_SOURCE_TDIF       (1UL << 22)
277 #define DICE_CLOCKCAP_SOURCE_WORDCLOCK  (1UL << 23)
278 #define DICE_CLOCKCAP_SOURCE_ARX1       (1UL << 24)
279 #define DICE_CLOCKCAP_SOURCE_ARX2       (1UL << 25)
280 #define DICE_CLOCKCAP_SOURCE_ARX3       (1UL << 26)
281 #define DICE_CLOCKCAP_SOURCE_ARX4       (1UL << 27)
282 #define DICE_CLOCKCAP_SOURCE_INTERNAL   (1UL << 28)
283
284 //   CLOCKSOURCENAMES
285 // note: in bytes
286 #define DICE_CLOCKSOURCENAMES_SIZE      256
287
288 //  TX_PAR_SPACE registers
289 // note: in bytes
290 #define DICE_TX_NAMES_SIZE              256
291
292 //  RX_PAR_SPACE registers
293 // note: in bytes
294 #define DICE_RX_NAMES_SIZE              256
295
296 #endif // DICEDEFINES_H
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