root/trunk/libffado/src/dice/dice_defines.h

Revision 445, 11.3 kB (checked in by pieterpalmers, 14 years ago)

* name change from FreeBoB to FFADO
* replaced tabs by 4 spaces
* got rid of end-of-line spaces
* made all license and copyrights conform

library becomes LGPL, apps become GPL
explicitly state LGPL v2.1 and GPL v2 (don't like v3 draft)

copyrights are 2005-2007 Daniel & Pieter
except for the MotU stuff (C) Jonathan, Pieter

Line 
1 /*
2  * Copyright (C) 2005-2007 by Pieter Palmers
3  *
4  * This file is part of FFADO
5  * FFADO = Free Firewire (pro-)audio drivers for linux
6  *
7  * FFADO is based upon FreeBoB
8  *
9  * This library is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU Lesser General Public
11  * License version 2.1, as published by the Free Software Foundation;
12  *
13  * This library is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * Lesser General Public License for more details.
17  *
18  * You should have received a copy of the GNU Lesser General Public
19  * License along with this library; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21  * MA 02110-1301 USA
22  */
23
24 #ifndef DICEDEFINES_H
25 #define DICEDEFINES_H
26
27 #define DICE_VER_1_0_4_0
28 // #define DICE_VER_1_0_7_0
29
30 #define DICE_INVALID_OFFSET                  0xFFFFF00000000000ULL
31
32 /*
33  * This header is based upon the DICE II driver specification
34  * version 1.0.7.0 and:
35  *  dicedriverExtStatus.h,v 1.2 2006/09/27 20:35:45
36  *  dicedriverInterface.h,v 1.1.1.1 2006/08/10 20:00:57
37  *
38  */
39
40 // Register addresses & offsets
41 //  DICE_PRIVATE_SPACE registers
42 #define DICE_REGISTER_BASE                  0x0000FFFFE0000000ULL
43
44 #define DICE_REGISTER_GLOBAL_PAR_SPACE_OFF  0x0000
45 #define DICE_REGISTER_GLOBAL_PAR_SPACE_SZ   0x0004
46 #define DICE_REGISTER_TX_PAR_SPACE_OFF      0x0008
47 #define DICE_REGISTER_TX_PAR_SPACE_SZ       0x000C
48 #define DICE_REGISTER_RX_PAR_SPACE_OFF      0x0010
49 #define DICE_REGISTER_RX_PAR_SPACE_SZ       0x0014
50 #define DICE_REGISTER_UNUSED1_SPACE_OFF     0x0018
51 #define DICE_REGISTER_UNUSED1_SPACE_SZ      0x001C
52 #define DICE_REGISTER_UNUSED2_SPACE_OFF     0x0020
53 #define DICE_REGISTER_UNUSED2_SPACE_SZ      0x0024
54
55 //  GLOBAL_PAR_SPACE registers
56 #define DICE_REGISTER_GLOBAL_OWNER              0x0000
57 #define DICE_REGISTER_GLOBAL_NOTIFICATION       0x0008
58 #define DICE_REGISTER_GLOBAL_NICK_NAME          0x000C
59 #define DICE_REGISTER_GLOBAL_CLOCK_SELECT       0x004C
60 #define DICE_REGISTER_GLOBAL_ENABLE             0x0050
61 #define DICE_REGISTER_GLOBAL_STATUS             0x0054
62 #define DICE_REGISTER_GLOBAL_EXTENDED_STATUS    0x0058
63 #define DICE_REGISTER_GLOBAL_SAMPLE_RATE        0x005C
64 #define DICE_REGISTER_GLOBAL_VERSION            0x0060
65 #define DICE_REGISTER_GLOBAL_CLOCKCAPABILITIES  0x0064
66 #define DICE_REGISTER_GLOBAL_CLOCKSOURCENAMES   0x0068
67
68 //  TX_PAR_SPACE registers
69 #define DICE_REGISTER_TX_NB_TX                  0x0000
70 #define DICE_REGISTER_TX_SZ_TX                  0x0004
71
72 #define DICE_REGISTER_TX_ISOC_BASE              0x0008
73 #define DICE_REGISTER_TX_NB_AUDIO_BASE          0x000C
74 #define DICE_REGISTER_TX_MIDI_BASE              0x0010
75 #define DICE_REGISTER_TX_SPEED_BASE             0x0014
76 #define DICE_REGISTER_TX_NAMES_BASE             0x0018
77 #define DICE_REGISTER_TX_AC3_CAPABILITIES_BASE  0x0118
78 #define DICE_REGISTER_TX_AC3_ENABLE_BASE        0x011C
79
80 #define DICE_REGISTER_TX_PARAM(size, i, offset) \
81             ( ((i) * (size) ) + (offset) )
82
83 //  RX_PAR_SPACE registers
84 #define DICE_REGISTER_RX_NB_RX                  0x0000
85 #define DICE_REGISTER_RX_SZ_RX                  0x0004
86
87 #ifdef DICE_VER_1_0_4_0
88     #define DICE_REGISTER_RX_ISOC_BASE              0x0008
89     #define DICE_REGISTER_RX_SEQ_START_BASE         0x0014
90     #define DICE_REGISTER_RX_NB_AUDIO_BASE          0x000C
91     #define DICE_REGISTER_RX_MIDI_BASE              0x0010
92     #define DICE_REGISTER_RX_NAMES_BASE             0x0018
93     #define DICE_REGISTER_RX_AC3_CAPABILITIES_BASE  0x0118
94     #define DICE_REGISTER_RX_AC3_ENABLE_BASE        0x011C
95 #endif
96
97 #ifdef DICE_VER_1_0_7_0
98     #define DICE_REGISTER_RX_ISOC_BASE              0x0008
99     #define DICE_REGISTER_RX_SEQ_START_BASE         0x000C
100     #define DICE_REGISTER_RX_NB_AUDIO_BASE          0x0010
101     #define DICE_REGISTER_RX_MIDI_BASE              0x0014
102     #define DICE_REGISTER_RX_NAMES_BASE             0x0018
103     #define DICE_REGISTER_RX_AC3_CAPABILITIES_BASE  0x0118
104     #define DICE_REGISTER_RX_AC3_ENABLE_BASE        0x011C
105 #endif
106
107 #define DICE_REGISTER_RX_PARAM(size, i, offset) \
108             ( ((i) * (size) ) + (offset) )
109
110 // Register Bitfields
111 //  GLOBAL_PAR_SPACE registers
112 //   OWNER register defines
113 #define DICE_OWNER_NO_OWNER 0xFFFF000000000000LLU
114
115 //   NOTIFICATION register defines
116 #define DICE_NOTIFY_RX_CFG_CHG_BIT      (1UL << 0)
117 #define DICE_NOTIFY_TX_CFG_CHG_BIT      (1UL << 1)
118 #define DICE_NOTIFY_DUP_ISOC_BIT        (1UL << 2)
119 #define DICE_NOTIFY_BW_ERR_BIT          (1UL << 3)
120 #define DICE_NOTIFY_LOCK_CHG_BIT        (1UL << 4)
121 #define DICE_NOTIFY_CLOCK_ACCEPTED      (1UL << 5)
122
123 // bits 6..15 are RESERVED
124
125 // FIXME:
126 // diceDriverInterface.h defines the following bitfield
127 // that is undocumented by spec 1.0.7.0
128 #define DICE_INTERFACE_CHG_BIT          (1UL << 6)
129
130 // FIXME:
131 // The spec 1.0.7.0 defines these as USER notifications
132 // however diceDriverInterface.h defines these as
133 // 'reserved bits for future system wide use'.
134 #define DICE_NOTIFY_RESERVED1           (1UL << 16)
135 #define DICE_NOTIFY_RESERVED2           (1UL << 17)
136 #define DICE_NOTIFY_RESERVED3           (1UL << 18)
137 #define DICE_NOTIFY_RESERVED4           (1UL << 19)
138
139 // FIXME:
140 // The spec 1.0.7.0 does not specify anything about
141 // the format of the user messages
142 // however diceDriverInterface.h indicates:
143 // "When DD_NOTIFY_MESSAGE is set DD_NOTIFY_USER4 through
144 //  DD_NOTIFY_USER11 are defined as an 8 bit message so
145 //  you can have 256 seperate messages (like gray encoder
146 //  movements)."
147
148 #define DICE_NOTIFY_MESSAGE             (1UL << 20)
149 #define DICE_NOTIFY_USER1               (1UL << 21)
150 #define DICE_NOTIFY_USER2               (1UL << 22)
151 #define DICE_NOTIFY_USER3               (1UL << 23)
152 #define DICE_NOTIFY_USER4               (1UL << 24)
153 #define DICE_NOTIFY_USER5               (1UL << 25)
154 #define DICE_NOTIFY_USER6               (1UL << 26)
155 #define DICE_NOTIFY_USER7               (1UL << 27)
156 #define DICE_NOTIFY_USER8               (1UL << 28)
157 #define DICE_NOTIFY_USER9               (1UL << 29)
158 #define DICE_NOTIFY_USER10              (1UL << 30)
159 #define DICE_NOTIFY_USER11              (1UL << 31)
160
161 #define DICE_NOTIFY_USER_IS_MESSAGE(x) \
162                 ( ((x) & DICE_NOTIFY_MESSAGE) != 0 )
163
164 #define DICE_NOTIFY_USER_GET_MESSAGE(x) \
165                 ( ((x) >> 24 ) & 0xFF )
166
167 //   NICK_NAME register
168
169 // NOTE: in bytes
170 #define DICE_NICK_NAME_SIZE             64
171
172 //   CLOCK_SELECT register
173 // Clock sources supported
174 #define DICE_CLOCKSOURCE_AES1           0x00
175 #define DICE_CLOCKSOURCE_AES2           0x01
176 #define DICE_CLOCKSOURCE_AES3           0x02
177 #define DICE_CLOCKSOURCE_AES4           0x03
178 #define DICE_CLOCKSOURCE_AES_ANY        0x04
179 #define DICE_CLOCKSOURCE_ADAT           0x05
180 #define DICE_CLOCKSOURCE_TDIF           0x06
181 #define DICE_CLOCKSOURCE_WC             0x07
182 #define DICE_CLOCKSOURCE_ARX1           0x08
183 #define DICE_CLOCKSOURCE_ARX2           0x09
184 #define DICE_CLOCKSOURCE_ARX3           0x0A
185 #define DICE_CLOCKSOURCE_ARX4           0x0B
186 #define DICE_CLOCKSOURCE_INTERNAL       0x0C
187
188 #define DICE_CLOCKSOURCE_MASK           0x0000FFFFLU
189 #define DICE_GET_CLOCKSOURCE(reg)       (((reg) & DICE_CLOCKSOURCE_MASK))
190 #define DICE_SET_CLOCKSOURCE(reg,clk)   (((reg) & ~DICE_CLOCKSOURCE_MASK) | ((clk) & DICE_CLOCKSOURCE_MASK))
191
192 // Supported rates
193 #define DICE_RATE_32K                   0x00
194 #define DICE_RATE_44K1                  0x01
195 #define DICE_RATE_48K                   0x02
196 #define DICE_RATE_88K2                  0x03
197 #define DICE_RATE_96K                   0x04
198 #define DICE_RATE_176K4                 0x05
199 #define DICE_RATE_192K                  0x06
200 #define DICE_RATE_ANY_LOW               0x07
201 #define DICE_RATE_ANY_MID               0x08
202 #define DICE_RATE_ANY_HIGH              0x09
203 #define DICE_RATE_NONE                  0x0A
204
205 #define DICE_RATE_MASK                  0x0000FF00LU
206 #define DICE_GET_RATE(reg)              (((reg) & DICE_RATE_MASK) >> 8)
207 #define DICE_SET_RATE(reg,rate)         (((reg) & ~DICE_RATE_MASK) | (((rate) << 8) & DICE_RATE_MASK) )
208
209 //   ENABLE register
210 #define DICE_ISOSTREAMING_ENABLE        (1UL << 0)
211 #define DICE_ISOSTREAMING_DISABLE       (0)
212
213
214 //   CLOCK_STATUS register
215 #define DICE_STATUS_SOURCE_LOCKED       (1UL << 0)
216 #define DICE_STATUS_RATE_CONFLICT       (1UL << 1)
217
218 #define DICE_STATUS_GET_NOMINAL_RATE(x) ( ((x) >> 8 ) & 0xFF )
219
220 //   EXTENDED_STATUS register
221 #define DICE_EXT_STATUS_AES0_LOCKED         (1UL << 0)
222 #define DICE_EXT_STATUS_AES1_LOCKED         (1UL << 1)
223 #define DICE_EXT_STATUS_AES2_LOCKED         (1UL << 2)
224 #define DICE_EXT_STATUS_AES3_LOCKED         (1UL << 3)
225 #define DICE_EXT_STATUS_ADAT_LOCKED         (1UL << 4)
226 #define DICE_EXT_STATUS_TDIF_LOCKED         (1UL << 5)
227 #define DICE_EXT_STATUS_ARX1_LOCKED         (1UL << 6)
228 #define DICE_EXT_STATUS_ARX2_LOCKED         (1UL << 7)
229 #define DICE_EXT_STATUS_ARX3_LOCKED         (1UL << 8)
230 #define DICE_EXT_STATUS_ARX4_LOCKED         (1UL << 9)
231
232 // FIXME: this one is missing in dicedriverExtStatus.h
233 #define DICE_EXT_STATUS_WORDCLOCK_LOCKED    (1UL << 10)
234
235 #define DICE_EXT_STATUS_AES0_SLIP           (1UL << 16)
236 #define DICE_EXT_STATUS_AES1_SLIP           (1UL << 17)
237 #define DICE_EXT_STATUS_AES2_SLIP           (1UL << 18)
238 #define DICE_EXT_STATUS_AES3_SLIP           (1UL << 19)
239 #define DICE_EXT_STATUS_ADAT_SLIP           (1UL << 20)
240 #define DICE_EXT_STATUS_TDIF_SLIP           (1UL << 21)
241 #define DICE_EXT_STATUS_ARX1_SLIP           (1UL << 22)
242 #define DICE_EXT_STATUS_ARX2_SLIP           (1UL << 23)
243 #define DICE_EXT_STATUS_ARX3_SLIP           (1UL << 24)
244 #define DICE_EXT_STATUS_ARX4_SLIP           (1UL << 25)
245
246 //   SAMPLE_RATE register
247 // nothing here
248
249 //   VERSION register
250 #define DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,y) \
251             ( ( (x) >> (y)) & 0xFF )
252
253 #define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_A(x) \
254             DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,24)
255
256 #define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_B(x) \
257             DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,16)
258
259 #define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_C(x) \
260             DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,8)
261
262 #define DICE_DRIVER_SPEC_VERSION_NUMBER_GET_D(x) \
263             DICE_DRIVER_SPEC_VERSION_NUMBER_GET(x,0)
264
265 //   CLOCKCAPABILITIES register
266 #define DICE_CLOCKCAP_RATE_32K          (1UL << 0)
267 #define DICE_CLOCKCAP_RATE_44K1         (1UL << 1)
268 #define DICE_CLOCKCAP_RATE_48K          (1UL << 2)
269 #define DICE_CLOCKCAP_RATE_88K2         (1UL << 3)
270 #define DICE_CLOCKCAP_RATE_96K          (1UL << 4)
271 #define DICE_CLOCKCAP_RATE_176K4        (1UL << 5)
272 #define DICE_CLOCKCAP_RATE_192K         (1UL << 6)
273 #define DICE_CLOCKCAP_SOURCE_AES1       (1UL << 16)
274 #define DICE_CLOCKCAP_SOURCE_AES2       (1UL << 17)
275 #define DICE_CLOCKCAP_SOURCE_AES3       (1UL << 18)
276 #define DICE_CLOCKCAP_SOURCE_AES4       (1UL << 19)
277 #define DICE_CLOCKCAP_SOURCE_AES_ANY    (1UL << 20)
278 #define DICE_CLOCKCAP_SOURCE_ADAT       (1UL << 21)
279 #define DICE_CLOCKCAP_SOURCE_TDIF       (1UL << 22)
280 #define DICE_CLOCKCAP_SOURCE_WORDCLOCK  (1UL << 23)
281 #define DICE_CLOCKCAP_SOURCE_ARX1       (1UL << 24)
282 #define DICE_CLOCKCAP_SOURCE_ARX2       (1UL << 25)
283 #define DICE_CLOCKCAP_SOURCE_ARX3       (1UL << 26)
284 #define DICE_CLOCKCAP_SOURCE_ARX4       (1UL << 27)
285 #define DICE_CLOCKCAP_SOURCE_INTERNAL   (1UL << 28)
286
287 //   CLOCKSOURCENAMES
288 // note: in bytes
289 #define DICE_CLOCKSOURCENAMES_SIZE      256
290
291 //  TX_PAR_SPACE registers
292 // note: in bytes
293 #define DICE_TX_NAMES_SIZE              256
294
295 //  RX_PAR_SPACE registers
296 // note: in bytes
297 #define DICE_RX_NAMES_SIZE              256
298
299 #endif // DICEDEFINES_H
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