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/* |
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* Copyright (C) 2005-2009 by Pieter Palmers |
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* |
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* This file is part of FFADO |
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* FFADO = Free Firewire (pro-)audio drivers for linux |
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* |
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* FFADO is based upon FreeBoB |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 2 of the License, or |
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* (at your option) version 3 of the License. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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* |
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*/ |
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#define DICE_EAP_BASE 0x0000000000200000ULL |
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#define DICE_EAP_MAX_SIZE 0x0000000000F00000ULL |
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#define DICE_EAP_CAPABILITY_SPACE_OFF 0x0000 |
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#define DICE_EAP_CAPABILITY_SPACE_SZ 0x0004 |
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#define DICE_EAP_CMD_SPACE_OFF 0x0008 |
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#define DICE_EAP_CMD_SPACE_SZ 0x000C |
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#define DICE_EAP_MIXER_SPACE_OFF 0x0010 |
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#define DICE_EAP_MIXER_SPACE_SZ 0x0014 |
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#define DICE_EAP_PEAK_SPACE_OFF 0x0018 |
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#define DICE_EAP_PEAK_SPACE_SZ 0x001C |
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#define DICE_EAP_NEW_ROUTING_SPACE_OFF 0x0020 |
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#define DICE_EAP_NEW_ROUTING_SPACE_SZ 0x0024 |
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#define DICE_EAP_NEW_STREAM_CFG_SPACE_OFF 0x0028 |
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#define DICE_EAP_NEW_STREAM_CFG_SPACE_SZ 0x002C |
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#define DICE_EAP_CURR_CFG_SPACE_OFF 0x0030 |
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#define DICE_EAP_CURR_CFG_SPACE_SZ 0x0034 |
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#define DICE_EAP_STAND_ALONE_CFG_SPACE_OFF 0x0038 |
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#define DICE_EAP_STAND_ALONE_CFG_SPACE_SZ 0x003C |
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#define DICE_EAP_APP_SPACE_OFF 0x0040 |
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#define DICE_EAP_APP_SPACE_SZ 0x0044 |
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#define DICE_EAP_ZERO_MARKER_1 0x0048 |
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// CAPABILITY registers |
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#define DICE_EAP_CAPABILITY_ROUTER 0x0000 |
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#define DICE_EAP_CAPABILITY_MIXER 0x0004 |
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#define DICE_EAP_CAPABILITY_GENERAL 0x0008 |
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#define DICE_EAP_CAPABILITY_RESERVED 0x000C |
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// CAPABILITY bit definitions |
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#define DICE_EAP_CAP_ROUTER_EXPOSED 0 |
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#define DICE_EAP_CAP_ROUTER_READONLY 1 |
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#define DICE_EAP_CAP_ROUTER_FLASHSTORED 2 |
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#define DICE_EAP_CAP_ROUTER_MAXROUTES 16 |
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#define DICE_EAP_CAP_MIXER_EXPOSED 0 |
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#define DICE_EAP_CAP_MIXER_READONLY 1 |
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#define DICE_EAP_CAP_MIXER_FLASHSTORED 2 |
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#define DICE_EAP_CAP_MIXER_IN_DEV 4 |
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#define DICE_EAP_CAP_MIXER_OUT_DEV 8 |
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#define DICE_EAP_CAP_MIXER_INPUTS 16 |
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#define DICE_EAP_CAP_MIXER_OUTPUTS 24 |
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#define DICE_EAP_CAP_GENERAL_STRM_CFG_EN 0 |
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#define DICE_EAP_CAP_GENERAL_FLASH_EN 1 |
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#define DICE_EAP_CAP_GENERAL_PEAK_EN 2 |
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#define DICE_EAP_CAP_GENERAL_MAX_TX_STREAM 4 |
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#define DICE_EAP_CAP_GENERAL_MAX_RX_STREAM 8 |
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#define DICE_EAP_CAP_GENERAL_STRM_CFG_FLS 12 |
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#define DICE_EAP_CAP_GENERAL_CHIP 16 |
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#define DICE_EAP_CAP_GENERAL_CHIP_DICEII 0 |
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#define DICE_EAP_CAP_GENERAL_CHIP_DICEMINI 1 |
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#define DICE_EAP_CAP_GENERAL_CHIP_DICEJR 2 |
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// COMMAND registers |
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#define DICE_EAP_COMMAND_OPCODE 0x0000 |
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#define DICE_EAP_COMMAND_RETVAL 0x0004 |
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// opcodes |
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#define DICE_EAP_CMD_OPCODE_NO_OP 0x0000 |
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#define DICE_EAP_CMD_OPCODE_LD_ROUTER 0x0001 |
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#define DICE_EAP_CMD_OPCODE_LD_STRM_CFG 0x0002 |
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#define DICE_EAP_CMD_OPCODE_LD_RTR_STRM_CFG 0x0003 |
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#define DICE_EAP_CMD_OPCODE_LD_FLASH_CFG 0x0004 |
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#define DICE_EAP_CMD_OPCODE_ST_FLASH_CFG 0x0005 |
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#define DICE_EAP_CMD_OPCODE_FLAG_LD_LOW (1U<<16) |
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#define DICE_EAP_CMD_OPCODE_FLAG_LD_MID (1U<<17) |
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#define DICE_EAP_CMD_OPCODE_FLAG_LD_HIGH (1U<<18) |
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#define DICE_EAP_CMD_OPCODE_FLAG_LD_EXECUTE (1U<<31) |
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// MIXER registers |
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// TODO |
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// PEAK registers |
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// TODO |
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// NEW ROUTER registers |
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// TODO |
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// NEW STREAM CFG registers |
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// TODO |
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// CURRENT CFG registers |
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#define DICE_EAP_CURRCFG_LOW_ROUTER 0x0000 |
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#define DICE_EAP_CURRCFG_LOW_STREAM 0x1000 |
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#define DICE_EAP_CURRCFG_MID_ROUTER 0x2000 |
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#define DICE_EAP_CURRCFG_MID_STREAM 0x3000 |
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#define DICE_EAP_CURRCFG_HIGH_ROUTER 0x4000 |
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#define DICE_EAP_CURRCFG_HIGH_STREAM 0x5000 |
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#define DICE_EAP_CHANNEL_CONFIG_NAMESTR_LEN_QUADS (64) |
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#define DICE_EAP_CHANNEL_CONFIG_NAMESTR_LEN_BYTES (4*DICE_EAP_CHANNEL_CONFIG_NAMESTR_LEN_QUADS) |
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