root/trunk/libffado/src/dice/dice_eap.h

Revision 1766, 16.5 kB (checked in by arnonym, 13 years ago)

Start some cleanup in the dice-code.

No need for the EAP to be defined inside Dice::Device.

Line 
1 /*
2  * Copyright (C) 2005-2009 by Pieter Palmers
3  *
4  * This file is part of FFADO
5  * FFADO = Free Firewire (pro-)audio drivers for linux
6  *
7  * FFADO is based upon FreeBoB
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation, either version 2 of the License, or
12  * (at your option) version 3 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23 #ifndef __DICE_EAP_H
24 #define __DICE_EAP_H
25
26 #include "dice_avdevice.h"
27
28 #define DICE_EAP_BASE                  0x0000000000200000ULL
29 #define DICE_EAP_MAX_SIZE              0x0000000000F00000ULL
30
31 #define DICE_EAP_CAPABILITY_SPACE_OFF      0x0000
32 #define DICE_EAP_CAPABILITY_SPACE_SZ       0x0004
33 #define DICE_EAP_CMD_SPACE_OFF             0x0008
34 #define DICE_EAP_CMD_SPACE_SZ              0x000C
35 #define DICE_EAP_MIXER_SPACE_OFF           0x0010
36 #define DICE_EAP_MIXER_SPACE_SZ            0x0014
37 #define DICE_EAP_PEAK_SPACE_OFF            0x0018
38 #define DICE_EAP_PEAK_SPACE_SZ             0x001C
39 #define DICE_EAP_NEW_ROUTING_SPACE_OFF     0x0020
40 #define DICE_EAP_NEW_ROUTING_SPACE_SZ      0x0024
41 #define DICE_EAP_NEW_STREAM_CFG_SPACE_OFF  0x0028
42 #define DICE_EAP_NEW_STREAM_CFG_SPACE_SZ   0x002C
43 #define DICE_EAP_CURR_CFG_SPACE_OFF        0x0030
44 #define DICE_EAP_CURR_CFG_SPACE_SZ         0x0034
45 #define DICE_EAP_STAND_ALONE_CFG_SPACE_OFF 0x0038
46 #define DICE_EAP_STAND_ALONE_CFG_SPACE_SZ  0x003C
47 #define DICE_EAP_APP_SPACE_OFF             0x0040
48 #define DICE_EAP_APP_SPACE_SZ              0x0044
49 #define DICE_EAP_ZERO_MARKER_1             0x0048
50
51 // CAPABILITY registers
52 #define DICE_EAP_CAPABILITY_ROUTER         0x0000
53 #define DICE_EAP_CAPABILITY_MIXER          0x0004
54 #define DICE_EAP_CAPABILITY_GENERAL        0x0008
55 #define DICE_EAP_CAPABILITY_RESERVED       0x000C
56
57 // CAPABILITY bit definitions
58 #define DICE_EAP_CAP_ROUTER_EXPOSED         0
59 #define DICE_EAP_CAP_ROUTER_READONLY        1
60 #define DICE_EAP_CAP_ROUTER_FLASHSTORED     2
61 #define DICE_EAP_CAP_ROUTER_MAXROUTES      16
62
63 #define DICE_EAP_CAP_MIXER_EXPOSED          0
64 #define DICE_EAP_CAP_MIXER_READONLY         1
65 #define DICE_EAP_CAP_MIXER_FLASHSTORED      2
66 #define DICE_EAP_CAP_MIXER_IN_DEV           4
67 #define DICE_EAP_CAP_MIXER_OUT_DEV          8
68 #define DICE_EAP_CAP_MIXER_INPUTS          16
69 #define DICE_EAP_CAP_MIXER_OUTPUTS         24
70
71 #define DICE_EAP_CAP_GENERAL_STRM_CFG_EN    0
72 #define DICE_EAP_CAP_GENERAL_FLASH_EN       1
73 #define DICE_EAP_CAP_GENERAL_PEAK_EN        2
74 #define DICE_EAP_CAP_GENERAL_MAX_TX_STREAM  4
75 #define DICE_EAP_CAP_GENERAL_MAX_RX_STREAM  8
76 #define DICE_EAP_CAP_GENERAL_STRM_CFG_FLS  12
77 #define DICE_EAP_CAP_GENERAL_CHIP          16
78
79 #define DICE_EAP_CAP_GENERAL_CHIP_DICEII    0
80 #define DICE_EAP_CAP_GENERAL_CHIP_DICEMINI  1
81 #define DICE_EAP_CAP_GENERAL_CHIP_DICEJR    2
82
83 // COMMAND registers
84 #define DICE_EAP_COMMAND_OPCODE         0x0000
85 #define DICE_EAP_COMMAND_RETVAL         0x0004
86
87 // opcodes
88 #define DICE_EAP_CMD_OPCODE_NO_OP            0x0000
89 #define DICE_EAP_CMD_OPCODE_LD_ROUTER        0x0001
90 #define DICE_EAP_CMD_OPCODE_LD_STRM_CFG      0x0002
91 #define DICE_EAP_CMD_OPCODE_LD_RTR_STRM_CFG  0x0003
92 #define DICE_EAP_CMD_OPCODE_LD_FLASH_CFG     0x0004
93 #define DICE_EAP_CMD_OPCODE_ST_FLASH_CFG     0x0005
94
95 #define DICE_EAP_CMD_OPCODE_FLAG_LD_LOW      (1U<<16)
96 #define DICE_EAP_CMD_OPCODE_FLAG_LD_MID      (1U<<17)
97 #define DICE_EAP_CMD_OPCODE_FLAG_LD_HIGH     (1U<<18)
98 #define DICE_EAP_CMD_OPCODE_FLAG_LD_EXECUTE  (1U<<31)
99
100
101 // MIXER registers
102 // TODO
103
104 // PEAK registers
105 // TODO
106
107 // NEW ROUTER registers
108 // TODO
109
110 // NEW STREAM CFG registers
111 // TODO
112
113 // CURRENT CFG registers
114 #define DICE_EAP_CURRCFG_LOW_ROUTER         0x0000
115 #define DICE_EAP_CURRCFG_LOW_STREAM         0x1000
116 #define DICE_EAP_CURRCFG_MID_ROUTER         0x2000
117 #define DICE_EAP_CURRCFG_MID_STREAM         0x3000
118 #define DICE_EAP_CURRCFG_HIGH_ROUTER        0x4000
119 #define DICE_EAP_CURRCFG_HIGH_STREAM        0x5000
120
121 #define DICE_EAP_CHANNEL_CONFIG_NAMESTR_LEN_QUADS  (64)
122 #define DICE_EAP_CHANNEL_CONFIG_NAMESTR_LEN_BYTES  (4*DICE_EAP_CHANNEL_CONFIG_NAMESTR_LEN_QUADS)
123
124 namespace Dice {
125
126 /**
127  * this class represents the EAP interface
128  * available on some devices
129  */
130 class EAP : public Control::Container
131 {
132 public:
133     enum eWaitReturn {
134         eWR_Error,
135         eWR_Timeout,
136         eWR_Busy,
137         eWR_Done,
138     };
139     enum eRegBase {
140         eRT_Base,
141         eRT_Capability,
142         eRT_Command,
143         eRT_Mixer,
144         eRT_Peak,
145         eRT_NewRouting,
146         eRT_NewStreamCfg,
147         eRT_CurrentCfg,
148         eRT_Standalone,
149         eRT_Application,
150         eRT_None,
151     };
152     enum eRouteSource {
153         eRS_AES = 0,
154         eRS_ADAT = 1,
155         eRS_Mixer = 2,
156         eRS_InS0 = 4,
157         eRS_InS1 = 5,
158         eRS_ARM = 10,
159         eRS_ARX0 = 11,
160         eRS_ARX1 = 12,
161         eRS_Muted = 15,
162         eRS_Invalid = 16,
163     };
164     enum eRouteDestination {
165         eRD_AES = 0,
166         eRD_ADAT = 1,
167         eRD_Mixer0 = 2,
168         eRD_Mixer1 = 3,
169         eRD_InS0 = 4,
170         eRD_InS1 = 5,
171         eRD_ARM = 10,
172         eRD_ATX0 = 11,
173         eRD_ATX1 = 12,
174         eRD_Muted = 15,
175         eRD_Invalid = 16,
176     };
177
178 public:
179
180     // ----------
181     class RouterConfig {
182     public:
183         struct Route
184         {
185             enum eRouteSource src;
186             int srcChannel;
187             enum eRouteDestination dst;
188             int dstChannel;
189             int peak;
190         };
191         typedef std::vector<RouterConfig::Route> RouteVector;
192         typedef std::vector<RouterConfig::Route>::iterator RouteVectorIterator;
193         RouterConfig(EAP &);
194         RouterConfig(EAP &, enum eRegBase, unsigned int offset);
195         virtual ~RouterConfig();
196
197         virtual bool read() {return read(m_base, m_offset);};
198         virtual bool write() {return write(m_base, m_offset);};
199         virtual bool read(enum eRegBase b, unsigned offset);
200         virtual bool write(enum eRegBase b, unsigned offset);
201         virtual void show();
202
203
204         bool insertRoute(struct Route r)
205             {return insertRoute(r, m_routes.size());};
206         bool insertRoute(struct Route r, unsigned int index);
207         bool replaceRoute(unsigned int old_index, struct Route new_route);
208         bool replaceRoute(struct Route old_route, struct Route new_route);
209         bool removeRoute(struct Route r);
210         bool removeRoute(unsigned int index);
211         int getRouteIndex(struct Route r);
212         struct Route getRoute(unsigned int index);
213
214         unsigned int getNbRoutes() {return m_routes.size();};
215
216         struct Route getRouteForDestination(enum eRouteDestination dst, int channel);
217         RouteVector getRoutesForSource(enum eRouteSource src, int channel);
218
219         struct Route decodeRoute(uint32_t val);
220         uint32_t encodeRoute(struct Route r);
221     public:
222         static enum eRouteDestination intToRouteDestination(int);
223         static enum eRouteSource intToRouteSource(int);
224     protected:
225         EAP &m_eap;
226         enum eRegBase m_base;
227         unsigned int m_offset;
228         RouteVector m_routes;
229     protected:
230         DECLARE_DEBUG_MODULE_REFERENCE;
231     };
232
233     // ----------
234     // the peak space is a special version of a router config
235     class PeakSpace : public RouterConfig {
236     public:
237         PeakSpace(EAP &p) : RouterConfig(p, eRT_Peak, 0) {};
238         virtual ~PeakSpace() {};
239
240         virtual bool read() {return read(m_base, m_offset);};
241         virtual bool write() {return write(m_base, m_offset);};
242         virtual bool read(enum eRegBase b, unsigned offset);
243         virtual bool write(enum eRegBase b, unsigned offset);
244         virtual void show();
245     };
246
247     // ----------
248     class StreamConfig {
249     public:
250         struct ConfigBlock { // FIXME: somewhere in the DICE avdevice this is present too
251             uint32_t nb_audio;
252             uint32_t nb_midi;
253             uint32_t names[DICE_EAP_CHANNEL_CONFIG_NAMESTR_LEN_QUADS];
254             uint32_t ac3_map;
255         };
256         void showConfigBlock(struct ConfigBlock &);
257         diceNameVector getNamesForBlock(struct ConfigBlock &b);
258     public:
259         StreamConfig(EAP &, enum eRegBase, unsigned int offset);
260         ~StreamConfig();
261
262         bool read() {return read(m_base, m_offset);};
263         bool write() {return write(m_base, m_offset);};
264         bool read(enum eRegBase b, unsigned offset);
265         bool write(enum eRegBase b, unsigned offset);
266
267         void show();
268
269     private:
270         EAP &m_eap;
271         enum eRegBase m_base;
272         unsigned int m_offset;
273
274         uint32_t m_nb_tx;
275         uint32_t m_nb_rx;
276
277         struct ConfigBlock *m_tx_configs;
278         struct ConfigBlock *m_rx_configs;
279
280         DECLARE_DEBUG_MODULE_REFERENCE;
281     };
282
283 public: // mixer control subclass
284     class Mixer : public Control::MatrixMixer {
285     public:
286         Mixer(EAP &);
287         ~Mixer();
288
289         bool init();
290         void show();
291
292         void updateNameCache();
293         /**
294          * load the coefficients from the device into the local cache
295          * @return
296          */
297         bool loadCoefficients();
298         /**
299          * Stores the coefficients from the cache to the device
300          * @return
301          */
302         bool storeCoefficients();
303
304         virtual int getRowCount( );
305         virtual int getColCount( );
306
307         virtual int canWrite( const int, const int );
308         virtual double setValue( const int, const int, const double );
309         virtual double getValue( const int, const int );
310
311         bool hasNames() const { return true; }
312         std::string getRowName( const int );
313         std::string getColName( const int );
314
315         // TODO: implement connections.
316         bool canConnect() const { return false; }
317
318         // full map updates are unsupported
319         virtual bool getCoefficientMap(int &);
320         virtual bool storeCoefficientMap(int &);
321
322     private:
323         EAP &         m_eap;
324         fb_quadlet_t *m_coeff;
325
326         std::map<int, RouterConfig::Route> m_input_route_map;
327         std::map<int, RouterConfig::RouteVector> m_output_route_map;
328
329         DECLARE_DEBUG_MODULE_REFERENCE;
330     };
331
332     // ----------
333     class Router : public Control::CrossbarRouter {
334     private:
335         struct Source {
336             std::string name;
337             enum eRouteSource src;
338             int srcChannel;
339         };
340         typedef std::vector<Source> SourceVector;
341         typedef std::vector<Source>::iterator SourceVectorIterator;
342
343         struct Destination {
344             std::string name;
345             enum eRouteDestination dst;
346             int dstChannel;
347         };
348         typedef std::vector<Destination> DestinationVector;
349         typedef std::vector<Destination>::iterator DestinationVectorIterator;
350
351     public:
352         Router(EAP &);
353         ~Router();
354
355         void show();
356
357         // to be subclassed by the implementing
358         // devices
359         virtual void setupSources();
360         virtual void setupDestinations();
361
362         void setupDestinationsAddDestination(const char *name, enum eRouteDestination dstid,
363                                              unsigned int base, unsigned int cnt);
364         void setupSourcesAddSource(const char *name, enum eRouteSource srcid,
365                                    unsigned int base, unsigned int cnt);
366
367         int getDestinationIndex(enum eRouteDestination dstid, int channel);
368         int getSourceIndex(enum eRouteSource srcid, int channel);
369
370         // per-coefficient access
371         virtual std::string getSourceName(const int);
372         virtual std::string getDestinationName(const int);
373         virtual int getSourceIndex(std::string);
374         virtual int getDestinationIndex(std::string);
375         virtual NameVector getSourceNames();
376         virtual NameVector getDestinationNames();
377
378         virtual Control::CrossbarRouter::Groups getSources();
379         virtual Control::CrossbarRouter::Groups getDestinations();
380
381         virtual IntVector getDestinationsForSource(const int);
382         virtual int getSourceForDestination(const int);
383
384         virtual bool canConnect( const int source, const int dest);
385         virtual bool setConnectionState( const int source, const int dest, const bool enable);
386         virtual bool getConnectionState( const int source, const int dest );
387
388         virtual bool canConnect(std::string, std::string);
389         virtual bool setConnectionState(std::string, std::string, const bool enable);
390         virtual bool getConnectionState(std::string, std::string);
391
392         virtual bool clearAllConnections();
393
394         virtual int getNbSources();
395         virtual int getNbDestinations();
396
397         // functions to access the entire routing map at once
398         // idea is that the row/col nodes that are 1 get a routing entry
399         virtual bool getConnectionMap(int *);
400         virtual bool setConnectionMap(int *);
401
402         // peak metering support
403         virtual bool hasPeakMetering();
404         virtual bool getPeakValues(double &) {return false;};
405         virtual double getPeakValue(const int source, const int dest);
406         virtual Control::CrossbarRouter::PeakValues getPeakValues();
407
408     private:
409         EAP &m_eap;
410         // these contain the sources and destinations available for this
411         // router
412         SourceVector      m_sources;
413         DestinationVector m_destinations;
414
415         PeakSpace &m_peak;
416
417         DECLARE_DEBUG_MODULE_REFERENCE;
418     };
419
420 public:
421     EAP(Device &);
422     virtual ~EAP();
423
424     static bool supportsEAP(Device &);
425     bool init();
426
427     void show();
428     void showApplication();
429     enum eWaitReturn operationBusy();
430     enum eWaitReturn waitForOperationEnd(int max_wait_time_ms = 100);
431
432     bool updateConfigurationCache();
433     RouterConfig * getActiveRouterConfig();
434     StreamConfig * getActiveStreamConfig();
435
436     bool updateRouterConfig(RouterConfig&, bool low, bool mid, bool high);
437     bool updateCurrentRouterConfig(RouterConfig&);
438     bool updateStreamConfig(StreamConfig&, bool low, bool mid, bool high);
439     bool updateStreamConfig(RouterConfig&, StreamConfig&, bool low, bool mid, bool high);
440
441     bool loadFlashConfig();
442     bool storeFlashConfig();
443
444 private:
445     bool loadRouterConfig(bool low, bool mid, bool high);
446     bool loadStreamConfig(bool low, bool mid, bool high);
447     bool loadRouterAndStreamConfig(bool low, bool mid, bool high);
448 private:
449     bool     m_router_exposed;
450     bool     m_router_readonly;
451     bool     m_router_flashstored;
452     uint16_t m_router_nb_entries;
453
454     bool     m_mixer_exposed;
455     bool     m_mixer_readonly;
456     bool     m_mixer_flashstored;
457     uint8_t  m_mixer_tx_id;
458     uint8_t  m_mixer_rx_id;
459     uint8_t  m_mixer_nb_tx;
460     uint8_t  m_mixer_nb_rx;
461
462     bool     m_general_support_dynstream;
463     bool     m_general_support_flash;
464     bool     m_general_peak_enabled;
465     uint8_t  m_general_max_tx;
466     uint8_t  m_general_max_rx;
467     bool     m_general_stream_cfg_stored;
468     uint16_t m_general_chip;
469
470     bool commandHelper(fb_quadlet_t cmd);
471
472 public:
473     bool readReg(enum eRegBase, unsigned offset, quadlet_t *);
474     bool writeReg(enum eRegBase, unsigned offset, quadlet_t);
475     bool readRegBlock(enum eRegBase, unsigned, fb_quadlet_t *, size_t);
476     bool writeRegBlock(enum eRegBase, unsigned, fb_quadlet_t *, size_t);
477     bool readRegBlockSwapped(enum eRegBase, unsigned, fb_quadlet_t *, size_t);
478     bool writeRegBlockSwapped(enum eRegBase, unsigned, fb_quadlet_t *, size_t);
479     fb_nodeaddr_t offsetGen(enum eRegBase, unsigned, size_t);
480
481 protected:
482     DECLARE_DEBUG_MODULE; //_REFERENCE;
483
484 private:
485     Device & m_device;
486     Mixer*   m_mixer;
487     Router*  m_router;
488     RouterConfig m_current_cfg_routing_low;
489     RouterConfig m_current_cfg_routing_mid;
490     RouterConfig m_current_cfg_routing_high;
491     StreamConfig m_current_cfg_stream_low;
492     StreamConfig m_current_cfg_stream_mid;
493     StreamConfig m_current_cfg_stream_high;
494 public:
495     Mixer*  getMixer() {return m_mixer;};
496     Router* getRouter() {return m_router;};
497
498 private:
499
500     fb_quadlet_t m_capability_offset;
501     fb_quadlet_t m_capability_size;
502     fb_quadlet_t m_cmd_offset;
503     fb_quadlet_t m_cmd_size;
504     fb_quadlet_t m_mixer_offset;
505     fb_quadlet_t m_mixer_size;
506     fb_quadlet_t m_peak_offset;
507     fb_quadlet_t m_peak_size;
508     fb_quadlet_t m_new_routing_offset;
509     fb_quadlet_t m_new_routing_size;
510     fb_quadlet_t m_new_stream_cfg_offset;
511     fb_quadlet_t m_new_stream_cfg_size;
512     fb_quadlet_t m_curr_cfg_offset;
513     fb_quadlet_t m_curr_cfg_size;
514     fb_quadlet_t m_standalone_offset;
515     fb_quadlet_t m_standalone_size;
516     fb_quadlet_t m_app_offset;
517     fb_quadlet_t m_app_size;
518 };
519
520 };
521
522 #endif // __DICE_EAP_H
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