root/trunk/libffado/src/rme/fireface_def.h

Revision 1573, 18.5 kB (checked in by jwoithe, 15 years ago)

RME: add I/O functions for the TCO. Clarify some comments. Fix compile issue which wasn't picked up earlier to do an incorrect scons setting.

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1 /*
2  * Copyright (C) 2009 by Jonathan Woithe
3  *
4  * This file is part of FFADO
5  * FFADO = Free Firewire (pro-)audio drivers for linux
6  *
7  * FFADO is based upon FreeBoB.
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation, either version 2 of the License, or
12  * (at your option) version 3 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23
24 /* This file contains definitions relating to the RME Fireface interfaces
25  * (Fireface 400 and Fireface 800).  Naming convention:
26  *   RME_FF_     identifier applies to both FF400 and FF800
27  *   RME_FF400_  identifier specific to the FF400
28  *   RME_FF800_  identifier specific to the FF800
29  */
30
31 #ifndef _FIREFACE_DEF
32 #define _FIREFACE_DEF
33
34 /* Identifiers for the Fireface models */
35 #define RME_FF400               0
36 #define RME_FF800               1
37
38 /* The Command Buffer Address (CBA) is different for the two interfaces */
39 #define RME_FF400_CMD_BUFFER    0x80100500
40 #define RME_FF800_CMD_BUFFER    0xfc88f000
41
42 /* Offsets for registers at fixed offsets from the device's command buffer address */
43 #define RME_FF_DDS_SRATE_OFS      (0*4)
44 #define RME_FF_CONF1_OFS          (5*4)
45 #define RME_FF_CONF2_OFS          (6*4)
46 #define RME_FF_CONF3_OFS          (7*4)
47 #define RME_FF400_FLASH_CMD_OFS   (8*4)       // Write only
48 #define RME_FF400_FLASH_STAT_OFS  (8*4)       // Read only
49
50 /* General register definitions */
51 #define RME_FF400_CONF_REG          (RME_FF400_CMD_BUFFER + RME_FF_CONF1_OFS)
52 #define RME_FF800_CONF_REG          (RME_FF800_CMD_BUFFER + RME_FF_CONF1_OFS)
53
54 #define RME_FF400_STREAM_INIT_REG   (RME_FF400_CMD_BUFFER)           // 3 quadlets wide
55 #define RME_FF400_STREAM_SRATE      (RME_FF400_CMD_BUFFER)
56 #define RME_FF400_STREAM_CONF0      (RME_FF400_CMD_BUFFER+4)
57 #define RME_FF400_STREAM_CONF1      (RME_FF400_CMD_BUFFER+8)
58 #define RME_FF800_STREAM_INIT_REG   0x20000001cLL                    // 3 quadlets wide
59 #define RME_FF800_STREAM_SRATE      0x20000001cLL
60 #define RME_FF800_STREAM_CONF0      (0x20000001cLL+4)
61 #define RME_FF800_STREAM_CONF1      (0x20000001cLL+8)
62 #define RME_FF400_STREAM_START_REG  (RME_FF400_CMD_BUFFER + 0x001c)  // 1 quadlet
63 #define RME_FF800_STREAM_START_REG  0x200000028LL                    // 1 quadlet
64 #define RME_FF400_STREAM_END_REG    (RME_FF400_CMD_BUFFER + 0x0004)  // 4 quadlets wide
65 #define RME_FF800_STREAM_END_REG    0x200000034LL                    // 3 quadlets wide
66
67 #define RME_FF800_HOST_LED_REG      0x200000324LL
68
69 #define RME_FF800_REVISION_REG      0x200000100LL
70
71 #define RME_FF_CHANNEL_MUTE_MASK     0x801c0000    // Write only
72 #define RME_FF_STATUS_REG0           0x801c0000    // Read only
73 #define RME_FF_STATUS_REG1           0x801c0004    // Read only
74
75 #define RME_FF_TCO_READ_REG          0x801f0000
76 #define RME_FF_TCO_WRITE_REG         0x810f0020
77
78 /* Addresses of various blocks in memory-mapped flash */
79 #define RME_FF400_FLASH_SETTINGS_ADDR       0x00060000
80 #define RME_FF400_FLASH_MIXER_VOLUME_ADDR   0x00070000
81 #define RME_FF400_FLASH_MIXER_PAN_ADDR      0x00070800
82 #define RME_FF400_FLASH_MIXER_HW_ADDR       0x00071000  /* Hardware volume settings, MIDI enable, submix */
83 #define RME_FF800_FLASH_MIXER_SHADOW_ADDR  0x3000e0000LL
84 #define RME_FF800_FLASH_MIXER_VOLUME_ADDR  0x3000e2000LL
85 #define RME_FF800_FLASH_MIXER_PAN_ADDR     0x3000e2800LL
86 #define RME_FF800_FLASH_MIXER_HW_ADDR      0x3000e3000LL  /* H/w volume settings, MIDI enable, submix */
87 #define RME_FF800_FLASH_SETTINGS_ADDR      0x3000f0000LL
88
89 /* Flash control registers */
90 #define RME_FF400_FLASH_BLOCK_ADDR_REG      0x80100288
91 #define RME_FF400_FLASH_BLOCK_SIZE_REG      0x8010028c
92 #define RME_FF400_FLASH_CMD_REG             (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_CMD_OFS)
93 #define RME_FF400_FLASH_STAT_REG            (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_STAT_OFS)
94 #define RME_FF400_FLASH_WRITE_BUFFER        0x80100290
95 #define RME_FF400_FLASH_READ_BUFFER         0x80100290
96
97 /* Flash erase control registers on the FF800 */
98 #define RME_FF800_FLASH_ERASE_VOLUME_REG    0x3fffffff4LL
99 #define RME_FF800_FLASH_ERASE_SETTINGS_REG  0x3fffffff0LL
100 #define RME_FF800_FLASH_ERASE_FIRMWARE_REG  0x3fffffff8LL
101 #define RME_FF800_FLASH_ERASE_CONFIG_REG    0x3fffffffcLL
102
103 /* Flags and special values */
104 #define RME_FF400_FLASH_CMD_WRITE           0x00000001
105 #define RME_FF400_FLASH_CMD_READ            0x00000002
106 #define RME_FF400_FLASH_CMD_ERASE_VOLUME    0x0000000e
107 #define RME_FF400_FLASH_CMD_ERASE_SETTINGS  0x0000000d
108 #define RME_FF400_FLASH_CMD_ERASE_CONFIG    0x0000000c
109 #define RME_FF400_FLASH_CMD_GET_REVISION    0x0000000f
110
111
112 /* Defines for components of the control registers */
113 // Configuration register 0
114 #define CR0_PHANTOM_MIC0        0x00000001
115 #define CR0_PHANTOM_MIC2        0x00000002
116 #define CR0_FILTER_FPGA         0x00000004
117 #define CR0_ILEVEL_FPGA_CTRL0   0x00000008
118 #define CR0_ILEVEL_FPGA_CTRL1   0x00000010
119 #define CR0_ILEVEL_FPGA_CTRL2   0x00000020
120 #define CR0_ZEROBIT06           0x00000040
121 #define CR0_PHANTOM_MIC1        0x00000080
122 #define CR0_PHANTOM_MIC3        0x00000100
123 #define CR0_ZEROBIT09           0x00000200
124 #define CR0_INSTR_DRIVE_FPGA    0x00000200
125 #define CRO_OLEVEL_FPGA_CTRL_0  0x00000400
126 #define CRO_OLEVEL_FPGA_CTRL_1  0x00000800
127 #define CRO_OLEVEL_FPGA_CTRL_2  0x00001000
128 #define CR0_ZEROBIT13           0x00002000
129 #define CRO_ZEROBIT14           0x00004000
130 #define CRO_ZEROBIT15           0x00008000
131 #define CRO_PHLEVEL_CTRL0       0x00010000
132 #define CRO_PHLEVEL_CTRL1       0x00020000
133
134 #define CR0_PHANTOM_FF400_MIC0  CR0_PHANTOM_MIC0
135 #define CR0_PHANTOM_FF400_MIC1  CR0_PHANTOM_MIC1
136 #define CR0_PHANTOM_FF800_MIC7  CR0_PHANTOM_MIC0
137 #define CR0_PHANTOM_FF800_MIC8  CR0_PHANTOM_MIC1
138 #define CR0_PHANTOM_FF800_MIC9  CR0_PHANTOM_MIC2
139 #define CR0_PHANTOM_FF800_MIC10 CR0_PHANTOM_MIC3
140 #define CR0_ILEVEL_FPGA_LOGAIN  CR0_ILEVEL_FPGA_CTRL0
141 #define CR0_ILEVEL_FPGA_4dBU    CR0_ILEVEL_FPGA_CTRL1
142 #define CR0_ILEVEL_FPGA_m10dBV  CR0_ILEVEL_FPGA_CTRL2
143 #define CR0_OLEVEL_FPGA_HIGAIN  CRO_OLEVEL_FPGA_CTRL_0
144 #define CR0_OLEVEL_FPGA_4dBU    CRO_OLEVEL_FPGA_CTRL_1
145 #define CR0_OLEVEL_FPGA_m10dBV  CRO_OLEVEL_FPGA_CTRL_2
146 #define CR0_PHLEVEL_4dBU        0
147 #define CRO_PHLEVEL_m10dBV      CRO_PHLEVEL_CTRL0
148 #define CRO_PHLEVEL_HIGAIN      CRO_PHLEVEL_CTRL1
149
150 // Configuration register 1
151 #define CR1_ILEVEL_CPLD_CTRL0   0x00000001
152 #define CR1_ILEVEL_CPLD_CTRL1   0x00000002
153 #define CR1_INPUT_OPT0_B        0x00000004    // Input optionset 0, option B
154 #define CR1_OLEVEL_CPLD_CTRL0   0x00000008
155 #define CR1_OLEVEL_CPLD_CTRL1   0x00000010
156 #define CR1_INPUT_OPT1_A        0x00000020    // Input optionset 1, option A
157 #define CR1_INPUT_OPT1_B        0x00000040    // Input optionset 1, option B
158 #define CR1_INPUT_OPT2_A        0x00000080    // Input optionset 2, option A
159 #define CR1_INPUT_OPT2_B        0x00000100    // Input optionset 2, option B
160 #define CR1_INSTR_DRIVE         0x00000200
161 #define CR1_INPUT_OPT0_A1       0x00000400    // Input optionset 0, option A bit 1
162 #define CR1_INPUT_OPT0_A0       0x00000800    // Input optionset 0, option A bit 0
163
164 #define CR1_ILEVEL_CPLD_LOGAIN  0
165 #define CR1_ILEVEL_CPLD_4dBU    CR1_ILEVEL_CPLD_CTRL1
166 #define CR1_ILEVEL_CPLD_m10dBV  (CR1_ILEVEL_CPLD_CTRL0 | CR1_ILEVEL_CPLD_CTRL1)
167 #define CR1_OLEVEL_CPLD_m10dBV  CR1_OLEVEL_CPLD_CTRL0
168 #define CR1_OLEVEL_CPLD_HIGAIN  CR1_OLEVEL_CPLD_CTRL1
169 #define CR1_OLEVEL_CPLD_4dBU    (CR1_OLEVEL_CPLD_CTRL0 | CR1_OLEVEL_CPLD_CTRL1)
170 #define CR1_FF800_INPUT7_FRONT  CR1_INPUT_OPT1_A
171 #define CR1_FF800_INPUT7_REAR   CR1_INPUT_OPT1_B
172 #define CR1_FF800_INPUT8_FRONT  CR1_INPUT_OPT2_A
173 #define CR1_FF800_INPUT8_REAR   CR1_INPUT_OPT2_B
174 #define CR1_FF400_INPUT3_INSTR  CR1_INPUT_OPT1_B   // To be confirmed
175 #define CR1_FF400_INPUT3_PAD    CR1_INPUT_OPT1_A   // To be confirmed
176 #define CR1_FF400_INPUT4_INSTR  CR1_INPUT_OPT2_B   // To be confirmed
177 #define CR1_FF400_INPUT4_PAD    CR1_INPUT_OPT2_A   // To be confirmed
178
179 // The input 1 "front" option is strange on the FF800 in that it is
180 // indicated using two bits.  The actual bit set depends, curiously enough,
181 // on the "speaker emulation" (aka "filter") setting.  How odd.
182 #define CR1_FF800_INPUT1_FRONT              CR1_INPUT_OPT0_A0
183 #define CR1_FF800_INPUT1_FRONT_WITH_FILTER  CR1_INPUT_OPT0_A1
184 #define CR1_FF800_INPUT1_REAR               CR1_INPUT_OPT0_B
185
186 // Configuration register 2
187 #define CR2_CLOCKMODE_AUTOSYNC  0x00000000
188 #define CR2_CLOCKMODE_MASTER    0x00000001
189 #define CR2_FREQ0               0x00000002
190 #define CR2_FREQ1               0x00000004
191 #define CR2_DSPEED              0x00000008
192 #define CR2_QSSPEED             0x00000010
193 #define CR2_SPDIF_OUT_PRO       0x00000020
194 #define CR2_SPDIF_OUT_EMP       0x00000040
195 #define CR2_SPDIF_OUT_NONAUDIO  0x00000080
196 #define CR2_SPDIF_OUT_ADAT2     0x00000100  // Optical SPDIF on ADAT2 port
197 #define CR2_SPDIF_IN_COAX       0x00000000
198 #define CR2_SPDIF_IN_ADAT2      0x00000200  // Optical SPDIF on ADAT2 port
199 #define CR2_SYNC_REF0           0x00000400
200 #define CR2_SYNC_REF1           0x00000800
201 #define CR2_SYNC_REF2           0x00001000
202 #define CR2_WORD_CLOCK_1x       0x00002000
203 #define CR2_TOGGLE_TCO          0x00004000  // Normally set to 0
204 #define CR2_P12DB_AN0           0x00010000  // Disable soft-limiter.  Normally set to 0
205 #define CR2_FF400_BIT           0x04000000  // Set on FF400, clear on FF800
206 #define CR2_TMS                 0x40000000  // Unit option, normally 0
207 #define CR2_DROP_AND_STOP       0x80000000  // Normally set to 1
208
209 #define CR2_SYNC_ADAT1          0x0
210 #define CR2_SYNC_ADAT2          (CR2_SYNC_REF0)
211 #define CR2_SYNC_SPDIF          (CR2_SYNC_REF0 | CR2_SYNC_REF1)
212 #define CR2_SYNC_WORDCLOCK      (CR2_SYNC_REF2)
213 #define CR2_SYNC_TCO            (CR2_SYNC_REF0 | CR2_SYNC_REF2)
214 #define CR2_DISABLE_LIMITER     CR2_P12DB_AN0
215
216 /* Defines for the status registers */
217 // Status register 0
218 #define SR0_ADAT1_LOCK          0x00000400
219 #define SR0_ADAT2_LOCK          0x00000800
220 #define SR0_ADAT1_SYNC          0x00001000
221 #define SR0_ADAT2_SYNC          0x00002000
222 #define SR0_F0                  0x00004000
223 #define SR0_F1                  0x00008000
224 #define SR0_F2                  0x00010000
225 #define SR0_F3                  0x00020000
226 #define SR0_SPDIF_SYNC          0x00040000
227 #define SR0_OVER                0x00080000
228 #define SR0_SPDIF_LOCK          0x00100000
229 #define SR0_SEL_SYNC_REF0       0x00200000
230 #define SR0_SEL_SYNC_REF1       0x00400000
231 #define SR0_SEL_SYNC_REF2       0x01000000
232 #define SR0_INP_FREQ0           0x02000000
233 #define SR0_INP_FREQ1           0x04000000
234 #define SR0_INP_FREQ2           0x08000000
235 #define SR0_INP_FREQ3           0x10000000
236 #define SR0_WC_SYNC             0x20000000
237 #define SR0_WC_LOCK             0x40000000
238
239 // Status register 1
240 #define SR1_TCO_LOCK            0x00800000
241 #define SR1_TCO_SYNC            0x00400000
242
243 /* Structure used to store device settings in the device flash RAM.  This
244  * structure mirrors the layout in the Fireface's flash, so it cannot be
245  * altered.  Fields named as unused_* are not utilised at present.
246  */
247 typedef struct {
248     uint32_t unused_device_id;
249     uint32_t unused_device_rev;
250     uint32_t unused_asio_latency;
251     uint32_t unused_samples_per_frame;
252     uint32_t spdif_input_mode;
253     uint32_t spdif_output_emphasis;
254     uint32_t spdif_output_pro;
255     uint32_t clock_mode;
256     uint32_t spdif_output_nonaudio;
257     uint32_t sync_ref;
258     uint32_t spdif_output_mode;
259     uint32_t unused_check_input;
260     uint32_t unused_status;
261     uint32_t unused_register[4];
262     uint32_t unused_iso_rx_channel;
263     uint32_t unused_iso_tx_channel;
264     uint32_t unused_timecode;
265     uint32_t unused_device_type;
266     uint32_t unused_number_of_devices;
267     uint32_t tms;
268     uint32_t unused_speed;
269     uint32_t unused_channels_avail_hi;
270     uint32_t unused_channels_avail_lo;
271     uint32_t limit_bandwidth;
272     uint32_t unused_bandwidth_allocated;
273     uint32_t stop_on_dropout;
274     uint32_t input_level;
275     uint32_t output_level;
276     uint32_t mic_level[2];
277     uint32_t mic_phantom[4];
278     uint32_t instrument;
279     uint32_t filter;
280     uint32_t fuzz;
281     uint32_t unused_sync_align;
282     uint32_t unused_device_index;
283     uint32_t unused_advanced_dialog;
284     uint32_t sample_rate;
285     uint32_t unused_interleaved;
286     uint32_t unused_sn;
287     uint32_t word_clock_single_speed;
288     uint32_t unused_num_channels;
289     uint32_t unused_dropped_samples;
290     uint32_t p12db_an[10];
291 } FF_device_flash_settings_t;
292
293 // Defines used to interpret device flash settings.  These appear to be
294 // arbitary from the device's perspective since the device doesn't appear to
295 // directly use these stored settings.  The driver loads the flash settings
296 // and then uses them to infer the appropriate values for the configuration
297 // registers.  The actual values used here appear to correspond more or less
298 // to the "value" returns from the GUI elements used to represent the
299 // controls under other systems.
300 #define FF_DEV_FLASH_INVALID                   0xffffffff
301 #define FF_DEV_FLASH_SPDIF_INPUT_COAX          0x00000002   // To be confirmed
302 #define FF_DEV_FLASH_SPDIF_INPUT_OPTICAL       0x00000001   // To be confirmed
303 #define FF_DEV_FLASH_SPDIF_OUTPUT_COAX         0x00000000   // To be confirmed
304 #define FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL      0x00000001   // To be confirmed
305 #define FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON  0x00000001
306 #define FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON       0x00000001
307 #define FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON  0x00000001
308 #define FF_DEV_FLASH_CLOCK_MODE_MASTER         0x00000002
309 #define FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC       0x00000001
310 #define FF_DEV_FLASH_CLOCK_MODE_SLAVE          0x00000001
311 #define FF_DEV_FLASH_SYNCREF_WORDCLOCK         0x00000001
312 #define FF_DEV_FLASH_SYNCREF_ADAT1             0x00000002
313 #define FF_DEV_FLASH_SYNCREF_ADAT2             0x00000003
314 #define FF_DEV_FLASH_SYNCREF_SPDIF             0x00000004
315 #define FF_DEV_FLASH_SYNCREC_TCO               0x00000005
316 #define FF_DEV_FLASH_ILEVEL_LOGAIN             0x00000001
317 #define FF_DEV_FLASH_ILEVEL_4dBU               0x00000002
318 #define FF_DEV_FLASH_ILEVEL_m10dBV             0x00000003
319 #define FF_DEV_FLASH_OLEVEL_HIGAIN             0x00000001
320 #define FF_DEV_FLASH_OLEVEL_4dBU               0x00000002
321 #define FF_DEV_FLASH_OLEVEL_m10dBV             0x00000003
322 #define FF_DEV_FLASH_MIC_PHANTOM_ON            0x00000001
323 #define FF_DEV_FLAS_WORD_CLOCK_1x              0x00000001
324
325 // Structure used by FFADO to keep track of the device status.  This is
326 // decoupled from any structures used directly by the device, so it can be
327 // added to and ordered freely.  When making changes to the device the
328 // configuration registers must be all written to, so any function changing
329 // a parameter must have access to the complete device status.
330 typedef struct {
331     uint32_t mic_phantom[4];
332     uint32_t spdif_input_mode;
333     uint32_t spdif_output_emphasis;
334     uint32_t spdif_output_pro;
335     uint32_t spdif_output_nonaudio;
336     uint32_t spdif_output_mode;
337     uint32_t clock_mode;
338     uint32_t sync_ref;
339     uint32_t tms;
340     uint32_t limit_bandwidth;
341     uint32_t stop_on_dropout;
342     uint32_t input_level;
343     uint32_t output_level;
344     uint32_t mic_level[2];
345     uint32_t instrument;
346     uint32_t filter;
347     uint32_t fuzz;
348     uint32_t limiter_disable;
349     uint32_t sample_rate;
350     uint32_t word_clock_single_speed;
351     uint32_t phones_level;             // No equivalent in device flash
352     uint32_t input_opt[3];             // No equivalent in device flash
353 } FF_software_settings_t;
354
355 // Defines used to interpret the software settings structure.  For now we
356 // use the same values as used by the device flash settings to remove the
357 // need for translation between reading the flash and copying it to the
358 // software settings structure, but in principle different values could be
359 // used given translation code.
360 #define FF_SWPARAM_INVALID                     FF_DEV_FLASH_INVALID
361 #define FF_SWPARAM_SPDIF_INPUT_COAX            FF_DEV_FLASH_SPDIF_INPUT_COAX
362 #define FF_SWPARAM_SPDIF_INPUT_OPTICAL         FF_DEV_FLASH_SPDIF_INPUT_OPTICAL
363 #define FF_SWPARAM_SPDIF_OUTPUT_COAX           FF_DEV_FLASH_SPDIF_OUTPUT_COAX
364 #define FF_SWPARAM_SPDIF_OUTPUT_OPTICAL        FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL
365 #define FF_SWPARAM_SPDIF_OUTPUT_EMPHASIS_ON    FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON
366 #define FF_SWPARAM_SPDIF_OUTPUT_PRO_ON         FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON
367 #define FF_SWPARAM_SPDIF_OUTPUT_NONAUDIO_ON    FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON
368 #define FF_SWPARAM_SPDIF_CLOCK_MODE_MASTER     FF_DEV_FLASH_CLOCK_MODE_MASTER
369 #define FF_SWPARAM_SPDIF_CLOCK_MODE_AUTOSYNC   FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC
370 #define FF_SWPARAM_SPDIF_CLOCK_MODE_SLAVE      FF_DEV_FLASH_CLOCK_MODE_SLAVE
371 #define FF_SWPARAM_SYNCREF_WORDCLOCK           FF_DEV_FLASH_SYNCREF_WORDCLOCK
372 #define FF_SWPARAM_SYNCREF_ADAT1               FF_DEV_FLASH_SYNCREF_ADAT1
373 #define FF_SWPARAM_SYNCREF_ADAT2               FF_DEV_FLASH_SYNCREF_ADAT2
374 #define FF_SWPARAM_SYNCREF_SPDIF               FF_DEV_FLASH_SYNCREF_SPDIF
375 #define FF_SWPARAM_SYNCREC_TCO                 FF_DEV_FLASH_SYNCREC_TCO
376 #define FF_SWPARAM_ILEVEL_LOGAIN               FF_DEV_FLASH_ILEVEL_LOGAIN
377 #define FF_SWPARAM_ILEVEL_4dBU                 FF_DEV_FLASH_ILEVEL_4dBU
378 #define FF_SWPARAM_ILEVEL_m10dBV               FF_DEV_FLASH_ILEVEL_m10dBV
379 #define FF_SWPARAM_OLEVEL_HIGAIN               FF_DEV_FLASH_OLEVEL_HIGAIN
380 #define FF_SWPARAM_OLEVEL_4dBU                 FF_DEV_FLASH_OLEVEL_4dBU
381 #define FF_SWPARAM_OLEVEL_m10dBV               FF_DEV_FLASH_OLEVEL_m10dBV
382 #define FF_SWPARAM_MIC_PHANTOM_ON              FF_DEV_FLASH_MIC_PHANTOM_ON
383 #define FF_SWPARAM_WORD_CLOCK_1x               FF_DEV_FLAS_WORD_CLOCK_1x
384 //
385 // The following defines refer to fields in the software parameter record which have no
386 // equivalent in the device flash.
387 #define FF_SWPARAM_PHONESLEVEL_HIGAIN          0x00000001
388 #define FF_SWPARAM_PHONESLEVEL_4dBU            0x00000002
389 #define FF_SWPARAM_PHONESLEVEL_m10dBV          0x00000003
390 #define FF_SWPARAM_INPUT_OPT_B                 0x00000001
391 #define FF_SWPARAM_INPUT_OPT_A                 0x00000002
392
393 #define FF_SWPARAM_FF800_INPUT_OPT_FRONT       FF_SWPARAM_INPUT_OPT_A
394 #define FF_SWPARAM_FF800_INPUT_OPT_REAR        FF_SWPARAM_INPUT_OPT_B
395
396 // Data structure for the TCO (Time Code Option) state
397 typedef struct {
398     uint32_t input;
399     uint32_t frame_rate;
400     uint32_t word_clock;
401     uint32_t sample_rate;
402     uint32_t pull;
403     uint32_t termination;
404     uint32_t MTC;
405 } FF_TCO_settings_t;
406
407 // Defines used to configure selected quadlets of the TCO write space.  The
408 // byte indices referenced in the define names are 0-based.
409 #define FF_TCO1_TCO_lock                      0x00000001
410
411 #endif
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