root/trunk/libffado/src/rme/fireface_def.h

Revision 1589, 24.4 kB (checked in by jwoithe, 14 years ago)

RME: tidied up software settings structure and removed unused fields.
RME: map configuration flash contents into software settings structure after flash is read.
RME: rename some methods to better reflect their function.
RME: documentation update to reflect the information embodied in these changes.

Line 
1 /*
2  * Copyright (C) 2009 by Jonathan Woithe
3  *
4  * This file is part of FFADO
5  * FFADO = Free Firewire (pro-)audio drivers for linux
6  *
7  * FFADO is based upon FreeBoB.
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation, either version 2 of the License, or
12  * (at your option) version 3 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23
24 /* This file contains definitions relating to the RME Fireface interfaces
25  * (Fireface 400 and Fireface 800).  Naming convention:
26  *   RME_FF_     identifier applies to both FF400 and FF800
27  *   RME_FF400_  identifier specific to the FF400
28  *   RME_FF800_  identifier specific to the FF800
29  */
30
31 #ifndef _FIREFACE_DEF
32 #define _FIREFACE_DEF
33
34 /* Identifiers for the Fireface models */
35 #define RME_FF400               0
36 #define RME_FF800               1
37
38 /* The Command Buffer Address (CBA) is different for the two interfaces */
39 #define RME_FF400_CMD_BUFFER    0x80100500
40 #define RME_FF800_CMD_BUFFER    0xfc88f000
41
42 /* Offsets for registers at fixed offsets from the device's command buffer address */
43 #define RME_FF_DDS_SRATE_OFS      (0*4)
44 #define RME_FF_CONF1_OFS          (5*4)
45 #define RME_FF_CONF2_OFS          (6*4)
46 #define RME_FF_CONF3_OFS          (7*4)
47 #define RME_FF400_FLASH_CMD_OFS   (8*4)       // Write only
48 #define RME_FF400_FLASH_STAT_OFS  (8*4)       // Read only
49
50 /* General register definitions */
51 #define RME_FF400_CONF_REG          (RME_FF400_CMD_BUFFER + RME_FF_CONF1_OFS)
52 #define RME_FF800_CONF_REG          (RME_FF800_CMD_BUFFER + RME_FF_CONF1_OFS)
53
54 #define RME_FF400_STREAM_INIT_REG   (RME_FF400_CMD_BUFFER)           // 3 quadlets wide
55 #define RME_FF400_STREAM_SRATE      (RME_FF400_CMD_BUFFER)
56 #define RME_FF400_STREAM_CONF0      (RME_FF400_CMD_BUFFER+4)
57 #define RME_FF400_STREAM_CONF1      (RME_FF400_CMD_BUFFER+8)
58 #define RME_FF800_STREAM_INIT_REG   0x20000001cLL                    // 3 quadlets wide
59 #define RME_FF800_STREAM_SRATE      0x20000001cLL
60 #define RME_FF800_STREAM_CONF0      (0x20000001cLL+4)
61 #define RME_FF800_STREAM_CONF1      (0x20000001cLL+8)
62 #define RME_FF400_STREAM_START_REG  (RME_FF400_CMD_BUFFER + 0x001c)  // 1 quadlet
63 #define RME_FF800_STREAM_START_REG  0x200000028LL                    // 1 quadlet
64 #define RME_FF400_STREAM_END_REG    (RME_FF400_CMD_BUFFER + 0x0004)  // 4 quadlets wide
65 #define RME_FF800_STREAM_END_REG    0x200000034LL                    // 3 quadlets wide
66
67 #define RME_FF800_HOST_LED_REG      0x200000324LL
68
69 #define RME_FF800_REVISION_REG      0x200000100LL
70
71 #define RME_FF_CHANNEL_MUTE_MASK     0x801c0000    // Write only
72 #define RME_FF_STATUS_REG0           0x801c0000    // Read only
73 #define RME_FF_STATUS_REG1           0x801c0004    // Read only
74
75 #define RME_FF_TCO_READ_REG          0x801f0000
76 #define RME_FF_TCO_WRITE_REG         0x810f0020
77
78 /* Addresses of various blocks in memory-mapped flash */
79 #define RME_FF400_FLASH_SETTINGS_ADDR       0x00060000
80 #define RME_FF400_FLASH_MIXER_VOLUME_ADDR   0x00070000
81 #define RME_FF400_FLASH_MIXER_PAN_ADDR      0x00070800
82 #define RME_FF400_FLASH_MIXER_HW_ADDR       0x00071000  /* Hardware volume settings, MIDI enable, submix */
83 #define RME_FF800_FLASH_MIXER_SHADOW_ADDR  0x3000e0000LL
84 #define RME_FF800_FLASH_MIXER_VOLUME_ADDR  0x3000e2000LL
85 #define RME_FF800_FLASH_MIXER_PAN_ADDR     0x3000e2800LL
86 #define RME_FF800_FLASH_MIXER_HW_ADDR      0x3000e3000LL  /* H/w volume settings, MIDI enable, submix */
87 #define RME_FF800_FLASH_SETTINGS_ADDR      0x3000f0000LL
88
89 /* Flash control registers */
90 #define RME_FF400_FLASH_BLOCK_ADDR_REG      0x80100288
91 #define RME_FF400_FLASH_BLOCK_SIZE_REG      0x8010028c
92 #define RME_FF400_FLASH_CMD_REG             (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_CMD_OFS)
93 #define RME_FF400_FLASH_STAT_REG            (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_STAT_OFS)
94 #define RME_FF400_FLASH_WRITE_BUFFER        0x80100290
95 #define RME_FF400_FLASH_READ_BUFFER         0x80100290
96
97 /* Flash erase control registers on the FF800 */
98 #define RME_FF800_FLASH_ERASE_VOLUME_REG    0x3fffffff4LL
99 #define RME_FF800_FLASH_ERASE_SETTINGS_REG  0x3fffffff0LL
100 #define RME_FF800_FLASH_ERASE_FIRMWARE_REG  0x3fffffff8LL
101 #define RME_FF800_FLASH_ERASE_CONFIG_REG    0x3fffffffcLL
102
103 /* Flash erase command values for the FF400 */
104 #define RME_FF400_FLASH_CMD_WRITE           0x00000001
105 #define RME_FF400_FLASH_CMD_READ            0x00000002
106 #define RME_FF400_FLASH_CMD_ERASE_VOLUME    0x0000000e
107 #define RME_FF400_FLASH_CMD_ERASE_SETTINGS  0x0000000d
108 #define RME_FF400_FLASH_CMD_ERASE_CONFIG    0x0000000c
109 #define RME_FF400_FLASH_CMD_GET_REVISION    0x0000000f
110
111 /* Flags for use with erase_flash() */
112 #define RME_FF_FLASH_ERASE_VOLUME           1
113 #define RME_FF_FLASH_ERASE_SETTINGS         2
114 #define RME_FF_FLASH_ERASE_CONFIG           3
115
116 /* Defines for components of the control registers */
117 // Configuration register 0
118 #define CR0_PHANTOM_MIC0        0x00000001
119 #define CR0_PHANTOM_MIC2        0x00000002
120 #define CR0_FILTER_FPGA         0x00000004
121 #define CR0_ILEVEL_FPGA_CTRL0   0x00000008
122 #define CR0_ILEVEL_FPGA_CTRL1   0x00000010
123 #define CR0_ILEVEL_FPGA_CTRL2   0x00000020
124 #define CR0_ZEROBIT06           0x00000040
125 #define CR0_PHANTOM_MIC1        0x00000080
126 #define CR0_PHANTOM_MIC3        0x00000100
127 #define CR0_ZEROBIT09           0x00000200
128 #define CR0_INSTR_DRIVE_FPGA    0x00000200
129 #define CRO_OLEVEL_FPGA_CTRL_0  0x00000400
130 #define CRO_OLEVEL_FPGA_CTRL_1  0x00000800
131 #define CRO_OLEVEL_FPGA_CTRL_2  0x00001000
132 #define CR0_ZEROBIT13           0x00002000
133 #define CRO_ZEROBIT14           0x00004000
134 #define CRO_ZEROBIT15           0x00008000
135 #define CRO_PHLEVEL_CTRL0       0x00010000
136 #define CRO_PHLEVEL_CTRL1       0x00020000
137
138 #define CR0_PHANTOM_FF400_MIC0  CR0_PHANTOM_MIC0
139 #define CR0_PHANTOM_FF400_MIC1  CR0_PHANTOM_MIC1
140 #define CR0_PHANTOM_FF800_MIC7  CR0_PHANTOM_MIC0
141 #define CR0_PHANTOM_FF800_MIC8  CR0_PHANTOM_MIC1
142 #define CR0_PHANTOM_FF800_MIC9  CR0_PHANTOM_MIC2
143 #define CR0_PHANTOM_FF800_MIC10 CR0_PHANTOM_MIC3
144 #define CR0_ILEVEL_FPGA_LOGAIN  CR0_ILEVEL_FPGA_CTRL0
145 #define CR0_ILEVEL_FPGA_4dBU    CR0_ILEVEL_FPGA_CTRL1
146 #define CR0_ILEVEL_FPGA_m10dBV  CR0_ILEVEL_FPGA_CTRL2
147 #define CR0_OLEVEL_FPGA_HIGAIN  CRO_OLEVEL_FPGA_CTRL_0
148 #define CR0_OLEVEL_FPGA_4dBU    CRO_OLEVEL_FPGA_CTRL_1
149 #define CR0_OLEVEL_FPGA_m10dBV  CRO_OLEVEL_FPGA_CTRL_2
150 #define CR0_PHLEVEL_4dBU        0
151 #define CRO_PHLEVEL_m10dBV      CRO_PHLEVEL_CTRL0
152 #define CRO_PHLEVEL_HIGAIN      CRO_PHLEVEL_CTRL1
153
154 // Configuration register 1
155 #define CR1_ILEVEL_CPLD_CTRL0   0x00000001
156 #define CR1_ILEVEL_CPLD_CTRL1   0x00000002
157 #define CR1_INPUT_OPT0_B        0x00000004    // Input optionset 0, option B
158 #define CR1_OLEVEL_CPLD_CTRL0   0x00000008
159 #define CR1_OLEVEL_CPLD_CTRL1   0x00000010
160 #define CR1_INPUT_OPT1_A        0x00000020    // Input optionset 1, option A
161 #define CR1_INPUT_OPT1_B        0x00000040    // Input optionset 1, option B
162 #define CR1_INPUT_OPT2_A        0x00000080    // Input optionset 2, option A
163 #define CR1_INPUT_OPT2_B        0x00000100    // Input optionset 2, option B
164 #define CR1_INSTR_DRIVE         0x00000200
165 #define CR1_INPUT_OPT0_A1       0x00000400    // Input optionset 0, option A bit 1
166 #define CR1_INPUT_OPT0_A0       0x00000800    // Input optionset 0, option A bit 0
167
168 #define CR1_ILEVEL_CPLD_LOGAIN  0
169 #define CR1_ILEVEL_CPLD_4dBU    CR1_ILEVEL_CPLD_CTRL1
170 #define CR1_ILEVEL_CPLD_m10dBV  (CR1_ILEVEL_CPLD_CTRL0 | CR1_ILEVEL_CPLD_CTRL1)
171 #define CR1_OLEVEL_CPLD_m10dBV  CR1_OLEVEL_CPLD_CTRL0
172 #define CR1_OLEVEL_CPLD_HIGAIN  CR1_OLEVEL_CPLD_CTRL1
173 #define CR1_OLEVEL_CPLD_4dBU    (CR1_OLEVEL_CPLD_CTRL0 | CR1_OLEVEL_CPLD_CTRL1)
174 #define CR1_FF800_INPUT7_FRONT  CR1_INPUT_OPT1_A
175 #define CR1_FF800_INPUT7_REAR   CR1_INPUT_OPT1_B
176 #define CR1_FF800_INPUT8_FRONT  CR1_INPUT_OPT2_A
177 #define CR1_FF800_INPUT8_REAR   CR1_INPUT_OPT2_B
178 #define CR1_FF400_INPUT3_INSTR  CR1_INPUT_OPT1_B   // To be confirmed
179 #define CR1_FF400_INPUT3_PAD    CR1_INPUT_OPT1_A   // To be confirmed
180 #define CR1_FF400_INPUT4_INSTR  CR1_INPUT_OPT2_B   // To be confirmed
181 #define CR1_FF400_INPUT4_PAD    CR1_INPUT_OPT2_A   // To be confirmed
182
183 // The input 1 "front" option is strange on the FF800 in that it is
184 // indicated using two bits.  The actual bit set depends, curiously enough,
185 // on the "speaker emulation" (aka "filter") setting.  How odd.
186 #define CR1_FF800_INPUT1_FRONT              CR1_INPUT_OPT0_A0
187 #define CR1_FF800_INPUT1_FRONT_WITH_FILTER  CR1_INPUT_OPT0_A1
188 #define CR1_FF800_INPUT1_REAR               CR1_INPUT_OPT0_B
189
190 // Configuration register 2
191 #define CR2_CLOCKMODE_AUTOSYNC  0x00000000
192 #define CR2_CLOCKMODE_MASTER    0x00000001
193 #define CR2_FREQ0               0x00000002
194 #define CR2_FREQ1               0x00000004
195 #define CR2_DSPEED              0x00000008
196 #define CR2_QSSPEED             0x00000010
197 #define CR2_SPDIF_OUT_PRO       0x00000020
198 #define CR2_SPDIF_OUT_EMP       0x00000040
199 #define CR2_SPDIF_OUT_NONAUDIO  0x00000080
200 #define CR2_SPDIF_OUT_ADAT2     0x00000100  // Optical SPDIF on ADAT2 port
201 #define CR2_SPDIF_IN_COAX       0x00000000
202 #define CR2_SPDIF_IN_ADAT2      0x00000200  // Optical SPDIF on ADAT2 port
203 #define CR2_SYNC_REF0           0x00000400
204 #define CR2_SYNC_REF1           0x00000800
205 #define CR2_SYNC_REF2           0x00001000
206 #define CR2_WORD_CLOCK_1x       0x00002000
207 #define CR2_TOGGLE_TCO          0x00004000  // Normally set to 0
208 #define CR2_P12DB_AN0           0x00010000  // Disable soft-limiter.  Normally set to 0
209 #define CR2_FF400_BIT           0x04000000  // Set on FF400, clear on FF800
210 #define CR2_TMS                 0x40000000  // Unit option, normally 0
211 #define CR2_DROP_AND_STOP       0x80000000  // Normally set to 1
212
213 #define CR2_SYNC_ADAT1          0x0
214 #define CR2_SYNC_ADAT2          (CR2_SYNC_REF0)
215 #define CR2_SYNC_SPDIF          (CR2_SYNC_REF0 | CR2_SYNC_REF1)
216 #define CR2_SYNC_WORDCLOCK      (CR2_SYNC_REF2)
217 #define CR2_SYNC_TCO            (CR2_SYNC_REF0 | CR2_SYNC_REF2)
218 #define CR2_DISABLE_LIMITER     CR2_P12DB_AN0
219
220 /* Defines for the status registers */
221 // Status register 0
222 #define SR0_ADAT1_LOCK          0x00000400
223 #define SR0_ADAT2_LOCK          0x00000800
224 #define SR0_ADAT1_SYNC          0x00001000
225 #define SR0_ADAT2_SYNC          0x00002000
226 #define SR0_F0                  0x00004000
227 #define SR0_F1                  0x00008000
228 #define SR0_F2                  0x00010000
229 #define SR0_F3                  0x00020000
230 #define SR0_SPDIF_SYNC          0x00040000
231 #define SR0_OVER                0x00080000
232 #define SR0_SPDIF_LOCK          0x00100000
233 #define SR0_SEL_SYNC_REF0       0x00200000
234 #define SR0_SEL_SYNC_REF1       0x00400000
235 #define SR0_SEL_SYNC_REF2       0x01000000
236 #define SR0_INP_FREQ0           0x02000000
237 #define SR0_INP_FREQ1           0x04000000
238 #define SR0_INP_FREQ2           0x08000000
239 #define SR0_INP_FREQ3           0x10000000
240 #define SR0_WC_SYNC             0x20000000
241 #define SR0_WC_LOCK             0x40000000
242
243 // Status register 1
244 #define SR1_TCO_LOCK            0x00800000
245 #define SR1_TCO_SYNC            0x00400000
246
247 /* Structure used to store device settings in the device flash RAM.  This
248  * structure mirrors the layout in the Fireface's flash, so it cannot be
249  * altered.  Fields named as unused_* are not utilised at present.
250  */
251 typedef struct {
252     uint32_t unused_device_id;
253     uint32_t unused_device_rev;
254     uint32_t unused_asio_latency;
255     uint32_t unused_samples_per_frame;
256     uint32_t spdif_input_mode;
257     uint32_t spdif_output_emphasis;
258     uint32_t spdif_output_pro;
259     uint32_t clock_mode;
260     uint32_t spdif_output_nonaudio;
261     uint32_t sync_ref;
262     uint32_t spdif_output_mode;
263     uint32_t unused_check_input;
264     uint32_t unused_status;
265     uint32_t unused_register[4];
266     uint32_t unused_iso_rx_channel;
267     uint32_t unused_iso_tx_channel;
268     uint32_t unused_timecode;
269     uint32_t unused_device_type;
270     uint32_t unused_number_of_devices;
271     uint32_t tms;
272     uint32_t unused_speed;
273     uint32_t unused_channels_avail_hi;
274     uint32_t unused_channels_avail_lo;
275     uint32_t limit_bandwidth;
276     uint32_t unused_bandwidth_allocated;
277     uint32_t stop_on_dropout;
278     uint32_t input_level;
279     uint32_t output_level;
280     uint32_t mic_plug_select[2];     // Front/rear select for FF800 ch 7/8
281                                      // [0] = phones level on FF400
282     uint32_t mic_phantom[4];
283     uint32_t instrument_plug_select; // Front/rear select for FF800 ch 1
284     uint32_t filter;
285     uint32_t fuzz;
286     uint32_t unused_sync_align;
287     uint32_t unused_device_index;
288     uint32_t unused_advanced_dialog;
289     uint32_t sample_rate;
290     uint32_t unused_interleaved;
291     uint32_t unused_sn;
292     uint32_t word_clock_single_speed;
293     uint32_t unused_num_channels;
294     uint32_t unused_dropped_samples;
295     uint32_t p12db_an[10];
296 } FF_device_flash_settings_t;
297
298 // Defines used to interpret device flash settings.  These appear to be
299 // arbitary from the device's perspective since the device doesn't appear to
300 // directly use these stored settings.  The driver loads the flash settings
301 // and then uses them to infer the appropriate values for the configuration
302 // registers.  The actual values used here appear to correspond more or less
303 // to the "value" returns from the GUI elements used to represent the
304 // controls under other systems.
305 #define FF_DEV_FLASH_INVALID                   0xffffffff
306 #define FF_DEV_FLASH_SPDIF_INPUT_COAX          0x00000002   // To be confirmed
307 #define FF_DEV_FLASH_SPDIF_INPUT_OPTICAL       0x00000001   // To be confirmed
308 #define FF_DEV_FLASH_SPDIF_OUTPUT_COAX         0x00000000   // To be confirmed
309 #define FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL      0x00000001   // To be confirmed
310 #define FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON  0x00000001
311 #define FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON       0x00000001
312 #define FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON  0x00000001
313 #define FF_DEV_FLASH_CLOCK_MODE_MASTER         0x00000002
314 #define FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC       0x00000001
315 #define FF_DEV_FLASH_CLOCK_MODE_SLAVE          0x00000001
316 #define FF_DEV_FLASH_SYNCREF_WORDCLOCK         0x00000001
317 #define FF_DEV_FLASH_SYNCREF_ADAT1             0x00000002
318 #define FF_DEV_FLASH_SYNCREF_ADAT2             0x00000003
319 #define FF_DEV_FLASH_SYNCREF_SPDIF             0x00000004
320 #define FF_DEV_FLASH_SYNCREC_TCO               0x00000005
321 #define FF_DEV_FLASH_ILEVEL_LOGAIN             0x00000001
322 #define FF_DEV_FLASH_ILEVEL_4dBU               0x00000002
323 #define FF_DEV_FLASH_ILEVEL_m10dBV             0x00000003
324 #define FF_DEV_FLASH_OLEVEL_HIGAIN             0x00000001
325 #define FF_DEV_FLASH_OLEVEL_4dBU               0x00000002
326 #define FF_DEV_FLASH_OLEVEL_m10dBV             0x00000003
327 #define FF_DEV_FLASH_MIC_PHANTOM_ON            0x00000001
328 #define FF_DEV_FLASH_WORD_CLOCK_1x             0x00000001
329 #define FF_DEV_FLASH_PLUG_SELECT_FRONT         0x00000001  // To be confirmed
330 #define FF_DEV_FLASH_PLUG_SELECT_REAR          0x00000000  // To be confirmed
331
332 // Structure used by FFADO to keep track of the device status.  This is
333 // decoupled from any structures used directly by the device, so it can be
334 // added to and ordered freely.  When making changes to the device the
335 // configuration registers must be all written to, so any function changing
336 // a parameter must have access to the complete device status.
337 typedef struct {
338     uint32_t mic_phantom[4];
339     uint32_t spdif_input_mode;
340     uint32_t spdif_output_emphasis;
341     uint32_t spdif_output_pro;
342     uint32_t spdif_output_nonaudio;
343     uint32_t spdif_output_mode;
344     uint32_t clock_mode;
345     uint32_t sync_ref;
346     uint32_t tms;
347     uint32_t limit_bandwidth;
348     uint32_t stop_on_dropout;
349     uint32_t input_level;
350     uint32_t output_level;
351     uint32_t filter;
352     uint32_t fuzz;
353     uint32_t limiter_disable;
354     uint32_t sample_rate;
355     uint32_t word_clock_single_speed;
356     uint32_t phones_level;             // Derived from fields in device flash
357     uint32_t input_opt[3];             // Derived from fields in device flash
358 } FF_software_settings_t;
359
360 // Defines used to interpret the software settings structure.  For now we
361 // use the same values as used by the device flash settings to remove the
362 // need for translation between reading the flash and copying it to the
363 // software settings structure, but in principle different values could be
364 // used given translation code.
365 #define FF_SWPARAM_INVALID                     FF_DEV_FLASH_INVALID
366 #define FF_SWPARAM_SPDIF_INPUT_COAX            FF_DEV_FLASH_SPDIF_INPUT_COAX
367 #define FF_SWPARAM_SPDIF_INPUT_OPTICAL         FF_DEV_FLASH_SPDIF_INPUT_OPTICAL
368 #define FF_SWPARAM_SPDIF_OUTPUT_COAX           FF_DEV_FLASH_SPDIF_OUTPUT_COAX
369 #define FF_SWPARAM_SPDIF_OUTPUT_OPTICAL        FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL
370 #define FF_SWPARAM_SPDIF_OUTPUT_EMPHASIS_ON    FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON
371 #define FF_SWPARAM_SPDIF_OUTPUT_PRO_ON         FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON
372 #define FF_SWPARAM_SPDIF_OUTPUT_NONAUDIO_ON    FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON
373 #define FF_SWPARAM_SPDIF_CLOCK_MODE_MASTER     FF_DEV_FLASH_CLOCK_MODE_MASTER
374 #define FF_SWPARAM_SPDIF_CLOCK_MODE_AUTOSYNC   FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC
375 #define FF_SWPARAM_SPDIF_CLOCK_MODE_SLAVE      FF_DEV_FLASH_CLOCK_MODE_SLAVE
376 #define FF_SWPARAM_SYNCREF_WORDCLOCK           FF_DEV_FLASH_SYNCREF_WORDCLOCK
377 #define FF_SWPARAM_SYNCREF_ADAT1               FF_DEV_FLASH_SYNCREF_ADAT1
378 #define FF_SWPARAM_SYNCREF_ADAT2               FF_DEV_FLASH_SYNCREF_ADAT2
379 #define FF_SWPARAM_SYNCREF_SPDIF               FF_DEV_FLASH_SYNCREF_SPDIF
380 #define FF_SWPARAM_SYNCREC_TCO                 FF_DEV_FLASH_SYNCREC_TCO
381 #define FF_SWPARAM_ILEVEL_LOGAIN               FF_DEV_FLASH_ILEVEL_LOGAIN
382 #define FF_SWPARAM_ILEVEL_4dBU                 FF_DEV_FLASH_ILEVEL_4dBU
383 #define FF_SWPARAM_ILEVEL_m10dBV               FF_DEV_FLASH_ILEVEL_m10dBV
384 #define FF_SWPARAM_OLEVEL_HIGAIN               FF_DEV_FLASH_OLEVEL_HIGAIN
385 #define FF_SWPARAM_OLEVEL_4dBU                 FF_DEV_FLASH_OLEVEL_4dBU
386 #define FF_SWPARAM_OLEVEL_m10dBV               FF_DEV_FLASH_OLEVEL_m10dBV
387 #define FF_SWPARAM_MIC_PHANTOM_ON              FF_DEV_FLASH_MIC_PHANTOM_ON
388 #define FF_SWPARAM_WORD_CLOCK_1x               FF_DEV_FLASH_WORD_CLOCK_1x
389 //
390 // The following defines refer to fields in the software parameter record
391 // which are derived from one or more fields in device flash.
392 #define FF_SWPARAM_PHONESLEVEL_HIGAIN          0x00000001
393 #define FF_SWPARAM_PHONESLEVEL_4dBU            0x00000002
394 #define FF_SWPARAM_PHONESLEVEL_m10dBV          0x00000003
395 #define FF_SWPARAM_INPUT_OPT_B                 0x00000001
396 #define FF_SWPARAM_INPUT_OPT_A                 0x00000002
397
398 #define FF_SWPARAM_FF800_INPUT_OPT_FRONT       FF_SWPARAM_INPUT_OPT_A
399 #define FF_SWPARAM_FF800_INPUT_OPT_REAR        FF_SWPARAM_INPUT_OPT_B
400
401 // Data structure for the TCO (Time Code Option) state
402 typedef struct {
403     uint32_t input;
404     uint32_t frame_rate;
405     uint32_t word_clock;
406     uint32_t sample_rate;
407     uint32_t pull;
408     uint32_t termination;
409     uint32_t MTC;
410 } FF_TCO_settings_t;
411
412 // Defines used to configure selected quadlets of the TCO write space.  The
413 // byte indices referenced in the define names are 0-based.
414
415 // TCO quadlet 0
416 #define FF_TCO0_MTC                           0x80000000
417
418 // TCO quadlet 1
419 #define FF_TCO1_TCO_lock                      0x00000001
420 #define FF_TCO1_WORD_CLOCK_INPUT_RATE0        0x00000002
421 #define FF_TCO1_WORD_CLOCK_INPUT_RATE1        0x00000004
422 #define FF_TCO1_LTC_INPUT_VALID               0x00000008
423 #define FF_TCO1_WORD_CLOCK_INPUT_VALID        0x00000010
424 #define FF_TCO1_VIDEO_INPUT_NTSC              0x00000020
425 #define FF_TCO1_VIDEO_INPUT_PAL               0x00000040
426 #define FF_TCO1_SET_TC                        0x00000100
427 #define FF_TCO1_SET_DROPFRAME                 0x00000200
428 #define FF_TCO1_LTC_FORMAT0                   0x00000400
429 #define FF_TCO1_LTC_FORMAT1                   0x00000800
430
431 #define FF_TCO1_WORD_CLOCK_INPUT_1x           0
432 #define FF_TCO1_WORD_CLOCK_INPUT_2x           FF_TCO1_WORD_CLOCK_INPUT_RATE0
433 #define FF_TCO1_WORD_CLOCK_INPUT_4x           FF_TCO1_WORD_CLOCK_INPUT_RATE1
434 #define FF_TCO1_WORD_CLOCK_INPUT_MASK         (FF_TCO1_WORD_CLOCK_INPUT_RATE0|FF_TCO1_WORD_CLOCK_INPUT_RATE1)
435 #define FF_TCO1_VIDEO_INPUT_MASK              (FF_TCO1_VIDEO_INPUT_NTSC|FF_TCO1_VIDEO_INPUT_PAL)
436 #define FF_TC01_LTC_FORMAT_24fps              0
437 #define FF_TCO1_LTC_FORMAT_25fps              FF_TCO1_LTC_FORMAT0
438 #define FF_TC01_LTC_FORMAT_29_97fps           FF_TCO1_LTC_FORMAT1
439 #define FF_TCO1_LTC_FORMAT_29_97dpfs          (FF_TCO1_LTC_FORMAT1|FF_TCO1_SET_DROPFRAME)
440 #define FF_TCO1_LTC_FORMAT_30fps              (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1)
441 #define FF_TCO1_LTC_FORMAT_30dfps             (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1|FF_TCO1_SET_DROPFRAME)
442 #define FF_TCO1_LTC_FORMAT_MASK               (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1)
443
444 // TCO quadlet 2
445 #define FF_TCO2_TC_RUN                        0x00010000
446 #define FF_TCO2_WORD_CLOCK_CONV0              0x00020000
447 #define FF_TCO2_WORD_CLOCK_CONV1              0x00040000
448 #define FF_TCO2_NUM_DROPFRAMES0               0x00080000 // Unused
449 #define FF_TCO2_NUM_DROPFRAMES1               0x00100000 // Unused
450 #define FF_TCO2_SET_JAM_SYNC                  0x00200000
451 #define FF_TCO2_SET_FLYWHEEL                  0x00400000
452 #define FF_TCO2_SET_01_4                      0x01000000
453 #define FF_TCO2_SET_PULLDOWN                  0x02000000
454 #define FF_TCO2_SET_PULLUP                    0x04000000
455 #define FF_TCO2_SET_FREQ                      0x08000000
456 #define FF_TCO2_SET_TERMINATION               0x10000000
457 #define FF_TCO2_SET_INPUT0                    0x20000000
458 #define FF_TCO2_SET_INPUT1                    0x40000000
459 #define FF_TCO2_SET_FREQ_FROM_APP             0x80000000
460
461 #define FF_TCO2_WORD_CLOCK_CONV_1_1           0
462 #define FF_TCO2_WORD_CLOCK_CONV_44_48         FF_TCO2_WORD_CLOCK_CONV0
463 #define FF_TCO2_WORD_CLOCK_CONV_48_44         FF_TCO2_WORD_CLOCK_CONV1
464 #define FF_TCO2_PULL_0                        0
465 #define FF_TCO2_PULL_UP_01                    FF_TCO2_SET_PULLUP
466 #define FF_TCO2_PULL_DOWN_01                  FF_TCO2_SET_PULLDOWN
467 #define FF_TCO2_PULL_UP_40                    (FF_TCO2_SET_PULLUP|FF_TCO2_SET_01_4)
468 #define FF_TCO2_PULL_DOWN_40                  (FF_TCO2_SET_PULLDOWN|FF_TCO2_SET_01_4)
469 #define FF_TCO2_INPUT_LTC                     FF_TCO2_SET_INPUT1
470 #define FF_TCO2_INPUT_VIDEO                   FF_TCO2_SET_INPUT0
471 #define FF_TCO2_INPUT_WORD_CLOCK              0
472 #define FF_TCO2_SRATE_44_1                    0
473 #define FF_TCO2_SRATE_48                      FF_TCO2_SET_FREQ
474 #define FF_TCO2_SRATE_FROM_APP                FF_TCO2_SET_FREQ_FROM_APP
475
476 // Interpretation of the TCO software settings fields
477 #define FF_TCOPARAM_INPUT_LTC                 1
478 #define FF_TCOPARAM_INPUT_VIDEO               2
479 #define FF_TCOPARAM_INPUT_WCK                 3
480 #define FF_TCOPARAM_FRAMERATE_24fps           1
481 #define FF_TCOPARAM_FRAMERATE_25fps           2
482 #define FF_TCOPARAM_FRAMERATE_29_97fps        3
483 #define FF_TCOPARAM_FRAMERATE_29_97dfps       4
484 #define FF_TCOPARAM_FRAMERATE_30fps           5
485 #define FF_TCOPARAM_FRAMERATE_30dfps          6
486 #define FF_TCOPARAM_WORD_CLOCK_CONV_1_1       1     // 1:1
487 #define FF_TCOPARAM_WORD_CLOCK_CONV_44_48     2     // 44.1 kHz-> 48 kHz
488 #define FF_TCOPARAM_WORD_CLOCK_CONV_48_44     3     // 48 kHz -> 44.1 kHz
489 #define FF_TCOPARAM_SRATE_44_1                1     // Rate is 44.1 kHz
490 #define FF_TCOPARAM_SRATE_48                  2     // Rate is 48 kHz
491 #define FF_TCOPARAM_SRATE_FROM_APP            3
492 #define FF_TCPPARAM_PULL_NONE                 1
493 #define FF_TCOPARAM_PULL_UP_01                2     // +0.1%
494 #define FF_TCOPARAM_PULL_DOWN_01              3     // -0.1%
495 #define FF_TCOPARAM_PULL_UP_40                4     // +4.0%
496 #define FF_TCOPARAM_PULL_DOWN_40              5     // -4.0%
497 #define FF_TCOPARAM_TERMINATION_ON            1
498
499 // The state of the TCO
500 typedef struct {
501   unsigned int locked, ltc_valid;
502   unsigned int hours, minutes, seconds, frames;
503   unsigned int frame_rate;
504   unsigned int drop_frame;
505   unsigned int video_input;
506   unsigned int word_clock_state;
507   float sample_rate;
508 } FF_TCO_state_t;
509
510 // TCO state field defines
511 #define FF_TCOSTATE_FRAMERATE_24fps           1
512 #define FF_TCOSTATE_FRAMERATE_25fps           2
513 #define FF_TCOSTATE_FRAMERATE_29_97fps        3
514 #define FF_TCOSTATE_FRAMERATE_30fps           4
515 #define FF_TCOSTATE_VIDEO_NONE                0
516 #define FF_TCOSTATE_VIDEO_PAL                 1
517 #define FF_TCOSTATE_VIDEO_NTSC                2
518 #define FF_TCOSTATE_WORDCLOCK_NONE            0
519 #define FF_TCOSTATE_WORDCLOCK_1x              1
520 #define FF_TCOSTATE_WORDCLOCK_2x              2
521 #define FF_TCOSTATE_WORDCLOCK_4x              3
522
523 #endif
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