root/trunk/libffado/src/rme/fireface_def.h

Revision 1609, 29.5 kB (checked in by jwoithe, 15 years ago)

RME: provide low-level support for the channel 3/4 pad/instrument options of the Fireface-400
RME: update device documentation

Line 
1 /*
2  * Copyright (C) 2009 by Jonathan Woithe
3  *
4  * This file is part of FFADO
5  * FFADO = Free Firewire (pro-)audio drivers for linux
6  *
7  * FFADO is based upon FreeBoB.
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation, either version 2 of the License, or
12  * (at your option) version 3 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23
24 /* This file contains definitions relating to the RME Fireface interfaces
25  * (Fireface 400 and Fireface 800).  Naming convention:
26  *   RME_FF_     identifier applies to both FF400 and FF800
27  *   RME_FF400_  identifier specific to the FF400
28  *   RME_FF800_  identifier specific to the FF800
29  */
30
31 #ifndef _FIREFACE_DEF
32 #define _FIREFACE_DEF
33
34 /* Boundaries between the speed multipliers */
35 #define MIN_SPEED               30000
36 #define MIN_DOUBLE_SPEED        56000
37 #define MIN_QUAD_SPEED          112000
38 #define MAX_SPEED               210000
39
40 // A flag used to indicate the use of a 800 Mbps bus speed to various
41 // streaming registers of the FF800.
42 #define RME_FF800_STREAMING_SPEED_800 0x800
43
44 /* The Command Buffer Address (CBA) is different for the two interfaces */
45 #define RME_FF400_CMD_BUFFER    0x80100500
46 #define RME_FF800_CMD_BUFFER    0xfc88f000
47
48 /* Offsets for registers at fixed offsets from the device's command buffer address */
49 #define RME_FF_DDS_SRATE_OFS      (0*4)
50 #define RME_FF_CONF1_OFS          (5*4)
51 #define RME_FF_CONF2_OFS          (6*4)
52 #define RME_FF_CONF3_OFS          (7*4)
53 #define RME_FF400_FLASH_CMD_OFS   (8*4)       // Write only
54 #define RME_FF400_FLASH_STAT_OFS  (8*4)       // Read only
55
56 /* General register definitions */
57 #define RME_FF400_CONF_REG          (RME_FF400_CMD_BUFFER + RME_FF_CONF1_OFS)
58 #define RME_FF800_CONF_REG          (RME_FF800_CMD_BUFFER + RME_FF_CONF1_OFS)
59
60 #define RME_FF400_STREAM_INIT_REG   (RME_FF400_CMD_BUFFER)           // 3 quadlets wide
61 #define RME_FF400_STREAM_INIT_SIZE  3              // Size in quadlets
62 #define RME_FF400_STREAM_SRATE      (RME_FF400_CMD_BUFFER)
63 #define RME_FF400_STREAM_CONF0      (RME_FF400_CMD_BUFFER+4)
64 #define RME_FF400_STREAM_CONF1      (RME_FF400_CMD_BUFFER+8)
65 #define RME_FF800_STREAM_INIT_REG   0x20000001cLL                    // 3 quadlets wide
66 #define RME_FF800_STREAM_INIT_SIZE  3              // Size in quadlets
67 #define RME_FF800_STREAM_SRATE      0x20000001cLL
68 #define RME_FF800_STREAM_CONF0      (0x20000001cLL+4)
69 #define RME_FF800_STREAM_CONF1      (0x20000001cLL+8)
70 #define RME_FF400_STREAM_START_REG  (RME_FF400_CMD_BUFFER + 0x001c)  // 1 quadlet
71 #define RME_FF800_STREAM_START_REG  0x200000028LL                    // 1 quadlet
72 #define RME_FF400_STREAM_END_REG    (RME_FF400_CMD_BUFFER + 0x0004)  // 4 quadlets wide
73 #define RME_FF400_STREAM_END_SIZE   4              // Size in quadlets
74 #define RME_FF800_STREAM_END_REG    0x200000034LL                    // 3 quadlets wide
75 #define RME_FF800_STREAM_END_SIZE   3              // Size in quadlets
76
77 #define RME_FF800_HOST_LED_REG      0x200000324LL
78
79 #define RME_FF800_REVISION_REG      0x200000100LL
80
81 #define RME_FF_CHANNEL_MUTE_MASK     0x801c0000    // Write only
82 #define RME_FF_STATUS_REG0           0x801c0000    // Read only
83 #define RME_FF_STATUS_REG1           0x801c0004    // Read only
84
85 #define RME_FF_TCO_READ_REG          0x801f0000
86 #define RME_FF_TCO_WRITE_REG         0x810f0020
87
88 /* Addresses of various blocks in memory-mapped flash */
89 #define RME_FF400_FLASH_SETTINGS_ADDR       0x00060000
90 #define RME_FF400_FLASH_MIXER_VOLUME_ADDR   0x00070000
91 #define RME_FF400_FLASH_MIXER_PAN_ADDR      0x00070800
92 #define RME_FF400_FLASH_MIXER_HW_ADDR       0x00071000  /* Hardware volume settings, MIDI enable, submix */
93 #define RME_FF800_FLASH_MIXER_SHADOW_ADDR  0x3000e0000LL
94 #define RME_FF800_FLASH_MIXER_VOLUME_ADDR  0x3000e2000LL
95 #define RME_FF800_FLASH_MIXER_PAN_ADDR     0x3000e2800LL
96 #define RME_FF800_FLASH_MIXER_HW_ADDR      0x3000e3000LL  /* H/w volume settings, MIDI enable, submix */
97 #define RME_FF800_FLASH_SETTINGS_ADDR      0x3000f0000LL
98
99 /* Flash control registers */
100 #define RME_FF400_FLASH_BLOCK_ADDR_REG      0x80100288
101 #define RME_FF400_FLASH_BLOCK_SIZE_REG      0x8010028c
102 #define RME_FF400_FLASH_CMD_REG             (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_CMD_OFS)
103 #define RME_FF400_FLASH_STAT_REG            (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_STAT_OFS)
104 #define RME_FF400_FLASH_WRITE_BUFFER        0x80100290
105 #define RME_FF400_FLASH_READ_BUFFER         0x80100290
106
107 /* Flash erase control registers on the FF800 */
108 #define RME_FF800_FLASH_ERASE_VOLUME_REG    0x3fffffff4LL
109 #define RME_FF800_FLASH_ERASE_SETTINGS_REG  0x3fffffff0LL
110 #define RME_FF800_FLASH_ERASE_FIRMWARE_REG  0x3fffffff8LL
111 #define RME_FF800_FLASH_ERASE_CONFIG_REG    0x3fffffffcLL
112
113 /* Flash erase command values for the FF400 */
114 #define RME_FF400_FLASH_CMD_WRITE           0x00000001
115 #define RME_FF400_FLASH_CMD_READ            0x00000002
116 #define RME_FF400_FLASH_CMD_ERASE_VOLUME    0x0000000e
117 #define RME_FF400_FLASH_CMD_ERASE_SETTINGS  0x0000000d
118 #define RME_FF400_FLASH_CMD_ERASE_CONFIG    0x0000000c
119 #define RME_FF400_FLASH_CMD_GET_REVISION    0x0000000f
120
121 /* Flags for use with erase_flash() */
122 #define RME_FF_FLASH_ERASE_VOLUME           1
123 #define RME_FF_FLASH_ERASE_SETTINGS         2
124 #define RME_FF_FLASH_ERASE_CONFIG           3
125
126 /* Defines for components of the control registers */
127 // Configuration register 0
128 #define CR0_PHANTOM_MIC0        0x00000001
129
130 #define CR0_PHANTOM_MIC2        0x00000002
131 #define CR0_FILTER_FPGA         0x00000004
132 #define CR0_BIT01               0x00000002  // Use depends on model - see below
133 #define CR0_BIT02               0x00000004  // Use depends on model - see below
134 #define CR0_ILEVEL_FPGA_CTRL0   0x00000008
135 #define CR0_ILEVEL_FPGA_CTRL1   0x00000010
136 #define CR0_ILEVEL_FPGA_CTRL2   0x00000020
137 #define CR0_ZEROBIT06           0x00000040
138 #define CR0_PHANTOM_MIC1        0x00000080
139 #define CR0_BIT08               0x00000100  // Use depends on model - see below
140 #define CR0_BIT09               0x00000200  // Use depends on model - see below
141 #define CRO_OLEVEL_FPGA_CTRL_0  0x00000400
142 #define CRO_OLEVEL_FPGA_CTRL_1  0x00000800
143 #define CRO_OLEVEL_FPGA_CTRL_2  0x00001000
144 #define CR0_ZEROBIT13           0x00002000
145 #define CRO_ZEROBIT14           0x00004000
146 #define CRO_ZEROBIT15           0x00008000
147 #define CRO_PHLEVEL_CTRL0       0x00010000
148 #define CRO_PHLEVEL_CTRL1       0x00020000
149
150 #define CR0_FF400_PHANTOM_MIC0  CR0_PHANTOM_MIC0
151 #define CR0_FF400_PHANTOM_MIC1  CR0_PHANTOM_MIC1
152 #define CR0_FF400_CH3_PAD       CR0_BIT08
153 #define CR0_FF400_CH3_INSTR     CR0_BIT09
154 #define CR0_FF400_CH4_PAD       CR0_BIT01
155 #define CR0_FF400_CH4_INSTR     CR0_BIT02
156 #define CR0_FF800_PHANTOM_MIC7  CR0_PHANTOM_MIC0
157 #define CR0_FF800_PHANTOM_MIC8  CR0_PHANTOM_MIC1
158 #define CR0_FF800_PHANTOM_MIC9  CR0_BIT01
159 #define CR0_FF800_PHANTOM_MIC10 CR0_BIT08
160 #define CR0_FF800_FILTER_FPGA   CR0_BIT02
161 #define CR0_FF800_DRIVE_FPGA    CR0_BIT09
162 #define CR0_ILEVEL_FPGA_LOGAIN  CR0_ILEVEL_FPGA_CTRL0
163 #define CR0_ILEVEL_FPGA_4dBU    CR0_ILEVEL_FPGA_CTRL1
164 #define CR0_ILEVEL_FPGA_m10dBV  CR0_ILEVEL_FPGA_CTRL2
165 #define CR0_OLEVEL_FPGA_HIGAIN  CRO_OLEVEL_FPGA_CTRL_0
166 #define CR0_OLEVEL_FPGA_4dBU    CRO_OLEVEL_FPGA_CTRL_1
167 #define CR0_OLEVEL_FPGA_m10dBV  CRO_OLEVEL_FPGA_CTRL_2
168 #define CR0_PHLEVEL_4dBU        0
169 #define CRO_PHLEVEL_m10dBV      CRO_PHLEVEL_CTRL0
170 #define CRO_PHLEVEL_HIGAIN      CRO_PHLEVEL_CTRL1
171
172 // Configuration register 1
173 #define CR1_ILEVEL_CPLD_CTRL0   0x00000001
174 #define CR1_ILEVEL_CPLD_CTRL1   0x00000002
175 #define CR1_INPUT_OPT0_B        0x00000004    // Input optionset 0, option B
176 #define CR1_OLEVEL_CPLD_CTRL0   0x00000008
177 #define CR1_OLEVEL_CPLD_CTRL1   0x00000010
178 #define CR1_INPUT_OPT1_A        0x00000020    // Input optionset 1, option A
179 #define CR1_INPUT_OPT1_B        0x00000040    // Input optionset 1, option B
180 #define CR1_INPUT_OPT2_A        0x00000080    // Input optionset 2, option A
181 #define CR1_INPUT_OPT2_B        0x00000100    // Input optionset 2, option B
182 #define CR1_INSTR_DRIVE         0x00000200
183 #define CR1_INPUT_OPT0_A1       0x00000400    // Input optionset 0, option A bit 1
184 #define CR1_INPUT_OPT0_A0       0x00000800    // Input optionset 0, option A bit 0
185
186 #define CR1_ILEVEL_CPLD_LOGAIN  0
187 #define CR1_ILEVEL_CPLD_4dBU    CR1_ILEVEL_CPLD_CTRL1
188 #define CR1_ILEVEL_CPLD_m10dBV  (CR1_ILEVEL_CPLD_CTRL0 | CR1_ILEVEL_CPLD_CTRL1)
189 #define CR1_OLEVEL_CPLD_m10dBV  CR1_OLEVEL_CPLD_CTRL0
190 #define CR1_OLEVEL_CPLD_HIGAIN  CR1_OLEVEL_CPLD_CTRL1
191 #define CR1_OLEVEL_CPLD_4dBU    (CR1_OLEVEL_CPLD_CTRL0 | CR1_OLEVEL_CPLD_CTRL1)
192 #define CR1_FF800_INPUT7_FRONT  CR1_INPUT_OPT1_A
193 #define CR1_FF800_INPUT7_REAR   CR1_INPUT_OPT1_B
194 #define CR1_FF800_INPUT8_FRONT  CR1_INPUT_OPT2_A
195 #define CR1_FF800_INPUT8_REAR   CR1_INPUT_OPT2_B
196 #define CR1_FF400_INPUT3_INSTR  CR1_INPUT_OPT1_B   // To be confirmed
197 #define CR1_FF400_INPUT3_PAD    CR1_INPUT_OPT1_A   // To be confirmed
198 #define CR1_FF400_INPUT4_INSTR  CR1_INPUT_OPT2_B   // To be confirmed
199 #define CR1_FF400_INPUT4_PAD    CR1_INPUT_OPT2_A   // To be confirmed
200
201 // The input 1 "front" option is strange on the FF800 in that it is
202 // indicated using two bits.  The actual bit set depends, curiously enough,
203 // on the "speaker emulation" (aka "filter") setting.  How odd.
204 #define CR1_FF800_INPUT1_FRONT              CR1_INPUT_OPT0_A0
205 #define CR1_FF800_INPUT1_FRONT_WITH_FILTER  CR1_INPUT_OPT0_A1
206 #define CR1_FF800_INPUT1_REAR               CR1_INPUT_OPT0_B
207
208 // Configuration register 2
209 #define CR2_CLOCKMODE_AUTOSYNC  0x00000000
210 #define CR2_CLOCKMODE_MASTER    0x00000001
211 #define CR2_FREQ0               0x00000002
212 #define CR2_FREQ1               0x00000004
213 #define CR2_DSPEED              0x00000008
214 #define CR2_QSSPEED             0x00000010
215 #define CR2_SPDIF_OUT_PRO       0x00000020
216 #define CR2_SPDIF_OUT_EMP       0x00000040
217 #define CR2_SPDIF_OUT_NONAUDIO  0x00000080
218 #define CR2_SPDIF_OUT_ADAT2     0x00000100  // Optical SPDIF on ADAT2 port
219 #define CR2_SPDIF_IN_COAX       0x00000000
220 #define CR2_SPDIF_IN_ADAT2      0x00000200  // Optical SPDIF on ADAT2 port
221 #define CR2_SYNC_REF0           0x00000400
222 #define CR2_SYNC_REF1           0x00000800
223 #define CR2_SYNC_REF2           0x00001000
224 #define CR2_WORD_CLOCK_1x       0x00002000
225 #define CR2_TOGGLE_TCO          0x00004000  // Normally set to 0
226 #define CR2_P12DB_AN0           0x00010000  // Disable soft-limiter.  Normally set to 0
227 #define CR2_FF400_BIT           0x04000000  // Set on FF400, clear on FF800
228 #define CR2_TMS                 0x40000000  // Unit option, normally 0
229 #define CR2_DROP_AND_STOP       0x80000000  // Normally set to 1
230
231 #define CR2_SYNC_ADAT1          0x0
232 #define CR2_SYNC_ADAT2          (CR2_SYNC_REF0)
233 #define CR2_SYNC_SPDIF          (CR2_SYNC_REF0 | CR2_SYNC_REF1)
234 #define CR2_SYNC_WORDCLOCK      (CR2_SYNC_REF2)
235 #define CR2_SYNC_TCO            (CR2_SYNC_REF0 | CR2_SYNC_REF2)
236 #define CR2_DISABLE_LIMITER     CR2_P12DB_AN0
237
238 /* Defines for the status registers */
239 // Status register 0
240 #define SR0_ADAT1_LOCK          0x00000400
241 #define SR0_ADAT2_LOCK          0x00000800
242 #define SR0_ADAT1_SYNC          0x00001000
243 #define SR0_ADAT2_SYNC          0x00002000
244 #define SR0_SPDIF_F0            0x00004000
245 #define SR0_SPDIF_F1            0x00008000
246 #define SR0_SPDIF_F2            0x00010000
247 #define SR0_SPDIF_F3            0x00020000
248 #define SR0_SPDIF_SYNC          0x00040000
249 #define SR0_OVER                0x00080000
250 #define SR0_SPDIF_LOCK          0x00100000
251 #define SR0_SEL_SYNC_REF0       0x00400000
252 #define SR0_SEL_SYNC_REF1       0x00800000
253 #define SR0_SEL_SYNC_REF2       0x01000000
254 #define SR0_INP_FREQ0           0x02000000
255 #define SR0_INP_FREQ1           0x04000000
256 #define SR0_INP_FREQ2           0x08000000
257 #define SR0_INP_FREQ3           0x10000000
258 #define SR0_WCLK_SYNC           0x20000000
259 #define SR0_WCLK_LOCK           0x40000000
260
261 // It seems the definition of SR0 is a little different depending on whether
262 // 2 or 4 status registers are read.  In the case of a request for 2, the
263 // following additional bits are defined.
264 #define SR0_IS_STREAMING        0x00000001
265 // If 4 quadlets are requested (as is done when checking the streaming
266 // system status), the lowest 10 bits instead represent sample_rate/250 if
267 // locked to an external clock source.
268 #define SR0_STREAMING_FREQ_MASK 0x000003ff
269
270 #define SR0_ADAT1_STATUS_MASK   (SR0_ADAT1_LOCK|SR0_ADAT1_SYNC)
271 #define SR0_ADAT1_STATUS_NOLOCK 0
272 #define SR0_ADAT1_STATUS_LOCK   SR0_ADAT1_LOCK
273 #define SR0_ADAT1_STATUS_SYNC   (SR0_ADAT1_LOCK|SR0_ADAT1_SYNC)
274 #define SR0_ADAT2_STATUS_MASK   (SR0_ADAT2_LOCK|SR0_ADAT2_SYNC)
275 #define SR0_ADAT2_STATUS_NOLOCK 0
276 #define SR0_ADAT2_STATUS_LOCK   SR0_ADAT2_LOCK
277 #define SR0_ADAT2_STATUS_SYNC   (SR0_ADAT2_LOCK|SR0_ADAT2_SYNC)
278 #define SR0_SPDIF_STATUS_MASK   (SR0_SPDIF_LOCK|SR0_SPDIF_SYNC)
279 #define SR0_SPDIF_STATUS_NOLOCK 0
280 #define SR0_SPDIF_STATUS_LOCK   SR0_SPDIF_LOCK
281 #define SR0_SPDIF_STATUS_SYNC   (SR0_SPDIF_LOCK|SR0_SPDIF_SYNC)
282 #define SR0_WCLK_STATUS_MASK    (SR0_WCLK_LOCK|SR0_WCLK_SYNC)
283 #define SR0_WCLK_STATUS_NOLOCK  0
284 #define SR0_WCLK_STATUS_LOCK    SR0_WCLK_LOCK
285 #define SR0_WCLK_STATUS_SYNC    (SR0_WCLK_LOCK|SR0_WCLK_SYNC)
286
287 #define SR0_SPDIF_FREQ_MASK     (SR0_SPDIF_F0|SR0_SPDIF_F1|SR0_SPDIF_F2|SR0_SPDIF_F3)
288 #define SR0_SPDIF_FREQ_32k      SR0_SPDIF_F0
289 #define SR0_SPDIF_FREQ_44k1     SR0_SPDIF_F1
290 #define SR0_SPDIF_FREQ_48k      (SR0_SPDIF_F0|SR0_SPDIF_F1)
291 #define SR0_SPDIF_FREQ_64k      SR0_SPDIF_F2
292 #define SR0_SPDIF_FREQ_88k2     (SR0_SPDIF_F0|SR0_SPDIF_F2)
293 #define SR0_SPDIF_FREQ_96k      (SR0_SPDIF_F1|SR0_SPDIF_F2)
294 #define SR0_SPDIF_FREQ_128k     (SR0_SPDIF_F0|SR0_SPDIF_F1|SR0_SPDIF_F2)
295 #define SR0_SPDIF_FREQ_176k4    SR0_SPDIF_F3
296 #define SR0_SPDIF_FREQ_192k     (SR0_SPDIF_F0|SR0_SPDIF_F3)
297
298 #define SR0_AUTOSYNC_SRC_MASK   (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF1|SR0_SEL_SYNC_REF2)
299 #define SR0_AUTOSYNC_SRC_ADAT1  0
300 #define SR0_AUTOSYNC_SRC_ADAT2  SR0_SEL_SYNC_REF0
301 #define SR0_AUTOSYNC_SRC_SPDIF  (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF1)
302 #define SR0_AUTOSYNC_SRC_WCLK   SR0_SEL_SYNC_REF2
303 #define SR0_AUTOSYNC_SRC_TCO    (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF2)
304
305 #define SR0_AUTOSYNC_FREQ_MASK  (SR0_INP_FREQ0|SR0_INP_FREQ1|SR0_INP_FREQ2|SR0_INP_FREQ3)
306 #define SR0_AUTOSYNC_FREQ_32k   SR0_INP_FREQ0
307 #define SR0_AUTOSYNC_FREQ_44k1  SR0_INP_FREQ1
308 #define SR0_AUTOSYNC_FREQ_48k   (SR0_INP_FREQ0|SR0_INP_FREQ1)
309 #define SR0_AUTOSYNC_FREQ_64k   SR0_INP_FREQ2
310 #define SR0_AUTOSYNC_FREQ_88k2  (SR0_INP_FREQ0|SR0_INP_FREQ2)
311 #define SR0_AUTOSYNC_FREQ_96k   (SR0_INP_FREQ1|SR0_INP_FREQ2)
312 #define SR0_AUTOSYNC_FREQ_128k  (SR0_INP_FREQ0|SR0_INP_FREQ1|SR0_INP_FREQ2)
313 #define SR0_AUTOSYNC_FREQ_176k4 SR0_INP_FREQ3
314 #define SR0_AUTOSYNC_FREQ_192k  (SR0_INP_FREQ0|SR0_INP_FREQ3)
315 #define SR0_AUTOSYNC_FREQ_NONE  0
316
317 // Status register 1
318 #define SR1_CLOCK_MODE_MASTER   0x00000001
319 #define SR1_TCO_SYNC            0x00400000
320 #define SR1_TCO_LOCK            0x00800000
321
322 #define SR1_TCO_STATUS_MASK    (SR1_TCO_LOCK|SR1_TCO_SYNC)
323 #define SR1_TCO_STATUS_NOLOCK  0
324 #define SR1_TCO_STATUS_LOCK    SR1_TCO_LOCK
325 #define SR1_TCO_STATUS_SYNC    (SR1_TCO_LOCK|SR1_TCO_SYNC)
326
327 /* Structure used to store device settings in the device flash RAM.  This
328  * structure mirrors the layout in the Fireface's flash, so it cannot be
329  * altered.  Fields named as unused_* are not utilised at present.
330  */
331 typedef struct {
332     uint32_t unused_device_id;
333     uint32_t unused_device_rev;
334     uint32_t unused_asio_latency;
335     uint32_t unused_samples_per_frame;
336     uint32_t spdif_input_mode;
337     uint32_t spdif_output_emphasis;
338     uint32_t spdif_output_pro;
339     uint32_t clock_mode;
340     uint32_t spdif_output_nonaudio;
341     uint32_t sync_ref;
342     uint32_t spdif_output_mode;
343     uint32_t unused_check_input;
344     uint32_t unused_status;
345     uint32_t unused_register[4];
346     uint32_t unused_iso_rx_channel;
347     uint32_t unused_iso_tx_channel;
348     uint32_t unused_timecode;
349     uint32_t unused_device_type;
350     uint32_t unused_number_of_devices;
351     uint32_t tms;
352     uint32_t unused_speed;
353     uint32_t unused_channels_avail_hi;
354     uint32_t unused_channels_avail_lo;
355     uint32_t limit_bandwidth;
356     uint32_t unused_bandwidth_allocated;
357     uint32_t stop_on_dropout;
358     uint32_t input_level;
359     uint32_t output_level;
360     uint32_t mic_plug_select[2];     // Front/rear select for FF800 ch 7/8
361                                      // [0] = phones level on FF400
362     uint32_t mic_phantom[4];
363     uint32_t instrument_plug_select; // Front/rear select for FF800 ch 1
364     uint32_t filter;
365     uint32_t fuzz;
366     uint32_t unused_sync_align;
367     uint32_t unused_device_index;
368     uint32_t unused_advanced_dialog;
369     uint32_t sample_rate;
370     uint32_t unused_interleaved;
371     uint32_t unused_sn;
372     uint32_t word_clock_single_speed;
373     uint32_t unused_num_channels;
374     uint32_t unused_dropped_samples;
375     uint32_t p12db_an[10];
376 } FF_device_flash_settings_t;
377
378 // Defines used to interpret device flash settings.  These appear to be
379 // arbitary from the device's perspective since the device doesn't appear to
380 // directly use these stored settings.  The driver loads the flash settings
381 // and then uses them to infer the appropriate values for the configuration
382 // registers.  The actual values used here appear to correspond more or less
383 // to the "value" returns from the GUI elements used to represent the
384 // controls under other systems.
385 #define FF_DEV_FLASH_INVALID                   0xffffffff
386 #define FF_DEV_FLASH_SPDIF_INPUT_COAX          0x00000002   // To be confirmed
387 #define FF_DEV_FLASH_SPDIF_INPUT_OPTICAL       0x00000001   // To be confirmed
388 #define FF_DEV_FLASH_SPDIF_OUTPUT_COAX         0x00000000   // To be confirmed
389 #define FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL      0x00000001   // To be confirmed
390 #define FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON  0x00000001
391 #define FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON       0x00000001
392 #define FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON  0x00000001
393 #define FF_DEV_FLASH_CLOCK_MODE_MASTER         0x00000002
394 #define FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC       0x00000001
395 #define FF_DEV_FLASH_CLOCK_MODE_SLAVE          0x00000001
396 #define FF_DEV_FLASH_SYNCREF_WORDCLOCK         0x00000001
397 #define FF_DEV_FLASH_SYNCREF_ADAT1             0x00000002
398 #define FF_DEV_FLASH_SYNCREF_ADAT2             0x00000003
399 #define FF_DEV_FLASH_SYNCREF_SPDIF             0x00000004
400 #define FF_DEV_FLASH_SYNCREC_TCO               0x00000005
401 #define FF_DEV_FLASH_ILEVEL_LOGAIN             0x00000001
402 #define FF_DEV_FLASH_ILEVEL_4dBU               0x00000002
403 #define FF_DEV_FLASH_ILEVEL_m10dBV             0x00000003
404 #define FF_DEV_FLASH_OLEVEL_HIGAIN             0x00000001
405 #define FF_DEV_FLASH_OLEVEL_4dBU               0x00000002
406 #define FF_DEV_FLASH_OLEVEL_m10dBV             0x00000003
407 #define FF_DEV_FLASH_MIC_PHANTOM_ON            0x00000001
408 #define FF_DEV_FLASH_SRATE_DDS_INACTIVE        0x00000000
409 #define FF_DEV_FLASH_WORD_CLOCK_1x             0x00000001
410 #define FF_DEV_FLASH_PLUG_SELECT_FRONT         0x00000001  // To be confirmed
411 #define FF_DEV_FLASH_PLUG_SELECT_REAR          0x00000000  // To be confirmed
412
413 // Structure used by FFADO to keep track of the device status.  This is
414 // decoupled from any structures used directly by the device, so it can be
415 // added to and ordered freely.  When making changes to the device the
416 // configuration registers must be all written to, so any function changing
417 // a parameter must have access to the complete device status.
418 typedef struct {
419     uint32_t mic_phantom[4];
420     uint32_t spdif_input_mode;
421     uint32_t spdif_output_emphasis;
422     uint32_t spdif_output_pro;
423     uint32_t spdif_output_nonaudio;
424     uint32_t spdif_output_mode;
425     uint32_t clock_mode;
426     uint32_t sync_ref;
427     uint32_t tms;
428     uint32_t limit_bandwidth;
429     uint32_t stop_on_dropout;
430     uint32_t input_level;
431     uint32_t output_level;
432     uint32_t filter;
433     uint32_t fuzz;
434     uint32_t limiter_disable;
435     uint32_t sample_rate;
436     uint32_t word_clock_single_speed;
437     uint32_t ff400_input_pad[2];       // Channels 3/4, FF400 only
438     uint32_t ff400_instr_input[2];     // Channels 3/4, FF400 only
439     uint32_t phones_level;             // Derived from fields in device flash
440     uint32_t input_opt[3];             // Derived from fields in device flash
441 } FF_software_settings_t;
442
443 // Defines used to interpret the software settings structure.  For now we
444 // use the same values as used by the device flash settings to remove the
445 // need for translation between reading the flash and copying it to the
446 // software settings structure, but in principle different values could be
447 // used given translation code.
448 #define FF_SWPARAM_INVALID                     FF_DEV_FLASH_INVALID
449 #define FF_SWPARAM_SPDIF_INPUT_COAX            FF_DEV_FLASH_SPDIF_INPUT_COAX
450 #define FF_SWPARAM_SPDIF_INPUT_OPTICAL         FF_DEV_FLASH_SPDIF_INPUT_OPTICAL
451 #define FF_SWPARAM_SPDIF_OUTPUT_COAX           FF_DEV_FLASH_SPDIF_OUTPUT_COAX
452 #define FF_SWPARAM_SPDIF_OUTPUT_OPTICAL        FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL
453 #define FF_SWPARAM_SPDIF_OUTPUT_EMPHASIS_ON    FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON
454 #define FF_SWPARAM_SPDIF_OUTPUT_PRO_ON         FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON
455 #define FF_SWPARAM_SPDIF_OUTPUT_NONAUDIO_ON    FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON
456 #define FF_SWPARAM_CLOCK_MODE_MASTER           FF_DEV_FLASH_CLOCK_MODE_MASTER
457 #define FF_SWPARAM_CLOCK_MODE_AUTOSYNC         FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC
458 #define FF_SWPARAM_CLOCK_MODE_SLAVE            FF_DEV_FLASH_CLOCK_MODE_SLAVE
459 #define FF_SWPARAM_SYNCREF_WORDCLOCK           FF_DEV_FLASH_SYNCREF_WORDCLOCK
460 #define FF_SWPARAM_SYNCREF_ADAT1               FF_DEV_FLASH_SYNCREF_ADAT1
461 #define FF_SWPARAM_SYNCREF_ADAT2               FF_DEV_FLASH_SYNCREF_ADAT2
462 #define FF_SWPARAM_SYNCREF_SPDIF               FF_DEV_FLASH_SYNCREF_SPDIF
463 #define FF_SWPARAM_SYNCREC_TCO                 FF_DEV_FLASH_SYNCREC_TCO
464 #define FF_SWPARAM_ILEVEL_LOGAIN               FF_DEV_FLASH_ILEVEL_LOGAIN
465 #define FF_SWPARAM_ILEVEL_4dBU                 FF_DEV_FLASH_ILEVEL_4dBU
466 #define FF_SWPARAM_ILEVEL_m10dBV               FF_DEV_FLASH_ILEVEL_m10dBV
467 #define FF_SWPARAM_OLEVEL_HIGAIN               FF_DEV_FLASH_OLEVEL_HIGAIN
468 #define FF_SWPARAM_OLEVEL_4dBU                 FF_DEV_FLASH_OLEVEL_4dBU
469 #define FF_SWPARAM_OLEVEL_m10dBV               FF_DEV_FLASH_OLEVEL_m10dBV
470 #define FF_SWPARAM_MIC_PHANTOM_ON              FF_DEV_FLASH_MIC_PHANTOM_ON
471 #define FF_SWPARAM_WORD_CLOCK_1x               FF_DEV_FLASH_WORD_CLOCK_1x
472 #define FF_SWPARAM_SRATE_DDS_INACTIVE          FF_DEV_FLASH_SRATE_DDS_INACTIVE
473 //
474 // The following defines refer to fields in the software parameter record
475 // which are derived from one or more fields in device flash.
476 #define FF_SWPARAM_PHONESLEVEL_HIGAIN          0x00000001
477 #define FF_SWPARAM_PHONESLEVEL_4dBU            0x00000002
478 #define FF_SWPARAM_PHONESLEVEL_m10dBV          0x00000003
479 #define FF_SWPARAM_INPUT_OPT_B                 0x00000001
480 #define FF_SWPARAM_INPUT_OPT_A                 0x00000002
481
482 #define FF_SWPARAM_FF800_INPUT_OPT_FRONT       FF_SWPARAM_INPUT_OPT_A
483 #define FF_SWPARAM_FF800_INPUT_OPT_REAR        FF_SWPARAM_INPUT_OPT_B
484
485 // The general Fireface state
486 typedef struct {
487     uint32_t is_streaming;
488     uint32_t clock_mode;
489     uint32_t autosync_source;
490     uint32_t autosync_freq;
491     uint32_t spdif_freq;
492     uint32_t adat1_sync_status, adat2_sync_status;
493     uint32_t spdif_sync_status;
494     uint32_t wclk_sync_status, tco_sync_status;
495 } FF_state_t;
496
497 #define FF_STATE_CLOCKMODE_MASTER              0
498 #define FF_STATE_CLOCKMODE_AUTOSYNC            1
499 #define FF_STATE_AUTOSYNC_SRC_NOLOCK           0
500 #define FF_STATE_AUTOSYNC_SRC_ADAT1            1
501 #define FF_STATE_AUTOSYNC_SRC_ADAT2            2
502 #define FF_STATE_AUTOSYNC_SRC_SPDIF            3
503 #define FF_STATE_AUTOSYNC_SRC_WCLK             4
504 #define FF_STATE_AUTOSYNC_SRC_TCO              5
505 #define FF_STATE_SYNC_NOLOCK                   0
506 #define FF_STATE_SYNC_LOCKED                   1
507 #define FF_STATE_SYNC_SYNCED                   2
508
509 // Data structure for the TCO (Time Code Option) state
510 typedef struct {
511     uint32_t input;
512     uint32_t frame_rate;
513     uint32_t word_clock;
514     uint32_t sample_rate;
515     uint32_t pull;
516     uint32_t termination;
517     uint32_t MTC;
518 } FF_TCO_settings_t;
519
520 // Defines used to configure selected quadlets of the TCO write space.  Some
521 // of these are also used when configuring the TCO.  The byte indices
522 // referenced in the define names are 0-based.
523
524 // TCO quadlet 0
525 #define FF_TCO0_MTC                           0x80000000
526
527 // TCO quadlet 1
528 #define FF_TCO1_TCO_lock                      0x00000001
529 #define FF_TCO1_WORD_CLOCK_INPUT_RATE0        0x00000002
530 #define FF_TCO1_WORD_CLOCK_INPUT_RATE1        0x00000004
531 #define FF_TCO1_LTC_INPUT_VALID               0x00000008
532 #define FF_TCO1_WORD_CLOCK_INPUT_VALID        0x00000010
533 #define FF_TCO1_VIDEO_INPUT_NTSC              0x00000020
534 #define FF_TCO1_VIDEO_INPUT_PAL               0x00000040
535 #define FF_TCO1_SET_TC                        0x00000100
536 #define FF_TCO1_SET_DROPFRAME                 0x00000200
537 #define FF_TCO1_LTC_FORMAT0                   0x00000400
538 #define FF_TCO1_LTC_FORMAT1                   0x00000800
539
540 #define FF_TCO1_WORD_CLOCK_INPUT_1x           0
541 #define FF_TCO1_WORD_CLOCK_INPUT_2x           FF_TCO1_WORD_CLOCK_INPUT_RATE0
542 #define FF_TCO1_WORD_CLOCK_INPUT_4x           FF_TCO1_WORD_CLOCK_INPUT_RATE1
543 #define FF_TCO1_WORD_CLOCK_INPUT_MASK         (FF_TCO1_WORD_CLOCK_INPUT_RATE0|FF_TCO1_WORD_CLOCK_INPUT_RATE1)
544 #define FF_TCO1_VIDEO_INPUT_MASK              (FF_TCO1_VIDEO_INPUT_NTSC|FF_TCO1_VIDEO_INPUT_PAL)
545 #define FF_TC01_LTC_FORMAT_24fps              0
546 #define FF_TCO1_LTC_FORMAT_25fps              FF_TCO1_LTC_FORMAT0
547 #define FF_TC01_LTC_FORMAT_29_97fps           FF_TCO1_LTC_FORMAT1
548 #define FF_TCO1_LTC_FORMAT_29_97dpfs          (FF_TCO1_LTC_FORMAT1|FF_TCO1_SET_DROPFRAME)
549 #define FF_TCO1_LTC_FORMAT_30fps              (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1)
550 #define FF_TCO1_LTC_FORMAT_30dfps             (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1|FF_TCO1_SET_DROPFRAME)
551 #define FF_TCO1_LTC_FORMAT_MASK               (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1)
552
553 // TCO quadlet 2
554 #define FF_TCO2_TC_RUN                        0x00010000
555 #define FF_TCO2_WORD_CLOCK_CONV0              0x00020000
556 #define FF_TCO2_WORD_CLOCK_CONV1              0x00040000
557 #define FF_TCO2_NUM_DROPFRAMES0               0x00080000 // Unused
558 #define FF_TCO2_NUM_DROPFRAMES1               0x00100000 // Unused
559 #define FF_TCO2_SET_JAM_SYNC                  0x00200000
560 #define FF_TCO2_SET_FLYWHEEL                  0x00400000
561 #define FF_TCO2_SET_01_4                      0x01000000
562 #define FF_TCO2_SET_PULLDOWN                  0x02000000
563 #define FF_TCO2_SET_PULLUP                    0x04000000
564 #define FF_TCO2_SET_FREQ                      0x08000000
565 #define FF_TCO2_SET_TERMINATION               0x10000000
566 #define FF_TCO2_SET_INPUT0                    0x20000000
567 #define FF_TCO2_SET_INPUT1                    0x40000000
568 #define FF_TCO2_SET_FREQ_FROM_APP             0x80000000
569
570 #define FF_TCO2_WORD_CLOCK_CONV_1_1           0
571 #define FF_TCO2_WORD_CLOCK_CONV_44_48         FF_TCO2_WORD_CLOCK_CONV0
572 #define FF_TCO2_WORD_CLOCK_CONV_48_44         FF_TCO2_WORD_CLOCK_CONV1
573 #define FF_TCO2_PULL_0                        0
574 #define FF_TCO2_PULL_UP_01                    FF_TCO2_SET_PULLUP
575 #define FF_TCO2_PULL_DOWN_01                  FF_TCO2_SET_PULLDOWN
576 #define FF_TCO2_PULL_UP_40                    (FF_TCO2_SET_PULLUP|FF_TCO2_SET_01_4)
577 #define FF_TCO2_PULL_DOWN_40                  (FF_TCO2_SET_PULLDOWN|FF_TCO2_SET_01_4)
578 #define FF_TCO2_INPUT_LTC                     FF_TCO2_SET_INPUT1
579 #define FF_TCO2_INPUT_VIDEO                   FF_TCO2_SET_INPUT0
580 #define FF_TCO2_INPUT_WORD_CLOCK              0
581 #define FF_TCO2_SRATE_44_1                    0
582 #define FF_TCO2_SRATE_48                      FF_TCO2_SET_FREQ
583 #define FF_TCO2_SRATE_FROM_APP                FF_TCO2_SET_FREQ_FROM_APP
584
585 // Interpretation of the TCO software settings fields
586 #define FF_TCOPARAM_INPUT_LTC                 1
587 #define FF_TCOPARAM_INPUT_VIDEO               2
588 #define FF_TCOPARAM_INPUT_WCK                 3
589 #define FF_TCOPARAM_FRAMERATE_24fps           1
590 #define FF_TCOPARAM_FRAMERATE_25fps           2
591 #define FF_TCOPARAM_FRAMERATE_29_97fps        3
592 #define FF_TCOPARAM_FRAMERATE_29_97dfps       4
593 #define FF_TCOPARAM_FRAMERATE_30fps           5
594 #define FF_TCOPARAM_FRAMERATE_30dfps          6
595 #define FF_TCOPARAM_WORD_CLOCK_CONV_1_1       1     // 1:1
596 #define FF_TCOPARAM_WORD_CLOCK_CONV_44_48     2     // 44.1 kHz-> 48 kHz
597 #define FF_TCOPARAM_WORD_CLOCK_CONV_48_44     3     // 48 kHz -> 44.1 kHz
598 #define FF_TCOPARAM_SRATE_44_1                1     // Rate is 44.1 kHz
599 #define FF_TCOPARAM_SRATE_48                  2     // Rate is 48 kHz
600 #define FF_TCOPARAM_SRATE_FROM_APP            3
601 #define FF_TCPPARAM_PULL_NONE                 1
602 #define FF_TCOPARAM_PULL_UP_01                2     // +0.1%
603 #define FF_TCOPARAM_PULL_DOWN_01              3     // -0.1%
604 #define FF_TCOPARAM_PULL_UP_40                4     // +4.0%
605 #define FF_TCOPARAM_PULL_DOWN_40              5     // -4.0%
606 #define FF_TCOPARAM_TERMINATION_ON            1
607
608 // The state of the TCO
609 typedef struct {
610   unsigned int locked, ltc_valid;
611   unsigned int hours, minutes, seconds, frames;
612   unsigned int frame_rate;
613   unsigned int drop_frame;
614   unsigned int video_input;
615   unsigned int word_clock_state;
616   float sample_rate;
617 } FF_TCO_state_t;
618
619 // TCO state field defines
620 #define FF_TCOSTATE_FRAMERATE_24fps           1
621 #define FF_TCOSTATE_FRAMERATE_25fps           2
622 #define FF_TCOSTATE_FRAMERATE_29_97fps        3
623 #define FF_TCOSTATE_FRAMERATE_30fps           4
624 #define FF_TCOSTATE_VIDEO_NONE                0
625 #define FF_TCOSTATE_VIDEO_PAL                 1
626 #define FF_TCOSTATE_VIDEO_NTSC                2
627 #define FF_TCOSTATE_WORDCLOCK_NONE            0
628 #define FF_TCOSTATE_WORDCLOCK_1x              1
629 #define FF_TCOSTATE_WORDCLOCK_2x              2
630 #define FF_TCOSTATE_WORDCLOCK_4x              3
631
632 #endif
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