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/* |
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* Copyright (C) 2009 by Jonathan Woithe |
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* |
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* This file is part of FFADO |
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* FFADO = Free Firewire (pro-)audio drivers for linux |
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* |
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* FFADO is based upon FreeBoB. |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 2 of the License, or |
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* (at your option) version 3 of the License. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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* |
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*/ |
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/* This file contains definitions relating to the RME Fireface interfaces |
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* (Fireface 400 and Fireface 800). Naming convention: |
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* RME_FF_ identifier applies to both FF400 and FF800 |
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* RME_FF400_ identifier specific to the FF400 |
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* RME_FF800_ identifier specific to the FF800 |
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*/ |
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#ifndef _FIREFACE_DEF |
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#define _FIREFACE_DEF |
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/* Boundaries between the speed multipliers */ |
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#define MIN_SPEED 30000 |
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#define MIN_DOUBLE_SPEED 56000 |
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#define MIN_QUAD_SPEED 112000 |
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#define MAX_SPEED 210000 |
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// A flag used to indicate the use of a 800 Mbps bus speed to various |
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// streaming registers of the FF800. |
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#define RME_FF800_STREAMING_SPEED_800 0x800 |
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/* The Command Buffer Address (CBA) is different for the two interfaces */ |
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#define RME_FF400_CMD_BUFFER 0x80100500 |
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#define RME_FF800_CMD_BUFFER 0xfc88f000 |
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/* Offsets for registers at fixed offsets from the device's command buffer address */ |
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#define RME_FF_DDS_SRATE_OFS (0*4) |
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#define RME_FF_CONF1_OFS (5*4) |
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#define RME_FF_CONF2_OFS (6*4) |
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#define RME_FF_CONF3_OFS (7*4) |
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#define RME_FF400_FLASH_CMD_OFS (8*4) // Write only |
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#define RME_FF400_FLASH_STAT_OFS (8*4) // Read only |
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/* General register definitions */ |
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#define RME_FF400_CONF_REG (RME_FF400_CMD_BUFFER + RME_FF_CONF1_OFS) |
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#define RME_FF800_CONF_REG (RME_FF800_CMD_BUFFER + RME_FF_CONF1_OFS) |
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#define RME_FF400_STREAM_INIT_REG (RME_FF400_CMD_BUFFER) // 3 quadlets wide |
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#define RME_FF400_STREAM_INIT_SIZE 3 // Size in quadlets |
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#define RME_FF400_STREAM_SRATE (RME_FF400_CMD_BUFFER) |
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#define RME_FF400_STREAM_CONF0 (RME_FF400_CMD_BUFFER+4) |
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#define RME_FF400_STREAM_CONF1 (RME_FF400_CMD_BUFFER+8) |
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#define RME_FF800_STREAM_INIT_REG 0x20000001cLL // 3 quadlets wide |
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#define RME_FF800_STREAM_INIT_SIZE 3 // Size in quadlets |
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#define RME_FF800_STREAM_SRATE 0x20000001cLL |
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#define RME_FF800_STREAM_CONF0 (0x20000001cLL+4) |
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#define RME_FF800_STREAM_CONF1 (0x20000001cLL+8) |
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#define RME_FF400_STREAM_START_REG (RME_FF400_CMD_BUFFER + 0x001c) // 1 quadlet |
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#define RME_FF800_STREAM_START_REG 0x200000028LL // 1 quadlet |
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#define RME_FF400_STREAM_END_REG (RME_FF400_CMD_BUFFER + 0x0004) // 4 quadlets wide |
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#define RME_FF400_STREAM_END_SIZE 4 // Size in quadlets |
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#define RME_FF800_STREAM_END_REG 0x200000034LL // 3 quadlets wide |
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#define RME_FF800_STREAM_END_SIZE 3 // Size in quadlets |
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#define RME_FF800_HOST_LED_REG 0x200000324LL |
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#define RME_FF800_REVISION_REG 0x200000100LL |
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#define RME_FF_CHANNEL_MUTE_MASK 0x801c0000 // Write only |
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#define RME_FF_STATUS_REG0 0x801c0000 // Read only |
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#define RME_FF_STATUS_REG1 0x801c0004 // Read only |
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#define RME_FF_TCO_READ_REG 0x801f0000 |
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#define RME_FF_TCO_WRITE_REG 0x810f0020 |
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#define RME_FF400_GAIN_REG 0x801c0180 |
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/* Addresses of various blocks in memory-mapped flash */ |
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#define RME_FF400_FLASH_SETTINGS_ADDR 0x00060000 |
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#define RME_FF400_FLASH_MIXER_VOLUME_ADDR 0x00070000 |
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#define RME_FF400_FLASH_MIXER_PAN_ADDR 0x00070800 |
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#define RME_FF400_FLASH_MIXER_HW_ADDR 0x00071000 /* Hardware volume settings, MIDI enable, submix */ |
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#define RME_FF800_FLASH_MIXER_SHADOW_ADDR 0x3000e0000LL |
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#define RME_FF800_FLASH_MIXER_VOLUME_ADDR 0x3000e2000LL |
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#define RME_FF800_FLASH_MIXER_PAN_ADDR 0x3000e2800LL |
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#define RME_FF800_FLASH_MIXER_HW_ADDR 0x3000e3000LL /* H/w volume settings, MIDI enable, submix */ |
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#define RME_FF800_FLASH_SETTINGS_ADDR 0x3000f0000LL |
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/* Flash control registers */ |
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#define RME_FF400_FLASH_BLOCK_ADDR_REG 0x80100288 |
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#define RME_FF400_FLASH_BLOCK_SIZE_REG 0x8010028c |
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#define RME_FF400_FLASH_CMD_REG (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_CMD_OFS) |
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#define RME_FF400_FLASH_STAT_REG (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_STAT_OFS) |
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#define RME_FF400_FLASH_WRITE_BUFFER 0x80100290 |
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#define RME_FF400_FLASH_READ_BUFFER 0x80100290 |
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/* Flash erase control registers on the FF800 */ |
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#define RME_FF800_FLASH_ERASE_VOLUME_REG 0x3fffffff4LL |
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#define RME_FF800_FLASH_ERASE_SETTINGS_REG 0x3fffffff0LL |
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#define RME_FF800_FLASH_ERASE_FIRMWARE_REG 0x3fffffff8LL |
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#define RME_FF800_FLASH_ERASE_CONFIG_REG 0x3fffffffcLL |
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/* Flash erase command values for the FF400 */ |
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#define RME_FF400_FLASH_CMD_WRITE 0x00000001 |
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#define RME_FF400_FLASH_CMD_READ 0x00000002 |
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#define RME_FF400_FLASH_CMD_ERASE_VOLUME 0x0000000e |
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#define RME_FF400_FLASH_CMD_ERASE_SETTINGS 0x0000000d |
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#define RME_FF400_FLASH_CMD_ERASE_CONFIG 0x0000000c |
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#define RME_FF400_FLASH_CMD_GET_REVISION 0x0000000f |
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/* Flags for use with erase_flash() */ |
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#define RME_FF_FLASH_ERASE_VOLUME 1 |
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#define RME_FF_FLASH_ERASE_SETTINGS 2 |
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#define RME_FF_FLASH_ERASE_CONFIG 3 |
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/* Defines for components of the control registers */ |
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// Configuration register 0 |
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#define CR0_PHANTOM_MIC0 0x00000001 |
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#define CR0_PHANTOM_MIC2 0x00000002 |
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#define CR0_FILTER_FPGA 0x00000004 |
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#define CR0_BIT01 0x00000002 // Use depends on model - see below |
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#define CR0_BIT02 0x00000004 // Use depends on model - see below |
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#define CR0_ILEVEL_FPGA_CTRL0 0x00000008 |
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#define CR0_ILEVEL_FPGA_CTRL1 0x00000010 |
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#define CR0_ILEVEL_FPGA_CTRL2 0x00000020 |
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#define CR0_ZEROBIT06 0x00000040 |
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#define CR0_PHANTOM_MIC1 0x00000080 |
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#define CR0_BIT08 0x00000100 // Use depends on model - see below |
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#define CR0_BIT09 0x00000200 // Use depends on model - see below |
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#define CRO_OLEVEL_FPGA_CTRL_0 0x00000400 |
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#define CRO_OLEVEL_FPGA_CTRL_1 0x00000800 |
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#define CRO_OLEVEL_FPGA_CTRL_2 0x00001000 |
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#define CR0_ZEROBIT13 0x00002000 |
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#define CRO_ZEROBIT14 0x00004000 |
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#define CRO_ZEROBIT15 0x00008000 |
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#define CRO_PHLEVEL_CTRL0 0x00010000 |
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#define CRO_PHLEVEL_CTRL1 0x00020000 |
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#define CR0_FF400_PHANTOM_MIC0 CR0_PHANTOM_MIC0 |
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#define CR0_FF400_PHANTOM_MIC1 CR0_PHANTOM_MIC1 |
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#define CR0_FF400_CH3_PAD CR0_BIT08 |
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#define CR0_FF400_CH3_INSTR CR0_BIT09 |
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#define CR0_FF400_CH4_PAD CR0_BIT01 |
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#define CR0_FF400_CH4_INSTR CR0_BIT02 |
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#define CR0_FF800_PHANTOM_MIC7 CR0_PHANTOM_MIC0 |
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#define CR0_FF800_PHANTOM_MIC8 CR0_PHANTOM_MIC1 |
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#define CR0_FF800_PHANTOM_MIC9 CR0_BIT01 |
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#define CR0_FF800_PHANTOM_MIC10 CR0_BIT08 |
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#define CR0_FF800_FILTER_FPGA CR0_BIT02 |
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#define CR0_FF800_DRIVE_FPGA CR0_BIT09 |
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#define CR0_ILEVEL_FPGA_LOGAIN CR0_ILEVEL_FPGA_CTRL0 |
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#define CR0_ILEVEL_FPGA_4dBU CR0_ILEVEL_FPGA_CTRL1 |
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#define CR0_ILEVEL_FPGA_m10dBV CR0_ILEVEL_FPGA_CTRL2 |
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#define CR0_OLEVEL_FPGA_HIGAIN CRO_OLEVEL_FPGA_CTRL_0 |
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#define CR0_OLEVEL_FPGA_4dBU CRO_OLEVEL_FPGA_CTRL_1 |
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#define CR0_OLEVEL_FPGA_m10dBV CRO_OLEVEL_FPGA_CTRL_2 |
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#define CR0_PHLEVEL_4dBU 0 |
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#define CRO_PHLEVEL_m10dBV CRO_PHLEVEL_CTRL0 |
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#define CRO_PHLEVEL_HIGAIN CRO_PHLEVEL_CTRL1 |
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// Configuration register 1 |
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#define CR1_ILEVEL_CPLD_CTRL0 0x00000001 |
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#define CR1_ILEVEL_CPLD_CTRL1 0x00000002 |
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#define CR1_INPUT_OPT0_B 0x00000004 // Input optionset 0, option B |
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#define CR1_OLEVEL_CPLD_CTRL0 0x00000008 |
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#define CR1_OLEVEL_CPLD_CTRL1 0x00000010 |
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#define CR1_INPUT_OPT1_A 0x00000020 // Input optionset 1, option A |
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#define CR1_INPUT_OPT1_B 0x00000040 // Input optionset 1, option B |
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#define CR1_INPUT_OPT2_A 0x00000080 // Input optionset 2, option A |
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#define CR1_INPUT_OPT2_B 0x00000100 // Input optionset 2, option B |
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#define CR1_INSTR_DRIVE 0x00000200 |
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#define CR1_INPUT_OPT0_A1 0x00000400 // Input optionset 0, option A bit 1 |
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#define CR1_INPUT_OPT0_A0 0x00000800 // Input optionset 0, option A bit 0 |
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#define CR1_ILEVEL_CPLD_LOGAIN 0 |
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#define CR1_ILEVEL_CPLD_4dBU CR1_ILEVEL_CPLD_CTRL1 |
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#define CR1_ILEVEL_CPLD_m10dBV (CR1_ILEVEL_CPLD_CTRL0 | CR1_ILEVEL_CPLD_CTRL1) |
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#define CR1_OLEVEL_CPLD_m10dBV CR1_OLEVEL_CPLD_CTRL0 |
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#define CR1_OLEVEL_CPLD_HIGAIN CR1_OLEVEL_CPLD_CTRL1 |
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#define CR1_OLEVEL_CPLD_4dBU (CR1_OLEVEL_CPLD_CTRL0 | CR1_OLEVEL_CPLD_CTRL1) |
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#define CR1_FF800_INPUT7_FRONT CR1_INPUT_OPT1_A |
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#define CR1_FF800_INPUT7_REAR CR1_INPUT_OPT1_B |
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#define CR1_FF800_INPUT8_FRONT CR1_INPUT_OPT2_A |
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#define CR1_FF800_INPUT8_REAR CR1_INPUT_OPT2_B |
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#define CR1_FF400_INPUT3_INSTR CR1_INPUT_OPT1_B // To be confirmed |
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#define CR1_FF400_INPUT3_PAD CR1_INPUT_OPT1_A // To be confirmed |
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#define CR1_FF400_INPUT4_INSTR CR1_INPUT_OPT2_B // To be confirmed |
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#define CR1_FF400_INPUT4_PAD CR1_INPUT_OPT2_A // To be confirmed |
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// The input 1 "front" option is strange on the FF800 in that it is |
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// indicated using two bits. The actual bit set depends, curiously enough, |
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// on the "speaker emulation" (aka "filter") setting. How odd. |
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#define CR1_FF800_INPUT1_FRONT CR1_INPUT_OPT0_A0 |
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#define CR1_FF800_INPUT1_FRONT_WITH_FILTER CR1_INPUT_OPT0_A1 |
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#define CR1_FF800_INPUT1_REAR CR1_INPUT_OPT0_B |
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// Configuration register 2 |
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#define CR2_CLOCKMODE_AUTOSYNC 0x00000000 |
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#define CR2_CLOCKMODE_MASTER 0x00000001 |
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#define CR2_FREQ0 0x00000002 |
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#define CR2_FREQ1 0x00000004 |
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#define CR2_DSPEED 0x00000008 |
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#define CR2_QSSPEED 0x00000010 |
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#define CR2_SPDIF_OUT_PRO 0x00000020 |
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#define CR2_SPDIF_OUT_EMP 0x00000040 |
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#define CR2_SPDIF_OUT_NONAUDIO 0x00000080 |
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#define CR2_SPDIF_OUT_ADAT2 0x00000100 // Optical SPDIF on ADAT2 port |
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#define CR2_SPDIF_IN_COAX 0x00000000 |
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#define CR2_SPDIF_IN_ADAT2 0x00000200 // Optical SPDIF on ADAT2 port |
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#define CR2_SYNC_REF0 0x00000400 |
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#define CR2_SYNC_REF1 0x00000800 |
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#define CR2_SYNC_REF2 0x00001000 |
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#define CR2_WORD_CLOCK_1x 0x00002000 |
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#define CR2_TOGGLE_TCO 0x00004000 // Normally set to 0 |
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#define CR2_P12DB_AN0 0x00010000 // Disable soft-limiter. Normally set to 0 |
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#define CR2_FF400_BIT 0x04000000 // Set on FF400, clear on FF800 |
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#define CR2_TMS 0x40000000 // Unit option, normally 0 |
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#define CR2_DROP_AND_STOP 0x80000000 // Normally set to 1 |
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#define CR2_SYNC_ADAT1 0x0 |
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#define CR2_SYNC_ADAT2 (CR2_SYNC_REF0) |
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#define CR2_SYNC_SPDIF (CR2_SYNC_REF0 | CR2_SYNC_REF1) |
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#define CR2_SYNC_WORDCLOCK (CR2_SYNC_REF2) |
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#define CR2_SYNC_TCO (CR2_SYNC_REF0 | CR2_SYNC_REF2) |
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#define CR2_DISABLE_LIMITER CR2_P12DB_AN0 |
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/* Defines for the status registers */ |
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// Status register 0 |
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#define SR0_ADAT1_LOCK 0x00000400 |
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#define SR0_ADAT2_LOCK 0x00000800 |
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#define SR0_ADAT1_SYNC 0x00001000 |
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#define SR0_ADAT2_SYNC 0x00002000 |
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#define SR0_SPDIF_F0 0x00004000 |
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#define SR0_SPDIF_F1 0x00008000 |
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#define SR0_SPDIF_F2 0x00010000 |
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#define SR0_SPDIF_F3 0x00020000 |
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#define SR0_SPDIF_SYNC 0x00040000 |
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#define SR0_OVER 0x00080000 |
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#define SR0_SPDIF_LOCK 0x00100000 |
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#define SR0_SEL_SYNC_REF0 0x00400000 |
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#define SR0_SEL_SYNC_REF1 0x00800000 |
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| 255 |
#define SR0_SEL_SYNC_REF2 0x01000000 |
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| 256 |
#define SR0_INP_FREQ0 0x02000000 |
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#define SR0_INP_FREQ1 0x04000000 |
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#define SR0_INP_FREQ2 0x08000000 |
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#define SR0_INP_FREQ3 0x10000000 |
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#define SR0_WCLK_SYNC 0x20000000 |
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| 261 |
#define SR0_WCLK_LOCK 0x40000000 |
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| 262 |
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// The lowest 10 bits of SR0 represent sample_rate/250 if locked to an |
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// external clock source. |
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#define SR0_STREAMING_FREQ_MASK 0x000003ff |
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| 266 |
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#define SR0_ADAT1_STATUS_MASK (SR0_ADAT1_LOCK|SR0_ADAT1_SYNC) |
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| 268 |
#define SR0_ADAT1_STATUS_NOLOCK 0 |
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#define SR0_ADAT1_STATUS_LOCK SR0_ADAT1_LOCK |
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#define SR0_ADAT1_STATUS_SYNC (SR0_ADAT1_LOCK|SR0_ADAT1_SYNC) |
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| 271 |
#define SR0_ADAT2_STATUS_MASK (SR0_ADAT2_LOCK|SR0_ADAT2_SYNC) |
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#define SR0_ADAT2_STATUS_NOLOCK 0 |
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#define SR0_ADAT2_STATUS_LOCK SR0_ADAT2_LOCK |
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#define SR0_ADAT2_STATUS_SYNC (SR0_ADAT2_LOCK|SR0_ADAT2_SYNC) |
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#define SR0_SPDIF_STATUS_MASK (SR0_SPDIF_LOCK|SR0_SPDIF_SYNC) |
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#define SR0_SPDIF_STATUS_NOLOCK 0 |
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#define SR0_SPDIF_STATUS_LOCK SR0_SPDIF_LOCK |
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| 278 |
#define SR0_SPDIF_STATUS_SYNC (SR0_SPDIF_LOCK|SR0_SPDIF_SYNC) |
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#define SR0_WCLK_STATUS_MASK (SR0_WCLK_LOCK|SR0_WCLK_SYNC) |
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| 280 |
#define SR0_WCLK_STATUS_NOLOCK 0 |
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| 281 |
#define SR0_WCLK_STATUS_LOCK SR0_WCLK_LOCK |
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| 282 |
#define SR0_WCLK_STATUS_SYNC (SR0_WCLK_LOCK|SR0_WCLK_SYNC) |
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| 283 |
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| 284 |
#define SR0_SPDIF_FREQ_MASK (SR0_SPDIF_F0|SR0_SPDIF_F1|SR0_SPDIF_F2|SR0_SPDIF_F3) |
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#define SR0_SPDIF_FREQ_32k SR0_SPDIF_F0 |
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| 286 |
#define SR0_SPDIF_FREQ_44k1 SR0_SPDIF_F1 |
|---|
| 287 |
#define SR0_SPDIF_FREQ_48k (SR0_SPDIF_F0|SR0_SPDIF_F1) |
|---|
| 288 |
#define SR0_SPDIF_FREQ_64k SR0_SPDIF_F2 |
|---|
| 289 |
#define SR0_SPDIF_FREQ_88k2 (SR0_SPDIF_F0|SR0_SPDIF_F2) |
|---|
| 290 |
#define SR0_SPDIF_FREQ_96k (SR0_SPDIF_F1|SR0_SPDIF_F2) |
|---|
| 291 |
#define SR0_SPDIF_FREQ_128k (SR0_SPDIF_F0|SR0_SPDIF_F1|SR0_SPDIF_F2) |
|---|
| 292 |
#define SR0_SPDIF_FREQ_176k4 SR0_SPDIF_F3 |
|---|
| 293 |
#define SR0_SPDIF_FREQ_192k (SR0_SPDIF_F0|SR0_SPDIF_F3) |
|---|
| 294 |
|
|---|
| 295 |
#define SR0_AUTOSYNC_SRC_MASK (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF1|SR0_SEL_SYNC_REF2) |
|---|
| 296 |
#define SR0_AUTOSYNC_SRC_ADAT1 0 |
|---|
| 297 |
#define SR0_AUTOSYNC_SRC_ADAT2 SR0_SEL_SYNC_REF0 |
|---|
| 298 |
#define SR0_AUTOSYNC_SRC_SPDIF (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF1) |
|---|
| 299 |
#define SR0_AUTOSYNC_SRC_WCLK SR0_SEL_SYNC_REF2 |
|---|
| 300 |
#define SR0_AUTOSYNC_SRC_TCO (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF2) |
|---|
| 301 |
#define SR0_AUTOSYNC_SRC_NONE (SR0_SEL_SYNC_REF1|SR0_SEL_SYNC_REF2) |
|---|
| 302 |
|
|---|
| 303 |
#define SR0_AUTOSYNC_FREQ_MASK (SR0_INP_FREQ0|SR0_INP_FREQ1|SR0_INP_FREQ2|SR0_INP_FREQ3) |
|---|
| 304 |
#define SR0_AUTOSYNC_FREQ_32k SR0_INP_FREQ0 |
|---|
| 305 |
#define SR0_AUTOSYNC_FREQ_44k1 SR0_INP_FREQ1 |
|---|
| 306 |
#define SR0_AUTOSYNC_FREQ_48k (SR0_INP_FREQ0|SR0_INP_FREQ1) |
|---|
| 307 |
#define SR0_AUTOSYNC_FREQ_64k SR0_INP_FREQ2 |
|---|
| 308 |
#define SR0_AUTOSYNC_FREQ_88k2 (SR0_INP_FREQ0|SR0_INP_FREQ2) |
|---|
| 309 |
#define SR0_AUTOSYNC_FREQ_96k (SR0_INP_FREQ1|SR0_INP_FREQ2) |
|---|
| 310 |
#define SR0_AUTOSYNC_FREQ_128k (SR0_INP_FREQ0|SR0_INP_FREQ1|SR0_INP_FREQ2) |
|---|
| 311 |
#define SR0_AUTOSYNC_FREQ_176k4 SR0_INP_FREQ3 |
|---|
| 312 |
#define SR0_AUTOSYNC_FREQ_192k (SR0_INP_FREQ0|SR0_INP_FREQ3) |
|---|
| 313 |
#define SR0_AUTOSYNC_FREQ_NONE 0 |
|---|
| 314 |
|
|---|
| 315 |
// Status register 1 |
|---|
| 316 |
#define SR1_CLOCK_MODE_MASTER 0x00000001 |
|---|
| 317 |
#define SR1_TCO_SYNC 0x00400000 |
|---|
| 318 |
#define SR1_TCO_LOCK 0x00800000 |
|---|
| 319 |
|
|---|
| 320 |
#define SR1_TCO_STATUS_MASK (SR1_TCO_LOCK|SR1_TCO_SYNC) |
|---|
| 321 |
#define SR1_TCO_STATUS_NOLOCK 0 |
|---|
| 322 |
#define SR1_TCO_STATUS_LOCK SR1_TCO_LOCK |
|---|
| 323 |
#define SR1_TCO_STATUS_SYNC (SR1_TCO_LOCK|SR1_TCO_SYNC) |
|---|
| 324 |
|
|---|
| 325 |
/* Structure used to store device settings in the device flash RAM. This |
|---|
| 326 |
* structure mirrors the layout in the Fireface's flash, so it cannot be |
|---|
| 327 |
* altered. Fields named as unused_* are not utilised at present. |
|---|
| 328 |
*/ |
|---|
| 329 |
typedef struct { |
|---|
| 330 |
uint32_t unused_device_id; |
|---|
| 331 |
uint32_t unused_device_rev; |
|---|
| 332 |
uint32_t unused_asio_latency; |
|---|
| 333 |
uint32_t unused_samples_per_frame; |
|---|
| 334 |
uint32_t spdif_input_mode; |
|---|
| 335 |
uint32_t spdif_output_emphasis; |
|---|
| 336 |
uint32_t spdif_output_pro; |
|---|
| 337 |
uint32_t clock_mode; |
|---|
| 338 |
uint32_t spdif_output_nonaudio; |
|---|
| 339 |
uint32_t sync_ref; |
|---|
| 340 |
uint32_t spdif_output_mode; |
|---|
| 341 |
uint32_t unused_check_input; |
|---|
| 342 |
uint32_t unused_status; |
|---|
| 343 |
uint32_t unused_register[4]; |
|---|
| 344 |
uint32_t unused_iso_rx_channel; |
|---|
| 345 |
uint32_t unused_iso_tx_channel; |
|---|
| 346 |
uint32_t unused_timecode; |
|---|
| 347 |
uint32_t unused_device_type; |
|---|
| 348 |
uint32_t unused_number_of_devices; |
|---|
| 349 |
uint32_t tms; |
|---|
| 350 |
uint32_t unused_speed; |
|---|
| 351 |
uint32_t unused_channels_avail_hi; |
|---|
| 352 |
uint32_t unused_channels_avail_lo; |
|---|
| 353 |
uint32_t limit_bandwidth; |
|---|
| 354 |
uint32_t unused_bandwidth_allocated; |
|---|
| 355 |
uint32_t stop_on_dropout; |
|---|
| 356 |
uint32_t input_level; |
|---|
| 357 |
uint32_t output_level; |
|---|
| 358 |
uint32_t mic_plug_select[2]; // Front/rear select for FF800 ch 7/8 |
|---|
| 359 |
// [0] = phones level on FF400 |
|---|
| 360 |
uint32_t mic_phantom[4]; |
|---|
| 361 |
uint32_t instrument_plug_select; // Front/rear select for FF800 ch 1 |
|---|
| 362 |
uint32_t filter; |
|---|
| 363 |
uint32_t fuzz; |
|---|
| 364 |
uint32_t unused_sync_align; |
|---|
| 365 |
uint32_t unused_device_index; |
|---|
| 366 |
uint32_t unused_advanced_dialog; |
|---|
| 367 |
uint32_t sample_rate; |
|---|
| 368 |
uint32_t unused_interleaved; |
|---|
| 369 |
uint32_t unused_sn; |
|---|
| 370 |
uint32_t word_clock_single_speed; |
|---|
| 371 |
uint32_t unused_num_channels; |
|---|
| 372 |
uint32_t unused_dropped_samples; |
|---|
| 373 |
uint32_t p12db_an[10]; |
|---|
| 374 |
} FF_device_flash_settings_t; |
|---|
| 375 |
|
|---|
| 376 |
// Defines used to interpret device flash settings. These appear to be |
|---|
| 377 |
// arbitary from the device's perspective since the device doesn't appear to |
|---|
| 378 |
// directly use these stored settings. The driver loads the flash settings |
|---|
| 379 |
// and then uses them to infer the appropriate values for the configuration |
|---|
| 380 |
// registers. The actual values used here appear to correspond more or less |
|---|
| 381 |
// to the "value" returns from the GUI elements used to represent the |
|---|
| 382 |
// controls under other systems. |
|---|
| 383 |
#define FF_DEV_FLASH_INVALID 0xffffffff |
|---|
| 384 |
#define FF_DEV_FLASH_SPDIF_INPUT_COAX 0x00000002 // To be confirmed |
|---|
| 385 |
#define FF_DEV_FLASH_SPDIF_INPUT_OPTICAL 0x00000001 // To be confirmed |
|---|
| 386 |
#define FF_DEV_FLASH_SPDIF_OUTPUT_COAX 0x00000000 // To be confirmed |
|---|
| 387 |
#define FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL 0x00000001 // To be confirmed |
|---|
| 388 |
#define FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON 0x00000001 |
|---|
| 389 |
#define FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON 0x00000001 |
|---|
| 390 |
#define FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON 0x00000001 |
|---|
| 391 |
#define FF_DEV_FLASH_BWLIMIT_SEND_ALL_CHANNELS 0x00000001 |
|---|
| 392 |
#define FF_DEV_FLASH_BWLIMIT_NO_ADAT2 0x00000002 // FF800 only |
|---|
| 393 |
#define FF_DEV_FLASH_BWLIMIT_ANALOG_SPDIF_ONLY 0x00000003 |
|---|
| 394 |
#define FF_DEV_FLASH_BWLIMIT_ANALOG_ONLY 0x00000004 |
|---|
| 395 |
#define FF_DEV_FLASH_CLOCK_MODE_MASTER 0x00000002 |
|---|
| 396 |
#define FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC 0x00000001 |
|---|
| 397 |
#define FF_DEV_FLASH_CLOCK_MODE_SLAVE 0x00000001 |
|---|
| 398 |
#define FF_DEV_FLASH_SYNCREF_WORDCLOCK 0x00000001 |
|---|
| 399 |
#define FF_DEV_FLASH_SYNCREF_ADAT1 0x00000002 |
|---|
| 400 |
#define FF_DEV_FLASH_SYNCREF_ADAT2 0x00000003 |
|---|
| 401 |
#define FF_DEV_FLASH_SYNCREF_SPDIF 0x00000004 |
|---|
| 402 |
#define FF_DEV_FLASH_SYNCREC_TCO 0x00000005 |
|---|
| 403 |
#define FF_DEV_FLASH_ILEVEL_LOGAIN 0x00000001 |
|---|
| 404 |
#define FF_DEV_FLASH_ILEVEL_4dBU 0x00000002 |
|---|
| 405 |
#define FF_DEV_FLASH_ILEVEL_m10dBV 0x00000003 |
|---|
| 406 |
#define FF_DEV_FLASH_OLEVEL_HIGAIN 0x00000001 |
|---|
| 407 |
#define FF_DEV_FLASH_OLEVEL_4dBU 0x00000002 |
|---|
| 408 |
#define FF_DEV_FLASH_OLEVEL_m10dBV 0x00000003 |
|---|
| 409 |
#define FF_DEV_FLASH_MIC_PHANTOM_ON 0x00000001 |
|---|
| 410 |
#define FF_DEV_FLASH_SRATE_DDS_INACTIVE 0x00000000 |
|---|
| 411 |
#define FF_DEV_FLASH_WORD_CLOCK_1x 0x00000001 |
|---|
| 412 |
#define FF_DEV_FLASH_PLUG_SELECT_FRONT 0x00000001 // To be confirmed |
|---|
| 413 |
#define FF_DEV_FLASH_PLUG_SELECT_REAR 0x00000000 // To be confirmed |
|---|
| 414 |
|
|---|
| 415 |
// Structure used by FFADO to keep track of the device status. This is |
|---|
| 416 |
// decoupled from any structures used directly by the device, so it can be |
|---|
| 417 |
// added to and ordered freely. When making changes to the device the |
|---|
| 418 |
// configuration registers must be all written to, so any function changing |
|---|
| 419 |
// a parameter must have access to the complete device status. |
|---|
| 420 |
typedef struct { |
|---|
| 421 |
uint32_t mic_phantom[4]; |
|---|
| 422 |
uint32_t spdif_input_mode; |
|---|
| 423 |
uint32_t spdif_output_emphasis; |
|---|
| 424 |
uint32_t spdif_output_pro; |
|---|
| 425 |
uint32_t spdif_output_nonaudio; |
|---|
| 426 |
uint32_t spdif_output_mode; |
|---|
| 427 |
uint32_t clock_mode; |
|---|
| 428 |
uint32_t sync_ref; |
|---|
| 429 |
uint32_t tms; |
|---|
| 430 |
uint32_t limit_bandwidth; |
|---|
| 431 |
uint32_t stop_on_dropout; |
|---|
| 432 |
uint32_t input_level; |
|---|
| 433 |
uint32_t output_level; |
|---|
| 434 |
uint32_t filter; |
|---|
| 435 |
uint32_t fuzz; |
|---|
| 436 |
uint32_t limiter_disable; |
|---|
| 437 |
uint32_t sample_rate; |
|---|
| 438 |
uint32_t word_clock_single_speed; |
|---|
| 439 |
uint32_t ff400_input_pad[2]; // Channels 3/4, FF400 only |
|---|
| 440 |
uint32_t ff400_instr_input[2]; // Channels 3/4, FF400 only |
|---|
| 441 |
uint32_t phones_level; // Derived from fields in device flash |
|---|
| 442 |
uint32_t input_opt[3]; // Derived from fields in device flash |
|---|
| 443 |
|
|---|
| 444 |
// Other "settings" fields which are not necessarily stored in device flash |
|---|
| 445 |
int32_t amp_gains[22]; // FF400: gains of input/output amps |
|---|
| 446 |
} FF_software_settings_t; |
|---|
| 447 |
|
|---|
| 448 |
// Defines used to interpret the software settings structure. For now we |
|---|
| 449 |
// use the same values as used by the device flash settings to remove the |
|---|
| 450 |
// need for translation between reading the flash and copying it to the |
|---|
| 451 |
// software settings structure, but in principle different values could be |
|---|
| 452 |
// used given translation code. |
|---|
| 453 |
#define FF_SWPARAM_INVALID FF_DEV_FLASH_INVALID |
|---|
| 454 |
#define FF_SWPARAM_SPDIF_INPUT_COAX FF_DEV_FLASH_SPDIF_INPUT_COAX |
|---|
| 455 |
#define FF_SWPARAM_SPDIF_INPUT_OPTICAL FF_DEV_FLASH_SPDIF_INPUT_OPTICAL |
|---|
| 456 |
#define FF_SWPARAM_SPDIF_OUTPUT_COAX FF_DEV_FLASH_SPDIF_OUTPUT_COAX |
|---|
| 457 |
#define FF_SWPARAM_SPDIF_OUTPUT_OPTICAL FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL |
|---|
| 458 |
#define FF_SWPARAM_SPDIF_OUTPUT_EMPHASIS_ON FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON |
|---|
| 459 |
#define FF_SWPARAM_SPDIF_OUTPUT_PRO_ON FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON |
|---|
| 460 |
#define FF_SWPARAM_SPDIF_OUTPUT_NONAUDIO_ON FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON |
|---|
| 461 |
#define FF_SWPARAM_BWLIMIT_SEND_ALL_CHANNELS FF_DEV_FLASH_BWLIMIT_SEND_ALL_CHANNELS |
|---|
| 462 |
#define FF_SWPARAM_BWLIMIT_NO_ADAT2 FF_DEV_FLASH_BWLIMIT_NO_ADAT2 |
|---|
| 463 |
#define FF_SWPARAM_BWLIMIT_ANALOG_SPDIF_ONLY FF_DEV_FLASH_BWLIMIT_ANALOG_SPDIF_ONLY |
|---|
| 464 |
#define FF_SWPARAM_BWLIMIT_ANALOG_ONLY FF_DEV_FLASH_BWLIMIT_ANALOG_ONLY |
|---|
| 465 |
#define FF_SWPARAM_CLOCK_MODE_MASTER FF_DEV_FLASH_CLOCK_MODE_MASTER |
|---|
| 466 |
#define FF_SWPARAM_CLOCK_MODE_AUTOSYNC FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC |
|---|
| 467 |
#define FF_SWPARAM_CLOCK_MODE_SLAVE FF_DEV_FLASH_CLOCK_MODE_SLAVE |
|---|
| 468 |
#define FF_SWPARAM_SYNCREF_WORDCLOCK FF_DEV_FLASH_SYNCREF_WORDCLOCK |
|---|
| 469 |
#define FF_SWPARAM_SYNCREF_ADAT1 FF_DEV_FLASH_SYNCREF_ADAT1 |
|---|
| 470 |
#define FF_SWPARAM_SYNCREF_ADAT2 FF_DEV_FLASH_SYNCREF_ADAT2 |
|---|
| 471 |
#define FF_SWPARAM_SYNCREF_SPDIF FF_DEV_FLASH_SYNCREF_SPDIF |
|---|
| 472 |
#define FF_SWPARAM_SYNCREC_TCO FF_DEV_FLASH_SYNCREC_TCO |
|---|
| 473 |
#define FF_SWPARAM_ILEVEL_LOGAIN FF_DEV_FLASH_ILEVEL_LOGAIN |
|---|
| 474 |
#define FF_SWPARAM_ILEVEL_4dBU FF_DEV_FLASH_ILEVEL_4dBU |
|---|
| 475 |
#define FF_SWPARAM_ILEVEL_m10dBV FF_DEV_FLASH_ILEVEL_m10dBV |
|---|
| 476 |
#define FF_SWPARAM_OLEVEL_HIGAIN FF_DEV_FLASH_OLEVEL_HIGAIN |
|---|
| 477 |
#define FF_SWPARAM_OLEVEL_4dBU FF_DEV_FLASH_OLEVEL_4dBU |
|---|
| 478 |
#define FF_SWPARAM_OLEVEL_m10dBV FF_DEV_FLASH_OLEVEL_m10dBV |
|---|
| 479 |
#define FF_SWPARAM_MIC_PHANTOM_ON FF_DEV_FLASH_MIC_PHANTOM_ON |
|---|
| 480 |
#define FF_SWPARAM_WORD_CLOCK_1x FF_DEV_FLASH_WORD_CLOCK_1x |
|---|
| 481 |
#define FF_SWPARAM_SRATE_DDS_INACTIVE FF_DEV_FLASH_SRATE_DDS_INACTIVE |
|---|
| 482 |
// |
|---|
| 483 |
// The following defines refer to fields in the software parameter record |
|---|
| 484 |
// which are derived from one or more fields in device flash. |
|---|
| 485 |
#define FF_SWPARAM_PHONESLEVEL_HIGAIN 0x00000001 |
|---|
| 486 |
#define FF_SWPARAM_PHONESLEVEL_4dBU 0x00000002 |
|---|
| 487 |
#define FF_SWPARAM_PHONESLEVEL_m10dBV 0x00000003 |
|---|
| 488 |
#define FF_SWPARAM_INPUT_OPT_B 0x00000001 |
|---|
| 489 |
#define FF_SWPARAM_INPUT_OPT_A 0x00000002 |
|---|
| 490 |
|
|---|
| 491 |
#define FF_SWPARAM_FF800_INPUT_OPT_FRONT FF_SWPARAM_INPUT_OPT_A |
|---|
| 492 |
#define FF_SWPARAM_FF800_INPUT_OPT_REAR FF_SWPARAM_INPUT_OPT_B |
|---|
| 493 |
|
|---|
| 494 |
// Indices into the amp_gains array |
|---|
| 495 |
#define FF400_AMPGAIN_MIC1 0 |
|---|
| 496 |
#define FF400_AMPGAIN_MIC2 1 |
|---|
| 497 |
#define FF400_AMPGAIN_INPUT3 2 |
|---|
| 498 |
#define FF400_AMPGAIN_INPUT4 3 |
|---|
| 499 |
#define FF400_AMPGAIN_OUTPUT1 4 |
|---|
| 500 |
#define FF400_AMPGAIN_OUTPUT2 5 |
|---|
| 501 |
#define FF400_AMPGAIN_OUTPUT3 6 |
|---|
| 502 |
#define FF400_AMPGAIN_OUTPUT4 7 |
|---|
| 503 |
#define FF400_AMPGAIN_OUTPUT5 8 |
|---|
| 504 |
#define FF400_AMPGAIN_OUTPUT6 9 |
|---|
| 505 |
#define FF400_AMPGAIN_PHONES_L 10 |
|---|
| 506 |
#define FF400_AMPGAIN_PHONES_R 11 |
|---|
| 507 |
#define FF400_AMPGAIN_SPDIF1 12 |
|---|
| 508 |
#define FF400_AMPGAIN_SPDIF2 13 |
|---|
| 509 |
#define FF400_AMPGAIN_ADAT1_1 14 |
|---|
| 510 |
#define FF400_AMPGAIN_ADAT1_2 15 |
|---|
| 511 |
#define FF400_AMPGAIN_ADAT1_3 16 |
|---|
| 512 |
#define FF400_AMPGAIN_ADAT1_4 17 |
|---|
| 513 |
#define FF400_AMPGAIN_ADAT1_5 18 |
|---|
| 514 |
#define FF400_AMPGAIN_ADAT1_6 19 |
|---|
| 515 |
#define FF400_AMPGAIN_ADAT1_7 20 |
|---|
| 516 |
#define FF400_AMPGAIN_ADAT1_8 21 |
|---|
| 517 |
#define FF400_AMPGAIN_NUM 22 |
|---|
| 518 |
|
|---|
| 519 |
// The general Fireface state |
|---|
| 520 |
typedef struct { |
|---|
| 521 |
uint32_t is_streaming; |
|---|
| 522 |
uint32_t clock_mode; |
|---|
| 523 |
uint32_t autosync_source; |
|---|
| 524 |
uint32_t autosync_freq; |
|---|
| 525 |
uint32_t spdif_freq; |
|---|
| 526 |
uint32_t adat1_sync_status, adat2_sync_status; |
|---|
| 527 |
uint32_t spdif_sync_status; |
|---|
| 528 |
uint32_t wclk_sync_status, tco_sync_status; |
|---|
| 529 |
} FF_state_t; |
|---|
| 530 |
|
|---|
| 531 |
#define FF_STATE_CLOCKMODE_MASTER 0 |
|---|
| 532 |
#define FF_STATE_CLOCKMODE_AUTOSYNC 1 |
|---|
| 533 |
#define FF_STATE_AUTOSYNC_SRC_NOLOCK 0 |
|---|
| 534 |
#define FF_STATE_AUTOSYNC_SRC_ADAT1 1 |
|---|
| 535 |
#define FF_STATE_AUTOSYNC_SRC_ADAT2 2 |
|---|
| 536 |
#define FF_STATE_AUTOSYNC_SRC_SPDIF 3 |
|---|
| 537 |
#define FF_STATE_AUTOSYNC_SRC_WCLK 4 |
|---|
| 538 |
#define FF_STATE_AUTOSYNC_SRC_TCO 5 |
|---|
| 539 |
#define FF_STATE_SYNC_NOLOCK 0 |
|---|
| 540 |
#define FF_STATE_SYNC_LOCKED 1 |
|---|
| 541 |
#define FF_STATE_SYNC_SYNCED 2 |
|---|
| 542 |
|
|---|
| 543 |
// Data structure for the TCO (Time Code Option) state |
|---|
| 544 |
typedef struct { |
|---|
| 545 |
uint32_t input; |
|---|
| 546 |
uint32_t frame_rate; |
|---|
| 547 |
uint32_t word_clock; |
|---|
| 548 |
uint32_t sample_rate; |
|---|
| 549 |
uint32_t pull; |
|---|
| 550 |
uint32_t termination; |
|---|
| 551 |
uint32_t MTC; |
|---|
| 552 |
} FF_TCO_settings_t; |
|---|
| 553 |
|
|---|
| 554 |
// Defines used to configure selected quadlets of the TCO write space. Some |
|---|
| 555 |
// of these are also used when configuring the TCO. The byte indices |
|---|
| 556 |
// referenced in the define names are 0-based. |
|---|
| 557 |
|
|---|
| 558 |
// TCO quadlet 0 |
|---|
| 559 |
#define FF_TCO0_MTC 0x80000000 |
|---|
| 560 |
|
|---|
| 561 |
// TCO quadlet 1 |
|---|
| 562 |
#define FF_TCO1_TCO_lock 0x00000001 |
|---|
| 563 |
#define FF_TCO1_WORD_CLOCK_INPUT_RATE0 0x00000002 |
|---|
| 564 |
#define FF_TCO1_WORD_CLOCK_INPUT_RATE1 0x00000004 |
|---|
| 565 |
#define FF_TCO1_LTC_INPUT_VALID 0x00000008 |
|---|
| 566 |
#define FF_TCO1_WORD_CLOCK_INPUT_VALID 0x00000010 |
|---|
| 567 |
#define FF_TCO1_VIDEO_INPUT_NTSC 0x00000020 |
|---|
| 568 |
#define FF_TCO1_VIDEO_INPUT_PAL 0x00000040 |
|---|
| 569 |
#define FF_TCO1_SET_TC 0x00000100 |
|---|
| 570 |
#define FF_TCO1_SET_DROPFRAME 0x00000200 |
|---|
| 571 |
#define FF_TCO1_LTC_FORMAT0 0x00000400 |
|---|
| 572 |
#define FF_TCO1_LTC_FORMAT1 0x00000800 |
|---|
| 573 |
|
|---|
| 574 |
#define FF_TCO1_WORD_CLOCK_INPUT_1x 0 |
|---|
| 575 |
#define FF_TCO1_WORD_CLOCK_INPUT_2x FF_TCO1_WORD_CLOCK_INPUT_RATE0 |
|---|
| 576 |
#define FF_TCO1_WORD_CLOCK_INPUT_4x FF_TCO1_WORD_CLOCK_INPUT_RATE1 |
|---|
| 577 |
#define FF_TCO1_WORD_CLOCK_INPUT_MASK (FF_TCO1_WORD_CLOCK_INPUT_RATE0|FF_TCO1_WORD_CLOCK_INPUT_RATE1) |
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| 578 |
#define FF_TCO1_VIDEO_INPUT_MASK (FF_TCO1_VIDEO_INPUT_NTSC|FF_TCO1_VIDEO_INPUT_PAL) |
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| 579 |
#define FF_TC01_LTC_FORMAT_24fps 0 |
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| 580 |
#define FF_TCO1_LTC_FORMAT_25fps FF_TCO1_LTC_FORMAT0 |
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| 581 |
#define FF_TC01_LTC_FORMAT_29_97fps FF_TCO1_LTC_FORMAT1 |
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| 582 |
#define FF_TCO1_LTC_FORMAT_29_97dpfs (FF_TCO1_LTC_FORMAT1|FF_TCO1_SET_DROPFRAME) |
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| 583 |
#define FF_TCO1_LTC_FORMAT_30fps (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1) |
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| 584 |
#define FF_TCO1_LTC_FORMAT_30dfps (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1|FF_TCO1_SET_DROPFRAME) |
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| 585 |
#define FF_TCO1_LTC_FORMAT_MASK (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1) |
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| 586 |
|
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| 587 |
// TCO quadlet 2 |
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| 588 |
#define FF_TCO2_TC_RUN 0x00010000 |
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| 589 |
#define FF_TCO2_WORD_CLOCK_CONV0 0x00020000 |
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| 590 |
#define FF_TCO2_WORD_CLOCK_CONV1 0x00040000 |
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| 591 |
#define FF_TCO2_NUM_DROPFRAMES0 0x00080000 // Unused |
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| 592 |
#define FF_TCO2_NUM_DROPFRAMES1 0x00100000 // Unused |
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| 593 |
#define FF_TCO2_SET_JAM_SYNC 0x00200000 |
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| 594 |
#define FF_TCO2_SET_FLYWHEEL 0x00400000 |
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| 595 |
#define FF_TCO2_SET_01_4 0x01000000 |
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| 596 |
#define FF_TCO2_SET_PULLDOWN 0x02000000 |
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| 597 |
#define FF_TCO2_SET_PULLUP 0x04000000 |
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| 598 |
#define FF_TCO2_SET_FREQ 0x08000000 |
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| 599 |
#define FF_TCO2_SET_TERMINATION 0x10000000 |
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| 600 |
#define FF_TCO2_SET_INPUT0 0x20000000 |
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| 601 |
#define FF_TCO2_SET_INPUT1 0x40000000 |
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| 602 |
#define FF_TCO2_SET_FREQ_FROM_APP 0x80000000 |
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| 603 |
|
|---|
| 604 |
#define FF_TCO2_WORD_CLOCK_CONV_1_1 0 |
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| 605 |
#define FF_TCO2_WORD_CLOCK_CONV_44_48 FF_TCO2_WORD_CLOCK_CONV0 |
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| 606 |
#define FF_TCO2_WORD_CLOCK_CONV_48_44 FF_TCO2_WORD_CLOCK_CONV1 |
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| 607 |
#define FF_TCO2_PULL_0 0 |
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| 608 |
#define FF_TCO2_PULL_UP_01 FF_TCO2_SET_PULLUP |
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| 609 |
#define FF_TCO2_PULL_DOWN_01 FF_TCO2_SET_PULLDOWN |
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| 610 |
#define FF_TCO2_PULL_UP_40 (FF_TCO2_SET_PULLUP|FF_TCO2_SET_01_4) |
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| 611 |
#define FF_TCO2_PULL_DOWN_40 (FF_TCO2_SET_PULLDOWN|FF_TCO2_SET_01_4) |
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| 612 |
#define FF_TCO2_INPUT_LTC FF_TCO2_SET_INPUT1 |
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| 613 |
#define FF_TCO2_INPUT_VIDEO FF_TCO2_SET_INPUT0 |
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| 614 |
#define FF_TCO2_INPUT_WORD_CLOCK 0 |
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| 615 |
#define FF_TCO2_SRATE_44_1 0 |
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| 616 |
#define FF_TCO2_SRATE_48 FF_TCO2_SET_FREQ |
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| 617 |
#define FF_TCO2_SRATE_FROM_APP FF_TCO2_SET_FREQ_FROM_APP |
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| 618 |
|
|---|
| 619 |
// Interpretation of the TCO software settings fields |
|---|
| 620 |
#define FF_TCOPARAM_INPUT_LTC 1 |
|---|
| 621 |
#define FF_TCOPARAM_INPUT_VIDEO 2 |
|---|
| 622 |
#define FF_TCOPARAM_INPUT_WCK 3 |
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| 623 |
#define FF_TCOPARAM_FRAMERATE_24fps 1 |
|---|
| 624 |
#define FF_TCOPARAM_FRAMERATE_25fps 2 |
|---|
| 625 |
#define FF_TCOPARAM_FRAMERATE_29_97fps 3 |
|---|
| 626 |
#define FF_TCOPARAM_FRAMERATE_29_97dfps 4 |
|---|
| 627 |
#define FF_TCOPARAM_FRAMERATE_30fps 5 |
|---|
| 628 |
#define FF_TCOPARAM_FRAMERATE_30dfps 6 |
|---|
| 629 |
#define FF_TCOPARAM_WORD_CLOCK_CONV_1_1 1 // 1:1 |
|---|
| 630 |
#define FF_TCOPARAM_WORD_CLOCK_CONV_44_48 2 // 44.1 kHz-> 48 kHz |
|---|
| 631 |
#define FF_TCOPARAM_WORD_CLOCK_CONV_48_44 3 // 48 kHz -> 44.1 kHz |
|---|
| 632 |
#define FF_TCOPARAM_SRATE_44_1 1 // Rate is 44.1 kHz |
|---|
| 633 |
#define FF_TCOPARAM_SRATE_48 2 // Rate is 48 kHz |
|---|
| 634 |
#define FF_TCOPARAM_SRATE_FROM_APP 3 |
|---|
| 635 |
#define FF_TCPPARAM_PULL_NONE 1 |
|---|
| 636 |
#define FF_TCOPARAM_PULL_UP_01 2 // +0.1% |
|---|
| 637 |
#define FF_TCOPARAM_PULL_DOWN_01 3 // -0.1% |
|---|
| 638 |
#define FF_TCOPARAM_PULL_UP_40 4 // +4.0% |
|---|
| 639 |
#define FF_TCOPARAM_PULL_DOWN_40 5 // -4.0% |
|---|
| 640 |
#define FF_TCOPARAM_TERMINATION_ON 1 |
|---|
| 641 |
|
|---|
| 642 |
// The state of the TCO |
|---|
| 643 |
typedef struct { |
|---|
| 644 |
unsigned int locked, ltc_valid; |
|---|
| 645 |
unsigned int hours, minutes, seconds, frames; |
|---|
| 646 |
unsigned int frame_rate; |
|---|
| 647 |
unsigned int drop_frame; |
|---|
| 648 |
unsigned int video_input; |
|---|
| 649 |
unsigned int word_clock_state; |
|---|
| 650 |
float sample_rate; |
|---|
| 651 |
} FF_TCO_state_t; |
|---|
| 652 |
|
|---|
| 653 |
// TCO state field defines |
|---|
| 654 |
#define FF_TCOSTATE_FRAMERATE_24fps 1 |
|---|
| 655 |
#define FF_TCOSTATE_FRAMERATE_25fps 2 |
|---|
| 656 |
#define FF_TCOSTATE_FRAMERATE_29_97fps 3 |
|---|
| 657 |
#define FF_TCOSTATE_FRAMERATE_30fps 4 |
|---|
| 658 |
#define FF_TCOSTATE_VIDEO_NONE 0 |
|---|
| 659 |
#define FF_TCOSTATE_VIDEO_PAL 1 |
|---|
| 660 |
#define FF_TCOSTATE_VIDEO_NTSC 2 |
|---|
| 661 |
#define FF_TCOSTATE_WORDCLOCK_NONE 0 |
|---|
| 662 |
#define FF_TCOSTATE_WORDCLOCK_1x 1 |
|---|
| 663 |
#define FF_TCOSTATE_WORDCLOCK_2x 2 |
|---|
| 664 |
#define FF_TCOSTATE_WORDCLOCK_4x 3 |
|---|
| 665 |
|
|---|
| 666 |
#endif |
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