root/trunk/libffado/src/rme/fireface_def.h

Revision 2016, 32.0 kB (checked in by jwoithe, 9 years ago)

rme: refine mute hardware mute controls. Add mute support for mixer outputs. Create dbus mixer objects to control channel muting and inversion.
matrixmixer: prepare infrastructure to allow channel muting to be controlled if enabled by the caller.

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1 /*
2  * Copyright (C) 2009 by Jonathan Woithe
3  *
4  * This file is part of FFADO
5  * FFADO = Free Firewire (pro-)audio drivers for linux
6  *
7  * FFADO is based upon FreeBoB.
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation, either version 2 of the License, or
12  * (at your option) version 3 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23
24 /* This file contains definitions relating to the RME Fireface interfaces
25  * (Fireface 400 and Fireface 800).  Naming convention:
26  *   RME_FF_     identifier applies to both FF400 and FF800
27  *   RME_FF400_  identifier specific to the FF400
28  *   RME_FF800_  identifier specific to the FF800
29  */
30
31 #ifndef _FIREFACE_DEF
32 #define _FIREFACE_DEF
33
34 /* The maximum number of channels supported by each device */
35 #define RME_FF400_MAX_CHANNELS  18
36 #define RME_FF800_MAX_CHANNELS  28
37
38 /* Boundaries between the speed multipliers */
39 #define MIN_SPEED               30000
40 #define MIN_DOUBLE_SPEED        56000
41 #define MIN_QUAD_SPEED          112000
42 #define MAX_SPEED               210000
43
44 // A flag used to indicate the use of a 800 Mbps bus speed to various
45 // streaming registers of the FF800.
46 #define RME_FF800_STREAMING_SPEED_800 0x800
47
48 /* The Command Buffer Address (CBA) is different for the two interfaces */
49 #define RME_FF400_CMD_BUFFER    0x80100500
50 #define RME_FF800_CMD_BUFFER    0xfc88f000
51
52 // Offsets for registers at fixed offsets from the device's command buffer
53 // address
54 #define RME_FF_DDS_SRATE_OFS      (0*4)
55 #define RME_FF_CONF1_OFS          (5*4)
56 #define RME_FF_CONF2_OFS          (6*4)
57 #define RME_FF_CONF3_OFS          (7*4)
58 #define RME_FF400_FLASH_CMD_OFS   (8*4)       // Write only
59 #define RME_FF400_FLASH_STAT_OFS  (8*4)       // Read only
60
61 /* General register definitions */
62 #define RME_FF400_CONF_REG          (RME_FF400_CMD_BUFFER + RME_FF_CONF1_OFS)
63 #define RME_FF800_CONF_REG          (RME_FF800_CMD_BUFFER + RME_FF_CONF1_OFS)
64
65 #define RME_FF400_STREAM_INIT_REG   (RME_FF400_CMD_BUFFER)  // 5 quadlets wide
66 #define RME_FF400_STREAM_INIT_SIZE  5                       // Size in quadlets
67 #define RME_FF400_STREAM_SRATE      (RME_FF400_CMD_BUFFER)
68 #define RME_FF400_STREAM_CONF0      (RME_FF400_CMD_BUFFER+4)
69 #define RME_FF400_STREAM_CONF1      (RME_FF400_CMD_BUFFER+8)
70 #define RME_FF800_STREAM_INIT_REG   0x20000001cLL           // 3 quadlets wide
71 #define RME_FF800_STREAM_INIT_SIZE  3                       // Size in quadlets
72 #define RME_FF800_STREAM_SRATE      0x20000001cLL
73 #define RME_FF800_STREAM_CONF0      (0x20000001cLL+4)
74 #define RME_FF800_STREAM_CONF1      (0x20000001cLL+8)
75 #define RME_FF400_STREAM_START_REG  (RME_FF400_CMD_BUFFER + 0x000c)  // 1 quadlet
76 #define RME_FF800_STREAM_START_REG  0x200000028LL                    // 1 quadlet
77 #define RME_FF400_STREAM_END_REG    (RME_FF400_CMD_BUFFER + 0x0004)  // 4 quadlets wide
78 #define RME_FF400_STREAM_END_SIZE   4              // Size in quadlets
79 #define RME_FF800_STREAM_END_REG    0x200000034LL  // 3 quadlets wide
80 #define RME_FF800_STREAM_END_SIZE   3              // Size in quadlets
81
82 #define RME_FF800_HOST_LED_REG      0x200000324LL
83
84 #define RME_FF800_REVISION_REG      0x200000100LL
85
86 #define RME_FF_CHANNEL_MUTE_MASK     0x801c0000    // Write only
87 #define RME_FF_STATUS_REG0           0x801c0000    // Read only
88 #define RME_FF_STATUS_REG1           0x801c0004    // Read only
89 #define RME_FF_STATUS_REG2           0x801c0008
90 #define RME_FF_STATUS_REG3           0x801c001c
91 #define RME_FF_OUTPUT_REC_MASK       0x801c0080    // Write only
92
93 #define RME_FF_MIXER_RAM             0x80080000
94
95 #define RME_FF_TCO_READ_REG          0x801f0000    // FF800 only
96 #define RME_FF_TCO_WRITE_REG         0x810f0020    // FF800 only
97
98 #define RME_FF400_GAIN_REG           0x801c0180
99
100 #define RME_FF400_MIDI_HIGH_ADDR     0x801003f4
101
102 /* Types of controls in the matrix mixer */
103 #define RME_FF_MM_INPUT              0x0000
104 #define RME_FF_MM_PLAYBACK           0x0001
105 #define RME_FF_MM_OUTPUT             0x0002
106
107 /* Addresses of various blocks in memory-mapped flash */
108 #define RME_FF400_FLASH_SETTINGS_ADDR       0x00060000
109 #define RME_FF400_FLASH_MIXER_VOLUME_ADDR   0x00070000
110 #define RME_FF400_FLASH_MIXER_PAN_ADDR      0x00070800
111 #define RME_FF400_FLASH_MIXER_HW_ADDR       0x00071000  /* Hardware volume settings, MIDI enable, submix */
112 #define RME_FF800_FLASH_MIXER_SHADOW_ADDR  0x3000e0000LL
113 #define RME_FF800_FLASH_MIXER_VOLUME_ADDR  0x3000e2000LL
114 #define RME_FF800_FLASH_MIXER_PAN_ADDR     0x3000e2800LL
115 #define RME_FF800_FLASH_MIXER_HW_ADDR      0x3000e3000LL  /* H/w volume settings, MIDI enable, submix */
116 #define RME_FF800_FLASH_SETTINGS_ADDR      0x3000f0000LL
117
118 /* Flash control registers */
119 #define RME_FF400_FLASH_BLOCK_ADDR_REG      0x80100288
120 #define RME_FF400_FLASH_BLOCK_SIZE_REG      0x8010028c
121 #define RME_FF400_FLASH_CMD_REG             (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_CMD_OFS)
122 #define RME_FF400_FLASH_STAT_REG            (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_STAT_OFS)
123 #define RME_FF400_FLASH_WRITE_BUFFER        0x80100290
124 #define RME_FF400_FLASH_READ_BUFFER         0x80100290
125
126 /* Flash erase control registers on the FF800 */
127 #define RME_FF800_FLASH_ERASE_VOLUME_REG    0x3fffffff4LL
128 #define RME_FF800_FLASH_ERASE_SETTINGS_REG  0x3fffffff0LL
129 #define RME_FF800_FLASH_ERASE_FIRMWARE_REG  0x3fffffff8LL
130 #define RME_FF800_FLASH_ERASE_CONFIG_REG    0x3fffffffcLL
131
132 /* Flash erase command values for the FF400 */
133 #define RME_FF400_FLASH_CMD_WRITE           0x00000001
134 #define RME_FF400_FLASH_CMD_READ            0x00000002
135 #define RME_FF400_FLASH_CMD_ERASE_VOLUME    0x0000000e
136 #define RME_FF400_FLASH_CMD_ERASE_SETTINGS  0x0000000d
137 #define RME_FF400_FLASH_CMD_ERASE_CONFIG    0x0000000c
138 #define RME_FF400_FLASH_CMD_GET_REVISION    0x0000000f
139
140 /* Flags for use with erase_flash() */
141 #define RME_FF_FLASH_ERASE_VOLUME           1
142 #define RME_FF_FLASH_ERASE_SETTINGS         2
143 #define RME_FF_FLASH_ERASE_CONFIG           3
144
145 /* Defines for components of the control registers */
146 // Configuration register 0
147 #define CR0_PHANTOM_MIC0        0x00000001
148
149 #define CR0_PHANTOM_MIC2        0x00000002
150 #define CR0_FILTER_FPGA         0x00000004
151 #define CR0_BIT01               0x00000002  // Use depends on model - see below
152 #define CR0_BIT02               0x00000004  // Use depends on model - see below
153 #define CR0_ILEVEL_FPGA_CTRL0   0x00000008
154 #define CR0_ILEVEL_FPGA_CTRL1   0x00000010
155 #define CR0_ILEVEL_FPGA_CTRL2   0x00000020
156 #define CR0_ZEROBIT06           0x00000040
157 #define CR0_PHANTOM_MIC1        0x00000080
158 #define CR0_BIT08               0x00000100  // Use depends on model - see below
159 #define CR0_BIT09               0x00000200  // Use depends on model - see below
160 #define CRO_OLEVEL_FPGA_CTRL_0  0x00000400
161 #define CRO_OLEVEL_FPGA_CTRL_1  0x00000800
162 #define CRO_OLEVEL_FPGA_CTRL_2  0x00001000
163 #define CR0_ZEROBIT13           0x00002000
164 #define CRO_ZEROBIT14           0x00004000
165 #define CRO_ZEROBIT15           0x00008000
166 #define CRO_PHLEVEL_CTRL0       0x00010000
167 #define CRO_PHLEVEL_CTRL1       0x00020000
168
169 #define CR0_FF400_PHANTOM_MIC0  CR0_PHANTOM_MIC0
170 #define CR0_FF400_PHANTOM_MIC1  CR0_PHANTOM_MIC1
171 #define CR0_FF400_CH3_PAD       CR0_BIT08
172 #define CR0_FF400_CH3_INSTR     CR0_BIT09
173 #define CR0_FF400_CH4_PAD       CR0_BIT01
174 #define CR0_FF400_CH4_INSTR     CR0_BIT02
175 #define CR0_FF800_PHANTOM_MIC7  CR0_PHANTOM_MIC0
176 #define CR0_FF800_PHANTOM_MIC8  CR0_PHANTOM_MIC1
177 #define CR0_FF800_PHANTOM_MIC9  CR0_BIT01
178 #define CR0_FF800_PHANTOM_MIC10 CR0_BIT08
179 #define CR0_FF800_FILTER_FPGA   CR0_BIT02
180 #define CR0_FF800_DRIVE_FPGA    CR0_BIT09
181 #define CR0_ILEVEL_FPGA_LOGAIN  CR0_ILEVEL_FPGA_CTRL0
182 #define CR0_ILEVEL_FPGA_4dBU    CR0_ILEVEL_FPGA_CTRL1
183 #define CR0_ILEVEL_FPGA_m10dBV  CR0_ILEVEL_FPGA_CTRL2
184 #define CR0_OLEVEL_FPGA_HIGAIN  CRO_OLEVEL_FPGA_CTRL_0
185 #define CR0_OLEVEL_FPGA_4dBU    CRO_OLEVEL_FPGA_CTRL_1
186 #define CR0_OLEVEL_FPGA_m10dBV  CRO_OLEVEL_FPGA_CTRL_2
187 #define CR0_PHLEVEL_4dBU        0
188 #define CRO_PHLEVEL_m10dBV      CRO_PHLEVEL_CTRL0
189 #define CRO_PHLEVEL_HIGAIN      CRO_PHLEVEL_CTRL1
190
191 // Configuration register 1
192 #define CR1_ILEVEL_CPLD_CTRL0   0x00000001
193 #define CR1_ILEVEL_CPLD_CTRL1   0x00000002
194 #define CR1_INPUT_OPT0_B        0x00000004    // Input optionset 0, option B
195 #define CR1_OLEVEL_CPLD_CTRL0   0x00000008
196 #define CR1_OLEVEL_CPLD_CTRL1   0x00000010
197 #define CR1_INPUT_OPT1_A        0x00000020    // Input optionset 1, option A
198 #define CR1_INPUT_OPT1_B        0x00000040    // Input optionset 1, option B
199 #define CR1_INPUT_OPT2_A        0x00000080    // Input optionset 2, option A
200 #define CR1_INPUT_OPT2_B        0x00000100    // Input optionset 2, option B
201 #define CR1_INSTR_DRIVE         0x00000200
202 #define CR1_INPUT_OPT0_A1       0x00000400    // Input optionset 0, option A bit 1
203 #define CR1_INPUT_OPT0_A0       0x00000800    // Input optionset 0, option A bit 0
204
205 #define CR1_ILEVEL_CPLD_LOGAIN  0
206 #define CR1_ILEVEL_CPLD_4dBU    CR1_ILEVEL_CPLD_CTRL1
207 #define CR1_ILEVEL_CPLD_m10dBV  (CR1_ILEVEL_CPLD_CTRL0 | CR1_ILEVEL_CPLD_CTRL1)
208 #define CR1_OLEVEL_CPLD_m10dBV  CR1_OLEVEL_CPLD_CTRL0
209 #define CR1_OLEVEL_CPLD_HIGAIN  CR1_OLEVEL_CPLD_CTRL1
210 #define CR1_OLEVEL_CPLD_4dBU    (CR1_OLEVEL_CPLD_CTRL0 | CR1_OLEVEL_CPLD_CTRL1)
211 #define CR1_FF800_INPUT7_FRONT  CR1_INPUT_OPT1_A
212 #define CR1_FF800_INPUT7_REAR   CR1_INPUT_OPT1_B
213 #define CR1_FF800_INPUT8_FRONT  CR1_INPUT_OPT2_A
214 #define CR1_FF800_INPUT8_REAR   CR1_INPUT_OPT2_B
215 #define CR1_FF400_INPUT3_INSTR  CR1_INPUT_OPT1_B   // To be confirmed
216 #define CR1_FF400_INPUT3_PAD    CR1_INPUT_OPT1_A   // To be confirmed
217 #define CR1_FF400_INPUT4_INSTR  CR1_INPUT_OPT2_B   // To be confirmed
218 #define CR1_FF400_INPUT4_PAD    CR1_INPUT_OPT2_A   // To be confirmed
219
220 // The input 1 "front" option is strange on the FF800 in that it is
221 // indicated using two bits.  The actual bit set depends, curiously enough,
222 // on the "speaker emulation" (aka "filter") setting.  How odd.
223 #define CR1_FF800_INPUT1_FRONT              CR1_INPUT_OPT0_A0
224 #define CR1_FF800_INPUT1_FRONT_WITH_FILTER  CR1_INPUT_OPT0_A1
225 #define CR1_FF800_INPUT1_REAR               CR1_INPUT_OPT0_B
226
227 // Configuration register 2
228 #define CR2_CLOCKMODE_AUTOSYNC  0x00000000
229 #define CR2_CLOCKMODE_MASTER    0x00000001
230 #define CR2_FREQ0               0x00000002
231 #define CR2_FREQ1               0x00000004
232 #define CR2_DSPEED              0x00000008
233 #define CR2_QSSPEED             0x00000010
234 #define CR2_SPDIF_OUT_PRO       0x00000020
235 #define CR2_SPDIF_OUT_EMP       0x00000040
236 #define CR2_SPDIF_OUT_NONAUDIO  0x00000080
237 #define CR2_SPDIF_OUT_ADAT2     0x00000100  // Optical SPDIF on ADAT2 port
238 #define CR2_SPDIF_IN_COAX       0x00000000
239 #define CR2_SPDIF_IN_ADAT2      0x00000200  // Optical SPDIF on ADAT2 port
240 #define CR2_SYNC_REF0           0x00000400
241 #define CR2_SYNC_REF1           0x00000800
242 #define CR2_SYNC_REF2           0x00001000
243 #define CR2_WORD_CLOCK_1x       0x00002000
244 #define CR2_TOGGLE_TCO          0x00004000  // Normally set to 0
245 #define CR2_P12DB_AN0           0x00010000  // Disable soft-limiter.  Normally set to 0
246 #define CR2_FF400_BIT           0x04000000  // Set on FF400, clear on FF800
247 #define CR2_TMS                 0x40000000  // Unit option, normally 0
248 #define CR2_DROP_AND_STOP       0x80000000  // Normally set to 1
249
250 #define CR2_SYNC_ADAT1          0x0
251 #define CR2_SYNC_ADAT2          (CR2_SYNC_REF0)
252 #define CR2_SYNC_SPDIF          (CR2_SYNC_REF0 | CR2_SYNC_REF1)
253 #define CR2_SYNC_WORDCLOCK      (CR2_SYNC_REF2)
254 #define CR2_SYNC_TCO            (CR2_SYNC_REF0 | CR2_SYNC_REF2)
255 #define CR2_DISABLE_LIMITER     CR2_P12DB_AN0
256
257 /* Defines for the status registers */
258 // Status register 0
259 #define SR0_ADAT1_LOCK          0x00000400
260 #define SR0_ADAT2_LOCK          0x00000800
261 #define SR0_ADAT1_SYNC          0x00001000
262 #define SR0_ADAT2_SYNC          0x00002000
263 #define SR0_SPDIF_F0            0x00004000
264 #define SR0_SPDIF_F1            0x00008000
265 #define SR0_SPDIF_F2            0x00010000
266 #define SR0_SPDIF_F3            0x00020000
267 #define SR0_SPDIF_SYNC          0x00040000
268 #define SR0_OVER                0x00080000
269 #define SR0_SPDIF_LOCK          0x00100000
270 #define SR0_SEL_SYNC_REF0       0x00400000
271 #define SR0_SEL_SYNC_REF1       0x00800000
272 #define SR0_SEL_SYNC_REF2       0x01000000
273 #define SR0_INP_FREQ0           0x02000000
274 #define SR0_INP_FREQ1           0x04000000
275 #define SR0_INP_FREQ2           0x08000000
276 #define SR0_INP_FREQ3           0x10000000
277 #define SR0_WCLK_SYNC           0x20000000
278 #define SR0_WCLK_LOCK           0x40000000
279
280 // The lowest 10 bits of SR0 represent sample_rate/250 if locked to an
281 // external clock source.
282 #define SR0_STREAMING_FREQ_MASK 0x000003ff
283
284 #define SR0_ADAT1_STATUS_MASK   (SR0_ADAT1_LOCK|SR0_ADAT1_SYNC)
285 #define SR0_ADAT1_STATUS_NOLOCK 0
286 #define SR0_ADAT1_STATUS_LOCK   SR0_ADAT1_LOCK
287 #define SR0_ADAT1_STATUS_SYNC   (SR0_ADAT1_LOCK|SR0_ADAT1_SYNC)
288 #define SR0_ADAT2_STATUS_MASK   (SR0_ADAT2_LOCK|SR0_ADAT2_SYNC)
289 #define SR0_ADAT2_STATUS_NOLOCK 0
290 #define SR0_ADAT2_STATUS_LOCK   SR0_ADAT2_LOCK
291 #define SR0_ADAT2_STATUS_SYNC   (SR0_ADAT2_LOCK|SR0_ADAT2_SYNC)
292 #define SR0_SPDIF_STATUS_MASK   (SR0_SPDIF_LOCK|SR0_SPDIF_SYNC)
293 #define SR0_SPDIF_STATUS_NOLOCK 0
294 #define SR0_SPDIF_STATUS_LOCK   SR0_SPDIF_LOCK
295 #define SR0_SPDIF_STATUS_SYNC   (SR0_SPDIF_LOCK|SR0_SPDIF_SYNC)
296 #define SR0_WCLK_STATUS_MASK    (SR0_WCLK_LOCK|SR0_WCLK_SYNC)
297 #define SR0_WCLK_STATUS_NOLOCK  0
298 #define SR0_WCLK_STATUS_LOCK    SR0_WCLK_LOCK
299 #define SR0_WCLK_STATUS_SYNC    (SR0_WCLK_LOCK|SR0_WCLK_SYNC)
300
301 #define SR0_SPDIF_FREQ_MASK     (SR0_SPDIF_F0|SR0_SPDIF_F1|SR0_SPDIF_F2|SR0_SPDIF_F3)
302 #define SR0_SPDIF_FREQ_32k      SR0_SPDIF_F0
303 #define SR0_SPDIF_FREQ_44k1     SR0_SPDIF_F1
304 #define SR0_SPDIF_FREQ_48k      (SR0_SPDIF_F0|SR0_SPDIF_F1)
305 #define SR0_SPDIF_FREQ_64k      SR0_SPDIF_F2
306 #define SR0_SPDIF_FREQ_88k2     (SR0_SPDIF_F0|SR0_SPDIF_F2)
307 #define SR0_SPDIF_FREQ_96k      (SR0_SPDIF_F1|SR0_SPDIF_F2)
308 #define SR0_SPDIF_FREQ_128k     (SR0_SPDIF_F0|SR0_SPDIF_F1|SR0_SPDIF_F2)
309 #define SR0_SPDIF_FREQ_176k4    SR0_SPDIF_F3
310 #define SR0_SPDIF_FREQ_192k     (SR0_SPDIF_F0|SR0_SPDIF_F3)
311
312 #define SR0_AUTOSYNC_SRC_MASK   (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF1|SR0_SEL_SYNC_REF2)
313 #define SR0_AUTOSYNC_SRC_ADAT1  0
314 #define SR0_AUTOSYNC_SRC_ADAT2  SR0_SEL_SYNC_REF0
315 #define SR0_AUTOSYNC_SRC_SPDIF  (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF1)
316 #define SR0_AUTOSYNC_SRC_WCLK   SR0_SEL_SYNC_REF2
317 #define SR0_AUTOSYNC_SRC_TCO    (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF2)
318 #define SR0_AUTOSYNC_SRC_NONE   (SR0_SEL_SYNC_REF1|SR0_SEL_SYNC_REF2)
319
320 #define SR0_AUTOSYNC_FREQ_MASK  (SR0_INP_FREQ0|SR0_INP_FREQ1|SR0_INP_FREQ2|SR0_INP_FREQ3)
321 #define SR0_AUTOSYNC_FREQ_32k   SR0_INP_FREQ0
322 #define SR0_AUTOSYNC_FREQ_44k1  SR0_INP_FREQ1
323 #define SR0_AUTOSYNC_FREQ_48k   (SR0_INP_FREQ0|SR0_INP_FREQ1)
324 #define SR0_AUTOSYNC_FREQ_64k   SR0_INP_FREQ2
325 #define SR0_AUTOSYNC_FREQ_88k2  (SR0_INP_FREQ0|SR0_INP_FREQ2)
326 #define SR0_AUTOSYNC_FREQ_96k   (SR0_INP_FREQ1|SR0_INP_FREQ2)
327 #define SR0_AUTOSYNC_FREQ_128k  (SR0_INP_FREQ0|SR0_INP_FREQ1|SR0_INP_FREQ2)
328 #define SR0_AUTOSYNC_FREQ_176k4 SR0_INP_FREQ3
329 #define SR0_AUTOSYNC_FREQ_192k  (SR0_INP_FREQ0|SR0_INP_FREQ3)
330 #define SR0_AUTOSYNC_FREQ_NONE  0
331
332 // Status register 1
333 #define SR1_CLOCK_MODE_MASTER   0x00000001
334 #define SR1_TCO_SYNC            0x00400000
335 #define SR1_TCO_LOCK            0x00800000
336
337 #define SR1_TCO_STATUS_MASK    (SR1_TCO_LOCK|SR1_TCO_SYNC)
338 #define SR1_TCO_STATUS_NOLOCK  0
339 #define SR1_TCO_STATUS_LOCK    SR1_TCO_LOCK
340 #define SR1_TCO_STATUS_SYNC    (SR1_TCO_LOCK|SR1_TCO_SYNC)
341
342 /* Structure used to store device settings in the device flash RAM.  This
343  * structure mirrors the layout in the Fireface's flash, so it cannot be
344  * altered.  Fields named as unused_* are not utilised at present.
345  */
346 typedef struct {
347     uint32_t unused_device_id;
348     uint32_t unused_device_rev;
349     uint32_t unused_asio_latency;
350     uint32_t unused_samples_per_frame;
351     uint32_t spdif_input_mode;
352     uint32_t spdif_output_emphasis;
353     uint32_t spdif_output_pro;
354     uint32_t clock_mode;
355     uint32_t spdif_output_nonaudio;
356     uint32_t sync_ref;
357     uint32_t spdif_output_mode;
358     uint32_t unused_check_input;
359     uint32_t unused_status;
360     uint32_t unused_register[4];
361     uint32_t unused_iso_rx_channel;
362     uint32_t unused_iso_tx_channel;
363     uint32_t unused_timecode;
364     uint32_t unused_device_type;
365     uint32_t unused_number_of_devices;
366     uint32_t tms;
367     uint32_t unused_speed;
368     uint32_t unused_channels_avail_hi;
369     uint32_t unused_channels_avail_lo;
370     uint32_t limit_bandwidth;
371     uint32_t unused_bandwidth_allocated;
372     uint32_t stop_on_dropout;
373     uint32_t input_level;
374     uint32_t output_level;
375     uint32_t mic_plug_select[2];     // Front/rear select for FF800 ch 7/8
376                                      // [0] = phones level on FF400
377     uint32_t mic_phantom[4];
378     uint32_t instrument_plug_select; // Front/rear select for FF800 ch 1
379     uint32_t filter;
380     uint32_t fuzz;
381     uint32_t unused_sync_align;
382     uint32_t unused_device_index;
383     uint32_t unused_advanced_dialog;
384     uint32_t sample_rate;
385     uint32_t unused_interleaved;
386     uint32_t unused_sn;
387     uint32_t word_clock_single_speed;
388     uint32_t unused_num_channels;
389     uint32_t unused_dropped_samples;
390     uint32_t p12db_an[10];
391 } FF_device_flash_settings_t;
392
393 // Defines used to interpret device flash settings.  These appear to be
394 // arbitary from the device's perspective since the device doesn't appear to
395 // directly use these stored settings.  The driver loads the flash settings
396 // and then uses them to infer the appropriate values for the configuration
397 // registers.  The actual values used here appear to correspond more or less
398 // to the "value" returns from the GUI elements used to represent the
399 // controls under other systems.
400 #define FF_DEV_FLASH_INVALID                   0xffffffff
401 #define FF_DEV_FLASH_SPDIF_INPUT_COAX          0x00000002   // To be confirmed
402 #define FF_DEV_FLASH_SPDIF_INPUT_OPTICAL       0x00000001   // To be confirmed
403 #define FF_DEV_FLASH_SPDIF_OUTPUT_COAX         0x00000000   // To be confirmed
404 #define FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL      0x00000001   // To be confirmed
405 #define FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON  0x00000001
406 #define FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON       0x00000001
407 #define FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON  0x00000001
408 #define FF_DEV_FLASH_BWLIMIT_SEND_ALL_CHANNELS 0x00000001
409 #define FF_DEV_FLASH_BWLIMIT_NO_ADAT2          0x00000002  // FF800 only
410 #define FF_DEV_FLASH_BWLIMIT_ANALOG_SPDIF_ONLY 0x00000003
411 #define FF_DEV_FLASH_BWLIMIT_ANALOG_ONLY       0x00000004
412 #define FF_DEV_FLASH_CLOCK_MODE_MASTER         0x00000002
413 #define FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC       0x00000001
414 #define FF_DEV_FLASH_CLOCK_MODE_SLAVE          0x00000001
415 #define FF_DEV_FLASH_SYNCREF_WORDCLOCK         0x00000001
416 #define FF_DEV_FLASH_SYNCREF_ADAT1             0x00000002
417 #define FF_DEV_FLASH_SYNCREF_ADAT2             0x00000003
418 #define FF_DEV_FLASH_SYNCREF_SPDIF             0x00000004
419 #define FF_DEV_FLASH_SYNCREC_TCO               0x00000005
420 #define FF_DEV_FLASH_ILEVEL_LOGAIN             0x00000001
421 #define FF_DEV_FLASH_ILEVEL_4dBU               0x00000002
422 #define FF_DEV_FLASH_ILEVEL_m10dBV             0x00000003
423 #define FF_DEV_FLASH_OLEVEL_HIGAIN             0x00000001
424 #define FF_DEV_FLASH_OLEVEL_4dBU               0x00000002
425 #define FF_DEV_FLASH_OLEVEL_m10dBV             0x00000003
426 #define FF_DEV_FLASH_MIC_PHANTOM_ON            0x00000001
427 #define FF_DEV_FLASH_SRATE_DDS_INACTIVE        0x00000000
428 #define FF_DEV_FLASH_WORD_CLOCK_1x             0x00000001
429 #define FF_DEV_FLASH_PLUG_SELECT_FRONT         0x00000001  // To be confirmed
430 #define FF_DEV_FLASH_PLUG_SELECT_REAR          0x00000000  // To be confirmed
431
432 #define FF_MATRIXMIXER_SIZE (RME_FF800_MAX_CHANNELS*RME_FF800_MAX_CHANNELS)
433
434 // Structure used by FFADO to keep track of the device status.  This is
435 // decoupled from any structures used directly by the device, so it can be
436 // added to and ordered freely.  When making changes to the device the
437 // configuration registers must be all written to, so any function changing
438 // a parameter must have access to the complete device status.
439 typedef struct {
440     uint32_t mic_phantom[4];
441     uint32_t spdif_input_mode;
442     uint32_t spdif_output_emphasis;
443     uint32_t spdif_output_pro;
444     uint32_t spdif_output_nonaudio;
445     uint32_t spdif_output_mode;
446     uint32_t clock_mode;
447     uint32_t sync_ref;
448     uint32_t tms;
449     uint32_t limit_bandwidth;
450     uint32_t stop_on_dropout;
451     uint32_t input_level;
452     uint32_t output_level;
453     uint32_t filter;
454     uint32_t fuzz;
455     uint32_t limiter_disable;
456     uint32_t sample_rate;
457     uint32_t word_clock_single_speed;
458     uint32_t ff400_input_pad[2];       // Channels 3/4, FF400 only
459     uint32_t ff400_instr_input[2];     // Channels 3/4, FF400 only
460     uint32_t phones_level;             // Derived from fields in device flash
461     uint32_t input_opt[3];             // Derived from fields in device flash
462
463     // Other "settings" fields which are not necessarily stored in device flash
464     int32_t amp_gains[22];             // FF400: gains of input/output amps
465     int32_t input_faders[FF_MATRIXMIXER_SIZE];
466     int32_t playback_faders[FF_MATRIXMIXER_SIZE];
467     int32_t output_faders[RME_FF800_MAX_CHANNELS];
468     unsigned char input_mixerflags[FF_MATRIXMIXER_SIZE];
469     unsigned char playback_mixerflags[FF_MATRIXMIXER_SIZE];
470     unsigned char output_mixerflags[FF_MATRIXMIXER_SIZE];
471 } FF_software_settings_t;
472
473 // Defines used to interpret the software settings structure.  For now we
474 // use the same values as used by the device flash settings to remove the
475 // need for translation between reading the flash and copying it to the
476 // software settings structure, but in principle different values could be
477 // used given translation code.
478 #define FF_SWPARAM_INVALID                     FF_DEV_FLASH_INVALID
479 #define FF_SWPARAM_SPDIF_INPUT_COAX            FF_DEV_FLASH_SPDIF_INPUT_COAX
480 #define FF_SWPARAM_SPDIF_INPUT_OPTICAL         FF_DEV_FLASH_SPDIF_INPUT_OPTICAL
481 #define FF_SWPARAM_SPDIF_OUTPUT_COAX           FF_DEV_FLASH_SPDIF_OUTPUT_COAX
482 #define FF_SWPARAM_SPDIF_OUTPUT_OPTICAL        FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL
483 #define FF_SWPARAM_SPDIF_OUTPUT_EMPHASIS_ON    FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON
484 #define FF_SWPARAM_SPDIF_OUTPUT_PRO_ON         FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON
485 #define FF_SWPARAM_SPDIF_OUTPUT_NONAUDIO_ON    FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON
486 #define FF_SWPARAM_BWLIMIT_SEND_ALL_CHANNELS   FF_DEV_FLASH_BWLIMIT_SEND_ALL_CHANNELS
487 #define FF_SWPARAM_BWLIMIT_NO_ADAT2            FF_DEV_FLASH_BWLIMIT_NO_ADAT2
488 #define FF_SWPARAM_BWLIMIT_ANALOG_SPDIF_ONLY   FF_DEV_FLASH_BWLIMIT_ANALOG_SPDIF_ONLY
489 #define FF_SWPARAM_BWLIMIT_ANALOG_ONLY         FF_DEV_FLASH_BWLIMIT_ANALOG_ONLY
490 #define FF_SWPARAM_CLOCK_MODE_MASTER           FF_DEV_FLASH_CLOCK_MODE_MASTER
491 #define FF_SWPARAM_CLOCK_MODE_AUTOSYNC         FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC
492 #define FF_SWPARAM_CLOCK_MODE_SLAVE            FF_DEV_FLASH_CLOCK_MODE_SLAVE
493 #define FF_SWPARAM_SYNCREF_WORDCLOCK           FF_DEV_FLASH_SYNCREF_WORDCLOCK
494 #define FF_SWPARAM_SYNCREF_ADAT1               FF_DEV_FLASH_SYNCREF_ADAT1
495 #define FF_SWPARAM_SYNCREF_ADAT2               FF_DEV_FLASH_SYNCREF_ADAT2
496 #define FF_SWPARAM_SYNCREF_SPDIF               FF_DEV_FLASH_SYNCREF_SPDIF
497 #define FF_SWPARAM_SYNCREC_TCO                 FF_DEV_FLASH_SYNCREC_TCO
498 #define FF_SWPARAM_ILEVEL_LOGAIN               FF_DEV_FLASH_ILEVEL_LOGAIN
499 #define FF_SWPARAM_ILEVEL_4dBU                 FF_DEV_FLASH_ILEVEL_4dBU
500 #define FF_SWPARAM_ILEVEL_m10dBV               FF_DEV_FLASH_ILEVEL_m10dBV
501 #define FF_SWPARAM_OLEVEL_HIGAIN               FF_DEV_FLASH_OLEVEL_HIGAIN
502 #define FF_SWPARAM_OLEVEL_4dBU                 FF_DEV_FLASH_OLEVEL_4dBU
503 #define FF_SWPARAM_OLEVEL_m10dBV               FF_DEV_FLASH_OLEVEL_m10dBV
504 #define FF_SWPARAM_MIC_PHANTOM_ON              FF_DEV_FLASH_MIC_PHANTOM_ON
505 #define FF_SWPARAM_WORD_CLOCK_1x               FF_DEV_FLASH_WORD_CLOCK_1x
506 #define FF_SWPARAM_SRATE_DDS_INACTIVE          FF_DEV_FLASH_SRATE_DDS_INACTIVE
507 //
508 // The following defines refer to fields in the software parameter record
509 // which are derived from one or more fields in device flash.
510 #define FF_SWPARAM_PHONESLEVEL_HIGAIN          0x00000001
511 #define FF_SWPARAM_PHONESLEVEL_4dBU            0x00000002
512 #define FF_SWPARAM_PHONESLEVEL_m10dBV          0x00000003
513 #define FF_SWPARAM_INPUT_OPT_B                 0x00000001
514 #define FF_SWPARAM_INPUT_OPT_A                 0x00000002
515
516 #define FF_SWPARAM_FF800_INPUT_OPT_FRONT       FF_SWPARAM_INPUT_OPT_A
517 #define FF_SWPARAM_FF800_INPUT_OPT_REAR        FF_SWPARAM_INPUT_OPT_B
518 //
519 // Flags for the *_mixerflags fields
520 #define FF_SWPARAM_MF_NORMAL    0x00
521 #define FF_SWPARAM_MF_MUTED     0x01
522 #define FF_SWPARAM_MF_INVERTED  0x02    // Inputs/playbacks only
523 #define FF_SWPARAM_MF_REC       0x04    // Outputs only
524
525 // Indices into the amp_gains array
526 #define FF400_AMPGAIN_MIC1      0
527 #define FF400_AMPGAIN_MIC2      1
528 #define FF400_AMPGAIN_INPUT3    2
529 #define FF400_AMPGAIN_INPUT4    3
530 #define FF400_AMPGAIN_OUTPUT1   4
531 #define FF400_AMPGAIN_OUTPUT2   5
532 #define FF400_AMPGAIN_OUTPUT3   6
533 #define FF400_AMPGAIN_OUTPUT4   7
534 #define FF400_AMPGAIN_OUTPUT5   8
535 #define FF400_AMPGAIN_OUTPUT6   9
536 #define FF400_AMPGAIN_PHONES_L 10
537 #define FF400_AMPGAIN_PHONES_R 11
538 #define FF400_AMPGAIN_SPDIF1   12
539 #define FF400_AMPGAIN_SPDIF2   13
540 #define FF400_AMPGAIN_ADAT1_1  14
541 #define FF400_AMPGAIN_ADAT1_2  15
542 #define FF400_AMPGAIN_ADAT1_3  16
543 #define FF400_AMPGAIN_ADAT1_4  17
544 #define FF400_AMPGAIN_ADAT1_5  18
545 #define FF400_AMPGAIN_ADAT1_6  19
546 #define FF400_AMPGAIN_ADAT1_7  20
547 #define FF400_AMPGAIN_ADAT1_8  21
548 #define FF400_AMPGAIN_NUM      22
549
550 // The general Fireface state
551 typedef struct {
552     uint32_t is_streaming;
553     uint32_t clock_mode;
554     uint32_t autosync_source;
555     uint32_t autosync_freq;
556     uint32_t spdif_freq;
557     uint32_t adat1_sync_status, adat2_sync_status;
558     uint32_t spdif_sync_status;
559     uint32_t wclk_sync_status, tco_sync_status;
560 } FF_state_t;
561
562 #define FF_STATE_CLOCKMODE_MASTER              0
563 #define FF_STATE_CLOCKMODE_AUTOSYNC            1
564 #define FF_STATE_AUTOSYNC_SRC_NOLOCK           0
565 #define FF_STATE_AUTOSYNC_SRC_ADAT1            1
566 #define FF_STATE_AUTOSYNC_SRC_ADAT2            2
567 #define FF_STATE_AUTOSYNC_SRC_SPDIF            3
568 #define FF_STATE_AUTOSYNC_SRC_WCLK             4
569 #define FF_STATE_AUTOSYNC_SRC_TCO              5
570 #define FF_STATE_SYNC_NOLOCK                   0
571 #define FF_STATE_SYNC_LOCKED                   1
572 #define FF_STATE_SYNC_SYNCED                   2
573
574 // Data structure for the TCO (Time Code Option) state
575 typedef struct {
576     uint32_t input;
577     uint32_t frame_rate;
578     uint32_t word_clock;
579     uint32_t sample_rate;
580     uint32_t pull;
581     uint32_t termination;
582     uint32_t MTC;
583 } FF_TCO_settings_t;
584
585 // Defines used to configure selected quadlets of the TCO write space.  Some
586 // of these are also used when configuring the TCO.  The byte indices
587 // referenced in the define names are 0-based.
588
589 // TCO quadlet 0
590 #define FF_TCO0_MTC                           0x80000000
591
592 // TCO quadlet 1
593 #define FF_TCO1_TCO_lock                      0x00000001
594 #define FF_TCO1_WORD_CLOCK_INPUT_RATE0        0x00000002
595 #define FF_TCO1_WORD_CLOCK_INPUT_RATE1        0x00000004
596 #define FF_TCO1_LTC_INPUT_VALID               0x00000008
597 #define FF_TCO1_WORD_CLOCK_INPUT_VALID        0x00000010
598 #define FF_TCO1_VIDEO_INPUT_NTSC              0x00000020
599 #define FF_TCO1_VIDEO_INPUT_PAL               0x00000040
600 #define FF_TCO1_SET_TC                        0x00000100
601 #define FF_TCO1_SET_DROPFRAME                 0x00000200
602 #define FF_TCO1_LTC_FORMAT0                   0x00000400
603 #define FF_TCO1_LTC_FORMAT1                   0x00000800
604
605 #define FF_TCO1_WORD_CLOCK_INPUT_1x           0
606 #define FF_TCO1_WORD_CLOCK_INPUT_2x           FF_TCO1_WORD_CLOCK_INPUT_RATE0
607 #define FF_TCO1_WORD_CLOCK_INPUT_4x           FF_TCO1_WORD_CLOCK_INPUT_RATE1
608 #define FF_TCO1_WORD_CLOCK_INPUT_MASK         (FF_TCO1_WORD_CLOCK_INPUT_RATE0|FF_TCO1_WORD_CLOCK_INPUT_RATE1)
609 #define FF_TCO1_VIDEO_INPUT_MASK              (FF_TCO1_VIDEO_INPUT_NTSC|FF_TCO1_VIDEO_INPUT_PAL)
610 #define FF_TC01_LTC_FORMAT_24fps              0
611 #define FF_TCO1_LTC_FORMAT_25fps              FF_TCO1_LTC_FORMAT0
612 #define FF_TC01_LTC_FORMAT_29_97fps           FF_TCO1_LTC_FORMAT1
613 #define FF_TCO1_LTC_FORMAT_29_97dpfs          (FF_TCO1_LTC_FORMAT1|FF_TCO1_SET_DROPFRAME)
614 #define FF_TCO1_LTC_FORMAT_30fps              (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1)
615 #define FF_TCO1_LTC_FORMAT_30dfps             (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1|FF_TCO1_SET_DROPFRAME)
616 #define FF_TCO1_LTC_FORMAT_MASK               (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1)
617
618 // TCO quadlet 2
619 #define FF_TCO2_TC_RUN                        0x00010000
620 #define FF_TCO2_WORD_CLOCK_CONV0              0x00020000
621 #define FF_TCO2_WORD_CLOCK_CONV1              0x00040000
622 #define FF_TCO2_NUM_DROPFRAMES0               0x00080000 // Unused
623 #define FF_TCO2_NUM_DROPFRAMES1               0x00100000 // Unused
624 #define FF_TCO2_SET_JAM_SYNC                  0x00200000
625 #define FF_TCO2_SET_FLYWHEEL                  0x00400000
626 #define FF_TCO2_SET_01_4                      0x01000000
627 #define FF_TCO2_SET_PULLDOWN                  0x02000000
628 #define FF_TCO2_SET_PULLUP                    0x04000000
629 #define FF_TCO2_SET_FREQ                      0x08000000
630 #define FF_TCO2_SET_TERMINATION               0x10000000
631 #define FF_TCO2_SET_INPUT0                    0x20000000
632 #define FF_TCO2_SET_INPUT1                    0x40000000
633 #define FF_TCO2_SET_FREQ_FROM_APP             0x80000000
634
635 #define FF_TCO2_WORD_CLOCK_CONV_1_1           0
636 #define FF_TCO2_WORD_CLOCK_CONV_44_48         FF_TCO2_WORD_CLOCK_CONV0
637 #define FF_TCO2_WORD_CLOCK_CONV_48_44         FF_TCO2_WORD_CLOCK_CONV1
638 #define FF_TCO2_PULL_0                        0
639 #define FF_TCO2_PULL_UP_01                    FF_TCO2_SET_PULLUP
640 #define FF_TCO2_PULL_DOWN_01                  FF_TCO2_SET_PULLDOWN
641 #define FF_TCO2_PULL_UP_40                    (FF_TCO2_SET_PULLUP|FF_TCO2_SET_01_4)
642 #define FF_TCO2_PULL_DOWN_40                  (FF_TCO2_SET_PULLDOWN|FF_TCO2_SET_01_4)
643 #define FF_TCO2_INPUT_LTC                     FF_TCO2_SET_INPUT1
644 #define FF_TCO2_INPUT_VIDEO                   FF_TCO2_SET_INPUT0
645 #define FF_TCO2_INPUT_WORD_CLOCK              0
646 #define FF_TCO2_SRATE_44_1                    0
647 #define FF_TCO2_SRATE_48                      FF_TCO2_SET_FREQ
648 #define FF_TCO2_SRATE_FROM_APP                FF_TCO2_SET_FREQ_FROM_APP
649
650 // Interpretation of the TCO software settings fields
651 #define FF_TCOPARAM_INPUT_LTC                 1
652 #define FF_TCOPARAM_INPUT_VIDEO               2
653 #define FF_TCOPARAM_INPUT_WCK                 3
654 #define FF_TCOPARAM_FRAMERATE_24fps           1
655 #define FF_TCOPARAM_FRAMERATE_25fps           2
656 #define FF_TCOPARAM_FRAMERATE_29_97fps        3
657 #define FF_TCOPARAM_FRAMERATE_29_97dfps       4
658 #define FF_TCOPARAM_FRAMERATE_30fps           5
659 #define FF_TCOPARAM_FRAMERATE_30dfps          6
660 #define FF_TCOPARAM_WORD_CLOCK_CONV_1_1       1     // 1:1
661 #define FF_TCOPARAM_WORD_CLOCK_CONV_44_48     2     // 44.1 kHz-> 48 kHz
662 #define FF_TCOPARAM_WORD_CLOCK_CONV_48_44     3     // 48 kHz -> 44.1 kHz
663 #define FF_TCOPARAM_SRATE_44_1                1     // Rate is 44.1 kHz
664 #define FF_TCOPARAM_SRATE_48                  2     // Rate is 48 kHz
665 #define FF_TCOPARAM_SRATE_FROM_APP            3
666 #define FF_TCPPARAM_PULL_NONE                 1
667 #define FF_TCOPARAM_PULL_UP_01                2     // +0.1%
668 #define FF_TCOPARAM_PULL_DOWN_01              3     // -0.1%
669 #define FF_TCOPARAM_PULL_UP_40                4     // +4.0%
670 #define FF_TCOPARAM_PULL_DOWN_40              5     // -4.0%
671 #define FF_TCOPARAM_TERMINATION_ON            1
672
673 // The state of the TCO
674 typedef struct {
675   unsigned int locked, ltc_valid;
676   unsigned int hours, minutes, seconds, frames;
677   unsigned int frame_rate;
678   unsigned int drop_frame;
679   unsigned int video_input;
680   unsigned int word_clock_state;
681   float sample_rate;
682 } FF_TCO_state_t;
683
684 // TCO state field defines
685 #define FF_TCOSTATE_FRAMERATE_24fps           1
686 #define FF_TCOSTATE_FRAMERATE_25fps           2
687 #define FF_TCOSTATE_FRAMERATE_29_97fps        3
688 #define FF_TCOSTATE_FRAMERATE_30fps           4
689 #define FF_TCOSTATE_VIDEO_NONE                0
690 #define FF_TCOSTATE_VIDEO_PAL                 1
691 #define FF_TCOSTATE_VIDEO_NTSC                2
692 #define FF_TCOSTATE_WORDCLOCK_NONE            0
693 #define FF_TCOSTATE_WORDCLOCK_1x              1
694 #define FF_TCOSTATE_WORDCLOCK_2x              2
695 #define FF_TCOSTATE_WORDCLOCK_4x              3
696
697 #endif
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