root/trunk/libffado/src/rme/fireface_def.h

Revision 2803, 32.9 kB (checked in by jwoithe, 3 years ago)

Cosmetic: capitalise "L" in "Linux".

"Linux" is a proper noun so it should start with a capital letter. These
changes are almost all within comments.

This patch was originally proposed by pander on the ffado-devel mailing
list. It has been expanded to cover all similar cases to maintain
consistency throughout the source tree.

Line 
1 /*
2  * Copyright (C) 2009 by Jonathan Woithe
3  *
4  * This file is part of FFADO
5  * FFADO = Free FireWire (pro-)audio drivers for Linux
6  *
7  * FFADO is based upon FreeBoB.
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation, either version 2 of the License, or
12  * (at your option) version 3 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23
24 /* This file contains definitions relating to the RME Fireface interfaces
25  * (Fireface 400 and Fireface 800).  Naming convention:
26  *   RME_FF_     identifier applies to both FF400 and FF800
27  *   RME_FF400_  identifier specific to the FF400
28  *   RME_FF800_  identifier specific to the FF800
29  */
30
31 #ifndef _FIREFACE_DEF
32 #define _FIREFACE_DEF
33
34 /* The maximum number of channels supported by each device */
35 #define RME_FF400_MAX_CHANNELS  18
36 #define RME_FF800_MAX_CHANNELS  28
37
38 /* Boundaries between the speed multipliers */
39 #define MIN_SPEED               30000
40 #define MIN_DOUBLE_SPEED        56000
41 #define MIN_QUAD_SPEED          112000
42 #define MAX_SPEED               210000
43
44 // A flag used to indicate the use of a 800 Mbps bus speed to various
45 // streaming registers of the FF800.
46 #define RME_FF800_STREAMING_SPEED_800 0x800
47
48 /* The Command Buffer Address (CBA) is different for the two interfaces */
49 #define RME_FF400_CMD_BUFFER    0x80100500
50 #define RME_FF800_CMD_BUFFER    0xfc88f000
51
52 // Offsets for registers at fixed offsets from the device's command buffer
53 // address
54 #define RME_FF_DDS_SRATE_OFS      (0*4)
55 #define RME_FF_CONF1_OFS          (5*4)
56 #define RME_FF_CONF2_OFS          (6*4)
57 #define RME_FF_CONF3_OFS          (7*4)
58 #define RME_FF400_FLASH_CMD_OFS   (8*4)       // Write only
59 #define RME_FF400_FLASH_STAT_OFS  (8*4)       // Read only
60
61 /* General register definitions */
62 #define RME_FF400_CONF_REG          (RME_FF400_CMD_BUFFER + RME_FF_CONF1_OFS)
63 #define RME_FF800_CONF_REG          (RME_FF800_CMD_BUFFER + RME_FF_CONF1_OFS)
64
65 #define RME_FF400_STREAM_INIT_REG   (RME_FF400_CMD_BUFFER)  // 5 quadlets wide
66 #define RME_FF400_STREAM_INIT_SIZE  5                       // Size in quadlets
67 #define RME_FF400_STREAM_SRATE      (RME_FF400_CMD_BUFFER)
68 #define RME_FF400_STREAM_CONF0      (RME_FF400_CMD_BUFFER+4)
69 #define RME_FF400_STREAM_CONF1      (RME_FF400_CMD_BUFFER+8)
70 #define RME_FF800_STREAM_INIT_REG   0x20000001cLL           // 3 quadlets wide
71 #define RME_FF800_STREAM_INIT_SIZE  3                       // Size in quadlets
72 #define RME_FF800_STREAM_SRATE      0x20000001cLL
73 #define RME_FF800_STREAM_CONF0      (0x20000001cLL+4)
74 #define RME_FF800_STREAM_CONF1      (0x20000001cLL+8)
75 #define RME_FF400_STREAM_START_REG  (RME_FF400_CMD_BUFFER + 0x000c)  // 1 quadlet
76 #define RME_FF800_STREAM_START_REG  0x200000028LL                    // 1 quadlet
77 #define RME_FF400_STREAM_END_REG    (RME_FF400_CMD_BUFFER + 0x0004)  // 4 quadlets wide
78 #define RME_FF400_STREAM_END_SIZE   4              // Size in quadlets
79 #define RME_FF800_STREAM_END_REG    0x200000034LL  // 3 quadlets wide
80 #define RME_FF800_STREAM_END_SIZE   3              // Size in quadlets
81
82 #define RME_FF800_HOST_LED_REG      0x200000324LL
83
84 #define RME_FF800_REVISION_REG      0x200000100LL
85
86 #define RME_FF_CHANNEL_MUTE_MASK     0x801c0000    // Write only
87 #define RME_FF_STATUS_REG0           0x801c0000    // Read only
88 #define RME_FF_STATUS_REG1           0x801c0004    // Read only
89 #define RME_FF_STATUS_REG2           0x801c0008
90 #define RME_FF_STATUS_REG3           0x801c001c
91 #define RME_FF_OUTPUT_REC_MASK       0x801c0080    // Write only
92
93 #define RME_FF_MIXER_RAM             0x80080000
94
95 #define RME_FF_TCO_READ_REG          0x801f0000    // FF800 only
96 #define RME_FF_TCO_WRITE_REG         0x801f0020    // FF800 only
97
98 #define RME_FF400_GAIN_REG           0x801c0180
99
100 #define RME_FF400_MIDI_HIGH_ADDR     0x801003f4
101
102 /* Types of controls in the matrix mixer */
103 #define RME_FF_MM_INPUT              0x0000
104 #define RME_FF_MM_PLAYBACK           0x0001
105 #define RME_FF_MM_OUTPUT             0x0002
106
107 /* Addresses of various blocks in memory-mapped flash */
108 #define RME_FF400_FLASH_SETTINGS_ADDR       0x00060000
109 #define RME_FF400_FLASH_MIXER_VOLUME_ADDR   0x00070000
110 #define RME_FF400_FLASH_MIXER_PAN_ADDR      0x00070800
111 #define RME_FF400_FLASH_MIXER_HW_ADDR       0x00071000  /* Hardware volume settings, MIDI enable, submix */
112 #define RME_FF800_FLASH_MIXER_SHADOW_ADDR  0x3000e0000LL
113 #define RME_FF800_FLASH_MIXER_SHADOW_SIZE   0x00002000
114 #define RME_FF800_FLASH_MIXER_VOLUME_ADDR  0x3000e2000LL
115 #define RME_FF800_FLASH_MIXER_PAN_ADDR     0x3000e2800LL
116 #define RME_FF800_FLASH_MIXER_HW_ADDR      0x3000e3000LL  /* H/w volume settings, MIDI enable, submix */
117 #define RME_FF800_FLASH_SETTINGS_ADDR      0x3000f0000LL
118 #define RME_FF_FLASH_MIXER_ARRAY_SIZE       0x00000800    // In bytes
119
120 /* Flash control registers */
121 #define RME_FF400_FLASH_BLOCK_ADDR_REG      0x80100288
122 #define RME_FF400_FLASH_BLOCK_SIZE_REG      0x8010028c
123 #define RME_FF400_FLASH_CMD_REG             (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_CMD_OFS)
124 #define RME_FF400_FLASH_STAT_REG            (RME_FF400_CMD_BUFFER + RME_FF400_FLASH_STAT_OFS)
125 #define RME_FF400_FLASH_WRITE_BUFFER        0x80100290
126 #define RME_FF400_FLASH_READ_BUFFER         0x80100290
127
128 /* Flash erase control registers on the FF800 */
129 #define RME_FF800_FLASH_ERASE_VOLUME_REG    0x3fffffff4LL
130 #define RME_FF800_FLASH_ERASE_SETTINGS_REG  0x3fffffff0LL
131 #define RME_FF800_FLASH_ERASE_FIRMWARE_REG  0x3fffffff8LL
132 #define RME_FF800_FLASH_ERASE_CONFIG_REG    0x3fffffffcLL
133
134 /* Flash erase command values for the FF400 */
135 #define RME_FF400_FLASH_CMD_WRITE           0x00000001
136 #define RME_FF400_FLASH_CMD_READ            0x00000002
137 #define RME_FF400_FLASH_CMD_ERASE_VOLUME    0x0000000e
138 #define RME_FF400_FLASH_CMD_ERASE_SETTINGS  0x0000000d
139 #define RME_FF400_FLASH_CMD_ERASE_CONFIG    0x0000000c
140 #define RME_FF400_FLASH_CMD_GET_REVISION    0x0000000f
141
142 /* Flags for use with erase_flash() */
143 #define RME_FF_FLASH_ERASE_VOLUME           1
144 #define RME_FF_FLASH_ERASE_SETTINGS         2
145 #define RME_FF_FLASH_ERASE_CONFIG           3
146
147 #define RME_FF_FLASH_SECTOR_SIZE            256   // In bytes
148 #define RME_FF_FLASH_SECTOR_SIZE_QUADS      (RME_FF_FLASH_SECTOR_SIZE/4)
149 #define RME_FF_FLASH_0DB_VOL_VALUE          0x323
150
151 /* Defines for components of the control registers */
152 // Configuration register 0
153 #define CR0_PHANTOM_MIC0        0x00000001
154
155 #define CR0_PHANTOM_MIC2        0x00000002
156 #define CR0_FILTER_FPGA         0x00000004
157 #define CR0_BIT01               0x00000002  // Use depends on model - see below
158 #define CR0_BIT02               0x00000004  // Use depends on model - see below
159 #define CR0_ILEVEL_FPGA_CTRL0   0x00000008
160 #define CR0_ILEVEL_FPGA_CTRL1   0x00000010
161 #define CR0_ILEVEL_FPGA_CTRL2   0x00000020
162 #define CR0_ZEROBIT06           0x00000040
163 #define CR0_PHANTOM_MIC1        0x00000080
164 #define CR0_BIT08               0x00000100  // Use depends on model - see below
165 #define CR0_BIT09               0x00000200  // Use depends on model - see below
166 #define CRO_OLEVEL_FPGA_CTRL_0  0x00000400
167 #define CRO_OLEVEL_FPGA_CTRL_1  0x00000800
168 #define CRO_OLEVEL_FPGA_CTRL_2  0x00001000
169 #define CR0_ZEROBIT13           0x00002000
170 #define CRO_ZEROBIT14           0x00004000
171 #define CRO_ZEROBIT15           0x00008000
172 #define CRO_PHLEVEL_CTRL0       0x00010000
173 #define CRO_PHLEVEL_CTRL1       0x00020000
174
175 #define CR0_FF400_PHANTOM_MIC0  CR0_PHANTOM_MIC0
176 #define CR0_FF400_PHANTOM_MIC1  CR0_PHANTOM_MIC1
177 #define CR0_FF400_CH3_PAD       CR0_BIT08
178 #define CR0_FF400_CH3_INSTR     CR0_BIT09
179 #define CR0_FF400_CH4_PAD       CR0_BIT01
180 #define CR0_FF400_CH4_INSTR     CR0_BIT02
181 #define CR0_FF800_PHANTOM_MIC7  CR0_PHANTOM_MIC0
182 #define CR0_FF800_PHANTOM_MIC8  CR0_PHANTOM_MIC1
183 #define CR0_FF800_PHANTOM_MIC9  CR0_BIT01
184 #define CR0_FF800_PHANTOM_MIC10 CR0_BIT08
185 #define CR0_FF800_FILTER_FPGA   CR0_BIT02
186 #define CR0_FF800_DRIVE_FPGA    CR0_BIT09
187 #define CR0_ILEVEL_FPGA_LOGAIN  CR0_ILEVEL_FPGA_CTRL0
188 #define CR0_ILEVEL_FPGA_4dBU    CR0_ILEVEL_FPGA_CTRL1
189 #define CR0_ILEVEL_FPGA_m10dBV  CR0_ILEVEL_FPGA_CTRL2
190 #define CR0_OLEVEL_FPGA_HIGAIN  CRO_OLEVEL_FPGA_CTRL_0
191 #define CR0_OLEVEL_FPGA_4dBU    CRO_OLEVEL_FPGA_CTRL_1
192 #define CR0_OLEVEL_FPGA_m10dBV  CRO_OLEVEL_FPGA_CTRL_2
193 #define CR0_PHLEVEL_4dBU        0
194 #define CRO_PHLEVEL_m10dBV      CRO_PHLEVEL_CTRL0
195 #define CRO_PHLEVEL_HIGAIN      CRO_PHLEVEL_CTRL1
196
197 // Configuration register 1
198 #define CR1_ILEVEL_CPLD_CTRL0   0x00000001
199 #define CR1_ILEVEL_CPLD_CTRL1   0x00000002
200 #define CR1_INPUT_OPT0_B        0x00000004    // Input optionset 0, option B
201 #define CR1_OLEVEL_CPLD_CTRL0   0x00000008
202 #define CR1_OLEVEL_CPLD_CTRL1   0x00000010
203 #define CR1_INPUT_OPT1_A        0x00000020    // Input optionset 1, option A
204 #define CR1_INPUT_OPT1_B        0x00000040    // Input optionset 1, option B
205 #define CR1_INPUT_OPT2_A        0x00000080    // Input optionset 2, option A
206 #define CR1_INPUT_OPT2_B        0x00000100    // Input optionset 2, option B
207 #define CR1_INSTR_DRIVE         0x00000200
208 #define CR1_INPUT_OPT0_A1       0x00000400    // Input optionset 0, option A bit 1
209 #define CR1_INPUT_OPT0_A0       0x00000800    // Input optionset 0, option A bit 0
210
211 #define CR1_ILEVEL_CPLD_LOGAIN  0
212 #define CR1_ILEVEL_CPLD_4dBU    CR1_ILEVEL_CPLD_CTRL1
213 #define CR1_ILEVEL_CPLD_m10dBV  (CR1_ILEVEL_CPLD_CTRL0 | CR1_ILEVEL_CPLD_CTRL1)
214 #define CR1_OLEVEL_CPLD_m10dBV  CR1_OLEVEL_CPLD_CTRL0
215 #define CR1_OLEVEL_CPLD_HIGAIN  CR1_OLEVEL_CPLD_CTRL1
216 #define CR1_OLEVEL_CPLD_4dBU    (CR1_OLEVEL_CPLD_CTRL0 | CR1_OLEVEL_CPLD_CTRL1)
217 #define CR1_FF800_INPUT7_FRONT  CR1_INPUT_OPT1_A
218 #define CR1_FF800_INPUT7_REAR   CR1_INPUT_OPT1_B
219 #define CR1_FF800_INPUT8_FRONT  CR1_INPUT_OPT2_A
220 #define CR1_FF800_INPUT8_REAR   CR1_INPUT_OPT2_B
221 #define CR1_FF400_INPUT3_INSTR  CR1_INPUT_OPT1_B   // To be confirmed
222 #define CR1_FF400_INPUT3_PAD    CR1_INPUT_OPT1_A   // To be confirmed
223 #define CR1_FF400_INPUT4_INSTR  CR1_INPUT_OPT2_B   // To be confirmed
224 #define CR1_FF400_INPUT4_PAD    CR1_INPUT_OPT2_A   // To be confirmed
225
226 // The input 1 "front" option is strange on the FF800 in that it is
227 // indicated using two bits.  The actual bit set depends, curiously enough,
228 // on the "speaker emulation" (aka "filter") setting.  How odd.
229 #define CR1_FF800_INPUT1_FRONT              CR1_INPUT_OPT0_A0
230 #define CR1_FF800_INPUT1_FRONT_WITH_FILTER  CR1_INPUT_OPT0_A1
231 #define CR1_FF800_INPUT1_REAR               CR1_INPUT_OPT0_B
232
233 // Configuration register 2
234 #define CR2_CLOCKMODE_AUTOSYNC  0x00000000
235 #define CR2_CLOCKMODE_MASTER    0x00000001
236 #define CR2_FREQ0               0x00000002
237 #define CR2_FREQ1               0x00000004
238 #define CR2_DSPEED              0x00000008
239 #define CR2_QSSPEED             0x00000010
240 #define CR2_SPDIF_OUT_PRO       0x00000020
241 #define CR2_SPDIF_OUT_EMP       0x00000040
242 #define CR2_SPDIF_OUT_NONAUDIO  0x00000080
243 #define CR2_SPDIF_OUT_ADAT2     0x00000100  // Optical SPDIF on ADAT2 port
244 #define CR2_SPDIF_IN_COAX       0x00000000
245 #define CR2_SPDIF_IN_ADAT2      0x00000200  // Optical SPDIF on ADAT2 port
246 #define CR2_SYNC_REF0           0x00000400
247 #define CR2_SYNC_REF1           0x00000800
248 #define CR2_SYNC_REF2           0x00001000
249 #define CR2_WORD_CLOCK_1x       0x00002000
250 #define CR2_TOGGLE_TCO          0x00004000  // Normally set to 0
251 #define CR2_P12DB_AN0           0x00010000  // Disable soft-limiter.  Normally set to 0
252 #define CR2_FF400_DISABLE_MIDI_TX_MASK  0x03000000  // Either or all bits will disable
253 #define CR2_FF400_SELECT_MIDI_TX_ADDR_1 0x04000000  // FF400 tx to 0x'....'....'0000'0000'0000'0000
254 #define CR2_FF400_SELECT_MIDI_TX_ADDR_2 0x08000000  // FF400 tx to 0x'....'....'0000'0000'0000'0080
255 #define CR2_FF400_SELECT_MIDI_TX_ADDR_3 0x10000000  // FF400 tx to 0x'....'....'0000'0000'0000'0100
256 #define CR2_FF400_SELECT_MIDI_TX_ADDR_4 0x20000000  // FF400 tx to 0x'....'....'0000'0000'0000'0180
257                                                     // '....'....' = content of RME_FF400_MIDI_HIGH_ADDR
258 #define CR2_TMS                 0x40000000  // Unit option, normally 0
259 #define CR2_DROP_AND_STOP       0x80000000  // Normally set to 1
260
261 #define CR2_SYNC_ADAT1          0x0
262 #define CR2_SYNC_ADAT2          (CR2_SYNC_REF0)
263 #define CR2_SYNC_SPDIF          (CR2_SYNC_REF0 | CR2_SYNC_REF1)
264 #define CR2_SYNC_WORDCLOCK      (CR2_SYNC_REF2)
265 #define CR2_SYNC_TCO            (CR2_SYNC_REF0 | CR2_SYNC_REF2)
266 #define CR2_DISABLE_LIMITER     CR2_P12DB_AN0
267
268 /* Defines for the status registers */
269 // Status register 0
270 #define SR0_ADAT1_LOCK          0x00000400
271 #define SR0_ADAT2_LOCK          0x00000800
272 #define SR0_ADAT1_SYNC          0x00001000
273 #define SR0_ADAT2_SYNC          0x00002000
274 #define SR0_SPDIF_F0            0x00004000
275 #define SR0_SPDIF_F1            0x00008000
276 #define SR0_SPDIF_F2            0x00010000
277 #define SR0_SPDIF_F3            0x00020000
278 #define SR0_SPDIF_SYNC          0x00040000
279 #define SR0_OVER                0x00080000
280 #define SR0_SPDIF_LOCK          0x00100000
281 #define SR0_SEL_SYNC_REF0       0x00400000
282 #define SR0_SEL_SYNC_REF1       0x00800000
283 #define SR0_SEL_SYNC_REF2       0x01000000
284 #define SR0_INP_FREQ0           0x02000000
285 #define SR0_INP_FREQ1           0x04000000
286 #define SR0_INP_FREQ2           0x08000000
287 #define SR0_INP_FREQ3           0x10000000
288 #define SR0_WCLK_SYNC           0x20000000
289 #define SR0_WCLK_LOCK           0x40000000
290
291 // The lowest 10 bits of SR0 represent sample_rate/250 if locked to an
292 // external clock source.
293 #define SR0_STREAMING_FREQ_MASK 0x000003ff
294
295 #define SR0_ADAT1_STATUS_MASK   (SR0_ADAT1_LOCK|SR0_ADAT1_SYNC)
296 #define SR0_ADAT1_STATUS_NOLOCK 0
297 #define SR0_ADAT1_STATUS_LOCK   SR0_ADAT1_LOCK
298 #define SR0_ADAT1_STATUS_SYNC   (SR0_ADAT1_LOCK|SR0_ADAT1_SYNC)
299 #define SR0_ADAT2_STATUS_MASK   (SR0_ADAT2_LOCK|SR0_ADAT2_SYNC)
300 #define SR0_ADAT2_STATUS_NOLOCK 0
301 #define SR0_ADAT2_STATUS_LOCK   SR0_ADAT2_LOCK
302 #define SR0_ADAT2_STATUS_SYNC   (SR0_ADAT2_LOCK|SR0_ADAT2_SYNC)
303 #define SR0_SPDIF_STATUS_MASK   (SR0_SPDIF_LOCK|SR0_SPDIF_SYNC)
304 #define SR0_SPDIF_STATUS_NOLOCK 0
305 #define SR0_SPDIF_STATUS_LOCK   SR0_SPDIF_LOCK
306 #define SR0_SPDIF_STATUS_SYNC   (SR0_SPDIF_LOCK|SR0_SPDIF_SYNC)
307 #define SR0_WCLK_STATUS_MASK    (SR0_WCLK_LOCK|SR0_WCLK_SYNC)
308 #define SR0_WCLK_STATUS_NOLOCK  0
309 #define SR0_WCLK_STATUS_LOCK    SR0_WCLK_LOCK
310 #define SR0_WCLK_STATUS_SYNC    (SR0_WCLK_LOCK|SR0_WCLK_SYNC)
311
312 #define SR0_SPDIF_FREQ_MASK     (SR0_SPDIF_F0|SR0_SPDIF_F1|SR0_SPDIF_F2|SR0_SPDIF_F3)
313 #define SR0_SPDIF_FREQ_32k      SR0_SPDIF_F0
314 #define SR0_SPDIF_FREQ_44k1     SR0_SPDIF_F1
315 #define SR0_SPDIF_FREQ_48k      (SR0_SPDIF_F0|SR0_SPDIF_F1)
316 #define SR0_SPDIF_FREQ_64k      SR0_SPDIF_F2
317 #define SR0_SPDIF_FREQ_88k2     (SR0_SPDIF_F0|SR0_SPDIF_F2)
318 #define SR0_SPDIF_FREQ_96k      (SR0_SPDIF_F1|SR0_SPDIF_F2)
319 #define SR0_SPDIF_FREQ_128k     (SR0_SPDIF_F0|SR0_SPDIF_F1|SR0_SPDIF_F2)
320 #define SR0_SPDIF_FREQ_176k4    SR0_SPDIF_F3
321 #define SR0_SPDIF_FREQ_192k     (SR0_SPDIF_F0|SR0_SPDIF_F3)
322
323 #define SR0_AUTOSYNC_SRC_MASK   (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF1|SR0_SEL_SYNC_REF2)
324 #define SR0_AUTOSYNC_SRC_ADAT1  0
325 #define SR0_AUTOSYNC_SRC_ADAT2  SR0_SEL_SYNC_REF0
326 #define SR0_AUTOSYNC_SRC_SPDIF  (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF1)
327 #define SR0_AUTOSYNC_SRC_WCLK   SR0_SEL_SYNC_REF2
328 #define SR0_AUTOSYNC_SRC_TCO    (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF2)
329 #define SR0_AUTOSYNC_SRC_NONE   (SR0_SEL_SYNC_REF1|SR0_SEL_SYNC_REF2)
330
331 #define SR0_AUTOSYNC_FREQ_MASK  (SR0_INP_FREQ0|SR0_INP_FREQ1|SR0_INP_FREQ2|SR0_INP_FREQ3)
332 #define SR0_AUTOSYNC_FREQ_32k   SR0_INP_FREQ0
333 #define SR0_AUTOSYNC_FREQ_44k1  SR0_INP_FREQ1
334 #define SR0_AUTOSYNC_FREQ_48k   (SR0_INP_FREQ0|SR0_INP_FREQ1)
335 #define SR0_AUTOSYNC_FREQ_64k   SR0_INP_FREQ2
336 #define SR0_AUTOSYNC_FREQ_88k2  (SR0_INP_FREQ0|SR0_INP_FREQ2)
337 #define SR0_AUTOSYNC_FREQ_96k   (SR0_INP_FREQ1|SR0_INP_FREQ2)
338 #define SR0_AUTOSYNC_FREQ_128k  (SR0_INP_FREQ0|SR0_INP_FREQ1|SR0_INP_FREQ2)
339 #define SR0_AUTOSYNC_FREQ_176k4 SR0_INP_FREQ3
340 #define SR0_AUTOSYNC_FREQ_192k  (SR0_INP_FREQ0|SR0_INP_FREQ3)
341 #define SR0_AUTOSYNC_FREQ_NONE  0
342
343 // Status register 1
344 #define SR1_CLOCK_MODE_MASTER   0x00000001
345 #define SR1_TCO_SYNC            0x00400000
346 #define SR1_TCO_LOCK            0x00800000
347
348 #define SR1_TCO_STATUS_MASK    (SR1_TCO_LOCK|SR1_TCO_SYNC)
349 #define SR1_TCO_STATUS_NOLOCK  0
350 #define SR1_TCO_STATUS_LOCK    SR1_TCO_LOCK
351 #define SR1_TCO_STATUS_SYNC    (SR1_TCO_LOCK|SR1_TCO_SYNC)
352
353 /* Structure used to store device settings in the device flash RAM.  This
354  * structure mirrors the layout in the Fireface's flash, so it cannot be
355  * altered.  Fields named as unused_* are not utilised at present.
356  */
357 typedef struct {
358     uint32_t unused_device_id;
359     uint32_t unused_device_rev;
360     uint32_t unused_asio_latency;
361     uint32_t unused_samples_per_frame;
362     uint32_t spdif_input_mode;
363     uint32_t spdif_output_emphasis;
364     uint32_t spdif_output_pro;
365     uint32_t clock_mode;
366     uint32_t spdif_output_nonaudio;
367     uint32_t sync_ref;
368     uint32_t spdif_output_mode;
369     uint32_t unused_check_input;
370     uint32_t unused_status;
371     uint32_t unused_register[4];
372     uint32_t unused_iso_rx_channel;
373     uint32_t unused_iso_tx_channel;
374     uint32_t unused_timecode;
375     uint32_t unused_device_type;
376     uint32_t unused_number_of_devices;
377     uint32_t tms;
378     uint32_t unused_speed;
379     uint32_t unused_channels_avail_hi;
380     uint32_t unused_channels_avail_lo;
381     uint32_t limit_bandwidth;
382     uint32_t unused_bandwidth_allocated;
383     uint32_t stop_on_dropout;
384     uint32_t input_level;
385     uint32_t output_level;
386     uint32_t mic_plug_select[2];     // Front/rear select for FF800 ch 7/8
387                                      // [0] = phones level on FF400
388     uint32_t mic_phantom[4];
389     uint32_t instrument_plug_select; // Front/rear select for FF800 ch 1
390     uint32_t filter;
391     uint32_t fuzz;
392     uint32_t unused_sync_align;
393     uint32_t unused_device_index;
394     uint32_t unused_advanced_dialog;
395     uint32_t sample_rate;
396     uint32_t unused_interleaved;
397     uint32_t unused_sn;
398     uint32_t word_clock_single_speed;
399     uint32_t unused_num_channels;
400     uint32_t unused_dropped_samples;
401     uint32_t p12db_an[10];
402 } FF_device_flash_settings_t;
403
404 // Defines used to interpret device flash settings.  The driver can read
405 // these and use them to infer the appropriate values for the configuration
406 // registers.  The flash settings are also used directly by the device
407 // at power up to define its initial state.  Therefore it's important that
408 // these settings correspond to the values expected by the device.
409 #define FF_DEV_FLASH_INVALID                   0xffffffff
410 #define FF_DEV_FLASH_SPDIF_INPUT_COAX          0x00000001
411 #define FF_DEV_FLASH_SPDIF_INPUT_OPTICAL       0x00000000
412 #define FF_DEV_FLASH_SPDIF_OUTPUT_COAX         0x00000000
413 #define FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL      0x00000001
414 #define FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON  0x00000001
415 #define FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON       0x00000001
416 #define FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON  0x00000001
417 #define FF_DEV_FLASH_BWLIMIT_SEND_ALL_CHANNELS 0x00000000
418 #define FF_DEV_FLASH_BWLIMIT_NO_ADAT2          0x00000001  // FF800 only
419 #define FF_DEV_FLASH_BWLIMIT_ANALOG_SPDIF_ONLY 0x00000002
420 #define FF_DEV_FLASH_BWLIMIT_ANALOG_ONLY       0x00000003
421 #define FF_DEV_FLASH_CLOCK_MODE_MASTER         0x00000000
422 #define FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC       0x00000001
423 #define FF_DEV_FLASH_CLOCK_MODE_SLAVE          0x00000001
424 #define FF_DEV_FLASH_SYNCREF_WORDCLOCK         0x00000003
425 #define FF_DEV_FLASH_SYNCREF_ADAT1             0x00000000
426 #define FF_DEV_FLASH_SYNCREF_ADAT2             0x00000001
427 #define FF_DEV_FLASH_SYNCREF_SPDIF             0x00000002
428 #define FF_DEV_FLASH_SYNCREC_TCO               0x00000004  // To be confirmed
429 #define FF_DEV_FLASH_ILEVEL_LOGAIN             0x00000000
430 #define FF_DEV_FLASH_ILEVEL_4dBU               0x00000002
431 #define FF_DEV_FLASH_ILEVEL_m10dBV             0x00000001
432 #define FF_DEV_FLASH_OLEVEL_HIGAIN             0x00000002
433 #define FF_DEV_FLASH_OLEVEL_4dBU               0x00000001
434 #define FF_DEV_FLASH_OLEVEL_m10dBV             0x00000000
435 #define FF_DEV_FLASH_MIC_PHANTOM_ON            0x00000001
436 #define FF_DEV_FLASH_SRATE_DDS_INACTIVE        0x00000000
437 #define FF_DEV_FLASH_WORD_CLOCK_1x             0x00000001
438 #define FF_DEV_FLASH_PLUG_SELECT_FRONT_REAR    0x00000002
439 #define FF_DEV_FLASH_PLUG_SELECT_FRONT         0x00000001
440 #define FF_DEV_FLASH_PLUG_SELECT_REAR          0x00000000
441
442 #define FF_MATRIXMIXER_SIZE (RME_FF800_MAX_CHANNELS*RME_FF800_MAX_CHANNELS)
443
444 // Structure used by FFADO to keep track of the device status.  This is
445 // decoupled from any structures used directly by the device, so it can be
446 // added to and ordered freely.  When making changes to the device the
447 // configuration registers must be all written to, so any function changing
448 // a parameter must have access to the complete device status.
449 typedef struct {
450     uint32_t mic_phantom[4];
451     uint32_t spdif_input_mode;
452     uint32_t spdif_output_emphasis;
453     uint32_t spdif_output_pro;
454     uint32_t spdif_output_nonaudio;
455     uint32_t spdif_output_mode;
456     uint32_t clock_mode;
457     uint32_t sync_ref;
458     uint32_t tms;
459     uint32_t limit_bandwidth;
460     uint32_t stop_on_dropout;
461     uint32_t input_level;
462     uint32_t output_level;
463     uint32_t filter;
464     uint32_t fuzz;
465     uint32_t limiter;
466     uint32_t sample_rate;
467     uint32_t word_clock_single_speed;
468     uint32_t ff400_input_pad[2];       // Channels 3/4, FF400 only
469     uint32_t ff400_instr_input[2];     // Channels 3/4, FF400 only
470     uint32_t phones_level;             // Derived from fields in device flash
471     uint32_t input_opt[3];             // Derived from fields in device flash
472
473     // Other "settings" fields which are not necessarily stored in device flash
474     int32_t amp_gains[22];             // FF400: gains of input/output amps
475     int32_t input_faders[FF_MATRIXMIXER_SIZE];
476     int32_t playback_faders[FF_MATRIXMIXER_SIZE];
477     int32_t output_faders[RME_FF800_MAX_CHANNELS];
478     unsigned char input_mixerflags[FF_MATRIXMIXER_SIZE];
479     unsigned char playback_mixerflags[FF_MATRIXMIXER_SIZE];
480     unsigned char output_mixerflags[FF_MATRIXMIXER_SIZE];
481 } FF_software_settings_t;
482
483 // Defines used to interpret the software settings structure.  For now we
484 // use the same values as used by the device flash settings to remove the
485 // need for translation between reading the flash and copying it to the
486 // software settings structure, but in principle different values could be
487 // used given translation code.
488 #define FF_SWPARAM_INVALID                     FF_DEV_FLASH_INVALID
489 #define FF_SWPARAM_SPDIF_INPUT_COAX            FF_DEV_FLASH_SPDIF_INPUT_COAX
490 #define FF_SWPARAM_SPDIF_INPUT_OPTICAL         FF_DEV_FLASH_SPDIF_INPUT_OPTICAL
491 #define FF_SWPARAM_SPDIF_OUTPUT_COAX           FF_DEV_FLASH_SPDIF_OUTPUT_COAX
492 #define FF_SWPARAM_SPDIF_OUTPUT_OPTICAL        FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL
493 #define FF_SWPARAM_SPDIF_OUTPUT_EMPHASIS_ON    FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON
494 #define FF_SWPARAM_SPDIF_OUTPUT_PRO_ON         FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON
495 #define FF_SWPARAM_SPDIF_OUTPUT_NONAUDIO_ON    FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON
496 #define FF_SWPARAM_BWLIMIT_SEND_ALL_CHANNELS   FF_DEV_FLASH_BWLIMIT_SEND_ALL_CHANNELS
497 #define FF_SWPARAM_BWLIMIT_NO_ADAT2            FF_DEV_FLASH_BWLIMIT_NO_ADAT2
498 #define FF_SWPARAM_BWLIMIT_ANALOG_SPDIF_ONLY   FF_DEV_FLASH_BWLIMIT_ANALOG_SPDIF_ONLY
499 #define FF_SWPARAM_BWLIMIT_ANALOG_ONLY         FF_DEV_FLASH_BWLIMIT_ANALOG_ONLY
500 #define FF_SWPARAM_CLOCK_MODE_MASTER           FF_DEV_FLASH_CLOCK_MODE_MASTER
501 #define FF_SWPARAM_CLOCK_MODE_AUTOSYNC         FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC
502 #define FF_SWPARAM_CLOCK_MODE_SLAVE            FF_DEV_FLASH_CLOCK_MODE_SLAVE
503 #define FF_SWPARAM_SYNCREF_WORDCLOCK           FF_DEV_FLASH_SYNCREF_WORDCLOCK
504 #define FF_SWPARAM_SYNCREF_ADAT1               FF_DEV_FLASH_SYNCREF_ADAT1
505 #define FF_SWPARAM_SYNCREF_ADAT2               FF_DEV_FLASH_SYNCREF_ADAT2
506 #define FF_SWPARAM_SYNCREF_SPDIF               FF_DEV_FLASH_SYNCREF_SPDIF
507 #define FF_SWPARAM_SYNCREC_TCO                 FF_DEV_FLASH_SYNCREC_TCO
508 #define FF_SWPARAM_ILEVEL_LOGAIN               FF_DEV_FLASH_ILEVEL_LOGAIN
509 #define FF_SWPARAM_ILEVEL_4dBU                 FF_DEV_FLASH_ILEVEL_4dBU
510 #define FF_SWPARAM_ILEVEL_m10dBV               FF_DEV_FLASH_ILEVEL_m10dBV
511 #define FF_SWPARAM_OLEVEL_HIGAIN               FF_DEV_FLASH_OLEVEL_HIGAIN
512 #define FF_SWPARAM_OLEVEL_4dBU                 FF_DEV_FLASH_OLEVEL_4dBU
513 #define FF_SWPARAM_OLEVEL_m10dBV               FF_DEV_FLASH_OLEVEL_m10dBV
514 #define FF_SWPARAM_MIC_PHANTOM_ON              FF_DEV_FLASH_MIC_PHANTOM_ON
515 #define FF_SWPARAM_WORD_CLOCK_1x               FF_DEV_FLASH_WORD_CLOCK_1x
516 #define FF_SWPARAM_SRATE_DDS_INACTIVE          FF_DEV_FLASH_SRATE_DDS_INACTIVE
517 //
518 // The following defines refer to fields in the software parameter record
519 // which are derived from one or more fields in device flash.
520 #define FF_SWPARAM_PHONESLEVEL_HIGAIN          0x00000000
521 #define FF_SWPARAM_PHONESLEVEL_4dBU            0x00000001
522 #define FF_SWPARAM_PHONESLEVEL_m10dBV          0x00000002
523 #define FF_SWPARAM_INPUT_OPT_B                 0x00000001
524 #define FF_SWPARAM_INPUT_OPT_A                 0x00000002
525
526 #define FF_SWPARAM_FF800_INPUT_OPT_FRONT       FF_SWPARAM_INPUT_OPT_A
527 #define FF_SWPARAM_FF800_INPUT_OPT_REAR        FF_SWPARAM_INPUT_OPT_B
528
529 // Flags for the "status" parameter of setInputInstrOpt()
530 #define FF400_INSTR_OPT_ACTIVE  0x01
531 #define FF800_INSTR_OPT_FILTER  0x02
532 #define FF800_INSTR_OPT_FUZZ    0x04
533 #define FF800_INSTR_OPT_LIMITER 0x08
534
535 // Flags for the *_mixerflags fields
536 #define FF_SWPARAM_MF_NORMAL    0x00
537 #define FF_SWPARAM_MF_MUTED     0x01
538 #define FF_SWPARAM_MF_INVERTED  0x02    // Inputs/playbacks only
539 #define FF_SWPARAM_MF_REC       0x04    // Outputs only
540
541 // Indices into the amp_gains array
542 #define FF400_AMPGAIN_MIC1      0
543 #define FF400_AMPGAIN_MIC2      1
544 #define FF400_AMPGAIN_INPUT3    2
545 #define FF400_AMPGAIN_INPUT4    3
546 #define FF400_AMPGAIN_OUTPUT1   4
547 #define FF400_AMPGAIN_OUTPUT2   5
548 #define FF400_AMPGAIN_OUTPUT3   6
549 #define FF400_AMPGAIN_OUTPUT4   7
550 #define FF400_AMPGAIN_OUTPUT5   8
551 #define FF400_AMPGAIN_OUTPUT6   9
552 #define FF400_AMPGAIN_PHONES_L 10
553 #define FF400_AMPGAIN_PHONES_R 11
554 #define FF400_AMPGAIN_SPDIF1   12
555 #define FF400_AMPGAIN_SPDIF2   13
556 #define FF400_AMPGAIN_ADAT1_1  14
557 #define FF400_AMPGAIN_ADAT1_2  15
558 #define FF400_AMPGAIN_ADAT1_3  16
559 #define FF400_AMPGAIN_ADAT1_4  17
560 #define FF400_AMPGAIN_ADAT1_5  18
561 #define FF400_AMPGAIN_ADAT1_6  19
562 #define FF400_AMPGAIN_ADAT1_7  20
563 #define FF400_AMPGAIN_ADAT1_8  21
564 #define FF400_AMPGAIN_NUM      22
565
566 // The general Fireface state
567 typedef struct {
568     uint32_t is_streaming;
569     uint32_t clock_mode;
570     uint32_t autosync_source;
571     uint32_t autosync_freq;
572     uint32_t spdif_freq;
573     uint32_t adat1_sync_status, adat2_sync_status;
574     uint32_t spdif_sync_status;
575     uint32_t wclk_sync_status, tco_sync_status;
576 } FF_state_t;
577
578 #define FF_STATE_CLOCKMODE_MASTER              0
579 #define FF_STATE_CLOCKMODE_AUTOSYNC            1
580 #define FF_STATE_AUTOSYNC_SRC_NOLOCK           0
581 #define FF_STATE_AUTOSYNC_SRC_ADAT1            1
582 #define FF_STATE_AUTOSYNC_SRC_ADAT2            2
583 #define FF_STATE_AUTOSYNC_SRC_SPDIF            3
584 #define FF_STATE_AUTOSYNC_SRC_WCLK             4
585 #define FF_STATE_AUTOSYNC_SRC_TCO              5
586 #define FF_STATE_SYNC_NOLOCK                   0
587 #define FF_STATE_SYNC_LOCKED                   1
588 #define FF_STATE_SYNC_SYNCED                   2
589
590 // Data structure for the TCO (Time Code Option) state
591 typedef struct {
592     uint32_t input;
593     uint32_t frame_rate;
594     uint32_t word_clock;
595     uint32_t sample_rate;
596     uint32_t pull;
597     uint32_t termination;
598     uint32_t MTC;
599 } FF_TCO_settings_t;
600
601 // Defines used to configure selected quadlets of the TCO read space.  Some
602 // of these are also used when configuring the TCO.  The byte indices
603 // referenced in the define names are 0-based.
604
605 // TCO quadlet 0
606 #define FF_TCO0_MTC                           0x80000000
607
608 // TCO quadlet 1
609 #define FF_TCO1_TCO_lock                      0x00000001
610 #define FF_TCO1_WORD_CLOCK_INPUT_RATE0        0x00000002
611 #define FF_TCO1_WORD_CLOCK_INPUT_RATE1        0x00000004
612 #define FF_TCO1_LTC_INPUT_VALID               0x00000008
613 #define FF_TCO1_WORD_CLOCK_INPUT_VALID        0x00000010
614 #define FF_TCO1_VIDEO_INPUT_NTSC              0x00000020
615 #define FF_TCO1_VIDEO_INPUT_PAL               0x00000040
616 #define FF_TCO1_SET_TC                        0x00000100
617 #define FF_TCO1_SET_DROPFRAME                 0x00000200
618 #define FF_TCO1_LTC_FORMAT0                   0x00000400
619 #define FF_TCO1_LTC_FORMAT1                   0x00000800
620
621 #define FF_TCO1_WORD_CLOCK_INPUT_1x           0
622 #define FF_TCO1_WORD_CLOCK_INPUT_2x           FF_TCO1_WORD_CLOCK_INPUT_RATE0
623 #define FF_TCO1_WORD_CLOCK_INPUT_4x           FF_TCO1_WORD_CLOCK_INPUT_RATE1
624 #define FF_TCO1_WORD_CLOCK_INPUT_MASK         (FF_TCO1_WORD_CLOCK_INPUT_RATE0|FF_TCO1_WORD_CLOCK_INPUT_RATE1)
625 #define FF_TCO1_VIDEO_INPUT_MASK              (FF_TCO1_VIDEO_INPUT_NTSC|FF_TCO1_VIDEO_INPUT_PAL)
626 #define FF_TC01_LTC_FORMAT_24fps              0
627 #define FF_TCO1_LTC_FORMAT_25fps              FF_TCO1_LTC_FORMAT0
628 #define FF_TC01_LTC_FORMAT_29_97fps           FF_TCO1_LTC_FORMAT1
629 #define FF_TCO1_LTC_FORMAT_29_97dpfs          (FF_TCO1_LTC_FORMAT1|FF_TCO1_SET_DROPFRAME)
630 #define FF_TCO1_LTC_FORMAT_30fps              (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1)
631 #define FF_TCO1_LTC_FORMAT_30dfps             (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1|FF_TCO1_SET_DROPFRAME)
632 #define FF_TCO1_LTC_FORMAT_MASK               (FF_TCO1_LTC_FORMAT0|FF_TCO1_LTC_FORMAT1)
633
634 // TCO quadlet 2
635 #define FF_TCO2_TC_RUN                        0x00010000
636 #define FF_TCO2_WORD_CLOCK_CONV0              0x00020000
637 #define FF_TCO2_WORD_CLOCK_CONV1              0x00040000
638 #define FF_TCO2_NUM_DROPFRAMES0               0x00080000 // Unused
639 #define FF_TCO2_NUM_DROPFRAMES1               0x00100000 // Unused
640 #define FF_TCO2_SET_JAM_SYNC                  0x00200000
641 #define FF_TCO2_SET_FLYWHEEL                  0x00400000
642 #define FF_TCO2_SET_01_4                      0x01000000
643 #define FF_TCO2_SET_PULLDOWN                  0x02000000
644 #define FF_TCO2_SET_PULLUP                    0x04000000
645 #define FF_TCO2_SET_FREQ                      0x08000000
646 #define FF_TCO2_SET_TERMINATION               0x10000000
647 #define FF_TCO2_SET_INPUT0                    0x20000000
648 #define FF_TCO2_SET_INPUT1                    0x40000000
649 #define FF_TCO2_SET_FREQ_FROM_APP             0x80000000
650
651 #define FF_TCO2_WORD_CLOCK_CONV_1_1           0
652 #define FF_TCO2_WORD_CLOCK_CONV_44_48         FF_TCO2_WORD_CLOCK_CONV0
653 #define FF_TCO2_WORD_CLOCK_CONV_48_44         FF_TCO2_WORD_CLOCK_CONV1
654 #define FF_TCO2_PULL_0                        0
655 #define FF_TCO2_PULL_UP_01                    FF_TCO2_SET_PULLUP
656 #define FF_TCO2_PULL_DOWN_01                  FF_TCO2_SET_PULLDOWN
657 #define FF_TCO2_PULL_UP_40                    (FF_TCO2_SET_PULLUP|FF_TCO2_SET_01_4)
658 #define FF_TCO2_PULL_DOWN_40                  (FF_TCO2_SET_PULLDOWN|FF_TCO2_SET_01_4)
659 #define FF_TCO2_INPUT_LTC                     FF_TCO2_SET_INPUT1
660 #define FF_TCO2_INPUT_VIDEO                   FF_TCO2_SET_INPUT0
661 #define FF_TCO2_INPUT_WORD_CLOCK              0
662 #define FF_TCO2_SRATE_44_1                    0
663 #define FF_TCO2_SRATE_48                      FF_TCO2_SET_FREQ
664 #define FF_TCO2_SRATE_FROM_APP                FF_TCO2_SET_FREQ_FROM_APP
665
666 // Interpretation of the TCO software settings fields
667 #define FF_TCOPARAM_INPUT_LTC                 1
668 #define FF_TCOPARAM_INPUT_VIDEO               2
669 #define FF_TCOPARAM_INPUT_WCK                 3
670 #define FF_TCOPARAM_FRAMERATE_24fps           1
671 #define FF_TCOPARAM_FRAMERATE_25fps           2
672 #define FF_TCOPARAM_FRAMERATE_29_97fps        3
673 #define FF_TCOPARAM_FRAMERATE_29_97dfps       4
674 #define FF_TCOPARAM_FRAMERATE_30fps           5
675 #define FF_TCOPARAM_FRAMERATE_30dfps          6
676 #define FF_TCOPARAM_WORD_CLOCK_CONV_1_1       1     // 1:1
677 #define FF_TCOPARAM_WORD_CLOCK_CONV_44_48     2     // 44.1 kHz-> 48 kHz
678 #define FF_TCOPARAM_WORD_CLOCK_CONV_48_44     3     // 48 kHz -> 44.1 kHz
679 #define FF_TCOPARAM_SRATE_44_1                1     // Rate is 44.1 kHz
680 #define FF_TCOPARAM_SRATE_48                  2     // Rate is 48 kHz
681 #define FF_TCOPARAM_SRATE_FROM_APP            3
682 #define FF_TCOPARAM_PULL_NONE                 1
683 #define FF_TCOPARAM_PULL_UP_01                2     // +0.1%
684 #define FF_TCOPARAM_PULL_DOWN_01              3     // -0.1%
685 #define FF_TCOPARAM_PULL_UP_40                4     // +4.0%
686 #define FF_TCOPARAM_PULL_DOWN_40              5     // -4.0%
687 #define FF_TCOPARAM_TERMINATION_ON            1
688
689 // The state of the TCO
690 typedef struct {
691   unsigned int locked, ltc_valid;
692   unsigned int hours, minutes, seconds, frames;
693   unsigned int frame_rate;
694   unsigned int drop_frame;
695   unsigned int video_input;
696   unsigned int word_clock_state;
697   float sample_rate;
698 } FF_TCO_state_t;
699
700 // TCO state field defines
701 #define FF_TCOSTATE_FRAMERATE_24fps           1
702 #define FF_TCOSTATE_FRAMERATE_25fps           2
703 #define FF_TCOSTATE_FRAMERATE_29_97fps        3
704 #define FF_TCOSTATE_FRAMERATE_30fps           4
705 #define FF_TCOSTATE_VIDEO_NONE                0
706 #define FF_TCOSTATE_VIDEO_PAL                 1
707 #define FF_TCOSTATE_VIDEO_NTSC                2
708 #define FF_TCOSTATE_WORDCLOCK_NONE            0
709 #define FF_TCOSTATE_WORDCLOCK_1x              1
710 #define FF_TCOSTATE_WORDCLOCK_2x              2
711 #define FF_TCOSTATE_WORDCLOCK_4x              3
712
713 #endif
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