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/* |
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* Copyright (C) 2009 by Jonathan Woithe |
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* |
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* This file is part of FFADO |
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* FFADO = Free FireWire (pro-)audio drivers for Linux |
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* |
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* FFADO is based upon FreeBoB. |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 2 of the License, or |
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* (at your option) version 3 of the License. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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* |
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*/ |
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/* This file implements miscellaneous lower-level hardware functions for the Fireface */ |
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#include <math.h> |
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#include "libieee1394/configrom.h" |
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#include "libieee1394/ieee1394service.h" |
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#include "rme/rme_avdevice.h" |
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#include "rme/fireface_def.h" |
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#include "debugmodule/debugmodule.h" |
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namespace Rme { |
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37 |
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unsigned int |
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Device::multiplier_of_freq(unsigned int freq) |
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{ |
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if (freq > MIN_QUAD_SPEED) |
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return 4; |
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if (freq > MIN_DOUBLE_SPEED) |
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return 2; |
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return 1; |
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} |
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void |
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Device::config_lock(void) { |
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rme_shm_lock(dev_config); |
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} |
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void |
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Device::config_unlock(void) { |
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rme_shm_unlock(dev_config); |
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} |
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signed int |
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Device::init_hardware(void) |
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{ |
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signed int ret = 0; |
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signed int src, dest; |
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signed int n_channels; |
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signed int have_mixer_settings = 0; |
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|
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switch (m_rme_model) { |
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case RME_MODEL_FIREFACE400: n_channels = RME_FF400_MAX_CHANNELS; break; |
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case RME_MODEL_FIREFACE800: n_channels = RME_FF800_MAX_CHANNELS; break; |
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default: |
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debugOutput(DEBUG_LEVEL_ERROR, "unknown model %d\n", m_rme_model); |
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return -1; |
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} |
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// Initialises the device's settings structure to a known state and then |
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// sets the hardware to reflect this state. |
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config_lock(); |
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// If the software state is not yet valid, attempt to obtain settings |
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// from the device flash. If that fails for some reason, initialise |
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// with a static setup. |
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if (dev_config->settings_valid == 0) { |
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dev_config->settings_valid = read_device_flash_settings(settings) == 0; |
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// If valid settings were read, write them to the device so we can |
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// be sure that this mirrors how the device is currently configured. |
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// This is also needed so the "host" LED is extinguished on first |
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// use after power up. Also use the stored sample rate as the |
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// operational rate. |
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if (dev_config->settings_valid) { |
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dev_config->software_freq = settings->sample_rate; |
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// dds_freq can be used to run the audio clock at a slightly |
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// different frequency to what the software requests (to allow |
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// for drop-frame rates for example). For the moment FFADO |
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// provides no explicit support for this, so dds_freq should |
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// always be zero. |
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// |
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// If user access to dds_freq is implemented in future, it may |
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// or may not be desireable to set dds_freq from |
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// settings->sample_rate. This will probably be determined by |
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// the nature of the user interface to dds_freq. |
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// |
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// See also comments in getSamplingFrequency() and |
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// setDDSFrequency(). |
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dev_config->dds_freq = 0; |
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set_hardware_params(settings); |
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} |
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} |
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// If no valid flash settings, configure with a static setup. |
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if (dev_config->settings_valid == 0) { |
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debugOutput(DEBUG_LEVEL_VERBOSE, "flash settings unavailable or invalid; using defaults\n"); |
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memset(settings, 0, sizeof(*settings)); |
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settings->spdif_input_mode = FF_SWPARAM_SPDIF_INPUT_COAX; |
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settings->spdif_output_mode = FF_SWPARAM_SPDIF_OUTPUT_COAX; |
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settings->clock_mode = FF_SWPARAM_CLOCK_MODE_MASTER; |
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settings->sync_ref = FF_SWPARAM_SYNCREF_WORDCLOCK; |
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settings->input_level = FF_SWPARAM_ILEVEL_LOGAIN; |
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settings->output_level = FF_SWPARAM_OLEVEL_HIGAIN; |
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settings->phones_level = FF_SWPARAM_PHONESLEVEL_HIGAIN; |
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settings->limit_bandwidth = FF_SWPARAM_BWLIMIT_SEND_ALL_CHANNELS; |
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// A default sampling rate. An explicit DDS frequency is not enabled |
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// by default (FFADO doesn't currently make explicit use of this - see |
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// above). |
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dev_config->software_freq = 44100; |
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dev_config->dds_freq = 0; |
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settings->sample_rate = dev_config->software_freq; |
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// TODO: set input amplifier gains to a value other than 0? |
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// TODO: store and manipulate channel mute/rec flags |
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// The FF800 needs the input source set via the input options. |
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// The device's default has the limiter enabled so we'll follow |
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// that convention. |
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if (m_rme_model == RME_MODEL_FIREFACE800) { |
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settings->input_opt[0] = settings->input_opt[1] = |
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settings->input_opt[2] = FF_SWPARAM_FF800_INPUT_OPT_FRONT; |
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settings->limiter = 1; |
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} |
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// Configure the hardware to match the current software status. |
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// This is only done if the settings valid flag is 0; if it is 1 it |
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// indicates that something has already set the device up to match |
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// the software settings so there's no need to do it again. |
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if (set_hardware_params(settings) != 0) |
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ret = -1; |
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if (ret==0) { |
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signed freq = dev_config->software_freq; |
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if (dev_config->dds_freq > 0) |
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freq = dev_config->dds_freq; |
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if (set_hardware_dds_freq(freq) != 0) |
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ret = -1; |
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} |
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if (m_rme_model == RME_MODEL_FIREFACE400) { |
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signed int i; |
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for (i=FF400_AMPGAIN_MIC1; i<=FF400_AMPGAIN_INPUT4; i++) { |
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set_hardware_ampgain(i, settings->amp_gains[i]); |
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} |
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} |
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dev_config->settings_valid = 1; |
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} |
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have_mixer_settings = read_device_mixer_settings(settings) == 0; |
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// Matrix mixer settings |
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for (dest=0; dest<n_channels; dest++) { |
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for (src=0; src<n_channels; src++) { |
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if (!have_mixer_settings) |
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settings->input_faders[getMixerGainIndex(src, dest)] = 0; |
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set_hardware_mixergain(RME_FF_MM_INPUT, src, dest, settings->input_faders[getMixerGainIndex(src, dest)]); |
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} |
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for (src=0; src<n_channels; src++) { |
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if (!have_mixer_settings) |
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settings->playback_faders[getMixerGainIndex(src, dest)] = |
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src==dest?0x8000:0; |
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set_hardware_mixergain(RME_FF_MM_PLAYBACK, src, dest, |
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settings->playback_faders[getMixerGainIndex(src, dest)]); |
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} |
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} |
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for (src=0; src<n_channels; src++) { |
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if (!have_mixer_settings) |
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settings->output_faders[src] = 0x8000; |
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set_hardware_mixergain(RME_FF_MM_OUTPUT, src, 0, settings->output_faders[src]); |
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} |
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set_hardware_output_rec(0); |
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if (ret==0 && m_rme_model==RME_MODEL_FIREFACE400 && provide_midi) { |
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// Precisely mirror the method used under other operating systems to |
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// set the high quadlet of the MIDI ARM address, even though it is a |
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// little inflexible. We can refine this later if need be. This is |
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// only done if FFADO is providing MIDI functionality. If not, the |
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// RME_FF400_MIDI_HIGH_ADDR is left alone for other drivers (such as |
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// snd-fireface in Linux kernel >= 4.12) to configure if desired. |
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unsigned int node_id = getConfigRom().getNodeId(); |
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unsigned int midi_hi_addr; |
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midi_hi_addr = 0x01; |
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if (writeRegister(RME_FF400_MIDI_HIGH_ADDR, (node_id<<16) | midi_hi_addr) != 0) { |
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debugOutput(DEBUG_LEVEL_ERROR, "failed to write MIDI high address register\n"); |
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ret = -1; |
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} |
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} |
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// Also configure the TCO (Time Code Option) settings for those devices |
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// which have a TCO. |
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if (ret==0 && dev_config->tco_settings_valid==0) { |
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if (dev_config->tco_present) { |
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FF_TCO_state_t tco_state; |
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memset(tco_settings, 0, sizeof(*tco_settings)); |
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if (read_tco_state(&tco_state) == 0) { |
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if (tco_state.ltc_valid) { |
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tco_settings->input = FF_TCOPARAM_INPUT_LTC; |
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switch (tco_state.frame_rate) { |
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case FF_TCOSTATE_FRAMERATE_24fps: |
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tco_settings->frame_rate = FF_TCOPARAM_FRAMERATE_24fps; |
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break; |
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case FF_TCOSTATE_FRAMERATE_25fps: |
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tco_settings->frame_rate = FF_TCOPARAM_FRAMERATE_25fps; |
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break; |
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case FF_TCOSTATE_FRAMERATE_29_97fps: |
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tco_settings->frame_rate = FF_TCOPARAM_FRAMERATE_29_97fps; |
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break; |
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case FF_TCOSTATE_FRAMERATE_30fps: |
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tco_settings->frame_rate = FF_TCOPARAM_FRAMERATE_30fps; |
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default: |
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tco_settings->frame_rate = FF_TCOPARAM_FRAMERATE_25fps; |
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} |
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if (tco_state.drop_frame) { |
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tco_settings->frame_rate += 1; |
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} |
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} else { |
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tco_settings->input = FF_TCOPARAM_INPUT_VIDEO; |
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tco_settings->frame_rate = FF_TCOPARAM_FRAMERATE_25fps; |
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} |
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tco_settings->word_clock = FF_TCOPARAM_WORD_CLOCK_CONV_1_1; |
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tco_settings->sample_rate = ((settings->sample_rate % 48000)==0) ? |
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FF_TCOPARAM_SRATE_48 : FF_TCOPARAM_SRATE_44_1; |
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tco_settings->pull = FF_TCOPARAM_PULL_NONE; |
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tco_settings->termination = 0; |
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tco_settings->MTC = 0; |
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} else { |
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debugOutput(DEBUG_LEVEL_ERROR, "failed to read TCO state\n"); |
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} |
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if (write_tco_settings(tco_settings) != 0) { |
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debugOutput(DEBUG_LEVEL_ERROR, "failed to write TCO settings\n"); |
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} |
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} |
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dev_config->tco_settings_valid = 1; |
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} |
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config_unlock(); |
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return ret; |
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} |
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signed int |
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Device::get_hardware_status(unsigned int *stat0, unsigned int *stat1) |
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{ |
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unsigned int buf[2]; |
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if (readBlock(RME_FF_STATUS_REG0, buf, 2) != 0) |
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return -1; |
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*stat0 = buf[0]; |
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*stat1 = buf[1]; |
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return 0; |
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} |
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signed int |
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Device::get_hardware_streaming_status(unsigned int *stat, unsigned int n) |
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{ |
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// Get the hardware status as it applies to the streaming system. This |
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// involves a request of 4 quadlets from the status register. It |
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// appears that the first register's definition is slightly different in |
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// this situation compared to when only 2 quadlets are requested as is |
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// done in get_hardware_status(). |
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// |
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// "n" is the size of the passed-in stat array. It must be >= 4. |
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if (n < 4) |
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return -1; |
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if (readBlock(RME_FF_STATUS_REG0, stat, 4) != 0) |
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return -1; |
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return 0; |
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} |
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|
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signed int |
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Device::get_hardware_state(FF_state_t *state) |
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{ |
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// Retrieve the hardware status and deduce the device state. Return |
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// -1 on error, 0 on success. The given state structure will be |
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// cleared by this call. |
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static signed int call_count = 0; |
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unsigned int stat0, stat1; |
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memset(state, 0, sizeof(*state)); |
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if (get_hardware_status(&stat0, &stat1) != 0) |
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return -1; |
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state->is_streaming = dev_config->is_streaming; |
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state->clock_mode = (settings->clock_mode == FF_SWPARAM_CLOCK_MODE_MASTER)?FF_STATE_CLOCKMODE_MASTER:FF_STATE_CLOCKMODE_AUTOSYNC; |
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switch (stat0 & SR0_AUTOSYNC_SRC_MASK) { |
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case SR0_AUTOSYNC_SRC_ADAT1: |
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state->autosync_source = FF_STATE_AUTOSYNC_SRC_ADAT1; |
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break; |
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case SR0_AUTOSYNC_SRC_ADAT2: |
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state->autosync_source = FF_STATE_AUTOSYNC_SRC_ADAT2; |
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break; |
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case SR0_AUTOSYNC_SRC_SPDIF: |
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state->autosync_source = FF_STATE_AUTOSYNC_SRC_SPDIF; |
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break; |
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case SR0_AUTOSYNC_SRC_WCLK: |
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state->autosync_source = FF_STATE_AUTOSYNC_SRC_WCLK; |
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break; |
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case SR0_AUTOSYNC_SRC_TCO: |
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state->autosync_source = FF_STATE_AUTOSYNC_SRC_TCO; |
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break; |
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default: state->autosync_source = FF_STATE_AUTOSYNC_SRC_NOLOCK; |
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} |
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|
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switch (stat0 & SR0_AUTOSYNC_FREQ_MASK) { |
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case SR0_AUTOSYNC_FREQ_32k: state->autosync_freq = 32000; break; |
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case SR0_AUTOSYNC_FREQ_44k1: state->autosync_freq = 44100; break; |
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case SR0_AUTOSYNC_FREQ_48k: state->autosync_freq = 48000; break; |
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case SR0_AUTOSYNC_FREQ_64k: state->autosync_freq = 64000; break; |
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case SR0_AUTOSYNC_FREQ_88k2: state->autosync_freq = 88200; break; |
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case SR0_AUTOSYNC_FREQ_96k: state->autosync_freq = 96000; break; |
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case SR0_AUTOSYNC_FREQ_128k: state->autosync_freq = 128000; break; |
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case SR0_AUTOSYNC_FREQ_176k4:state->autosync_freq = 176400; break; |
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case SR0_AUTOSYNC_FREQ_192k: state->autosync_freq = 192000; break; |
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} |
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|
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switch (stat0 & SR0_SPDIF_FREQ_MASK) { |
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case SR0_SPDIF_FREQ_32k: state->spdif_freq = 32000; break; |
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case SR0_SPDIF_FREQ_44k1: state->spdif_freq = 41000; break; |
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case SR0_SPDIF_FREQ_48k: state->spdif_freq = 48000; break; |
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case SR0_SPDIF_FREQ_64k: state->spdif_freq = 64000; break; |
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case SR0_SPDIF_FREQ_88k2: state->spdif_freq = 88200; break; |
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case SR0_SPDIF_FREQ_96k: state->spdif_freq = 96000; break; |
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case SR0_SPDIF_FREQ_128k: state->spdif_freq = 128000; break; |
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case SR0_SPDIF_FREQ_176k4:state->spdif_freq = 176400; break; |
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case SR0_SPDIF_FREQ_192k: state->spdif_freq = 192000; break; |
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} |
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|
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switch (stat0 & SR0_ADAT1_STATUS_MASK) { |
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case SR0_ADAT1_STATUS_NOLOCK: |
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state->adat1_sync_status = FF_STATE_SYNC_NOLOCK; break; |
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case SR0_ADAT1_STATUS_LOCK: |
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state->adat1_sync_status = FF_STATE_SYNC_LOCKED; break; |
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case SR0_ADAT1_STATUS_SYNC: |
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state->adat1_sync_status = FF_STATE_SYNC_SYNCED; break; |
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} |
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switch (stat0 & SR0_ADAT2_STATUS_MASK) { |
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case SR0_ADAT2_STATUS_NOLOCK: |
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state->adat2_sync_status = FF_STATE_SYNC_NOLOCK; break; |
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case SR0_ADAT2_STATUS_LOCK: |
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state->adat2_sync_status = FF_STATE_SYNC_LOCKED; break; |
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case SR0_ADAT2_STATUS_SYNC: |
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state->adat2_sync_status = FF_STATE_SYNC_SYNCED; break; |
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363 |
} |
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364 |
switch (stat0 & SR0_SPDIF_STATUS_MASK) { |
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case SR0_SPDIF_STATUS_NOLOCK: |
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state->spdif_sync_status = FF_STATE_SYNC_NOLOCK; break; |
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case SR0_SPDIF_STATUS_LOCK: |
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state->spdif_sync_status = FF_STATE_SYNC_LOCKED; break; |
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case SR0_SPDIF_STATUS_SYNC: |
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state->spdif_sync_status = FF_STATE_SYNC_SYNCED; break; |
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371 |
} |
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372 |
switch (stat0 & SR0_WCLK_STATUS_MASK) { |
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373 |
case SR0_WCLK_STATUS_NOLOCK: |
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state->wclk_sync_status = FF_STATE_SYNC_NOLOCK; break; |
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case SR0_WCLK_STATUS_LOCK: |
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state->wclk_sync_status = FF_STATE_SYNC_LOCKED; break; |
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case SR0_WCLK_STATUS_SYNC: |
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378 |
state->wclk_sync_status = FF_STATE_SYNC_SYNCED; break; |
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379 |
} |
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380 |
switch (stat1 & SR1_TCO_STATUS_MASK) { |
---|
381 |
case SR1_TCO_STATUS_NOLOCK: |
---|
382 |
state->tco_sync_status = FF_STATE_SYNC_NOLOCK; break; |
---|
383 |
case SR1_TCO_STATUS_LOCK: |
---|
384 |
state->tco_sync_status = FF_STATE_SYNC_LOCKED; break; |
---|
385 |
case SR1_TCO_STATUS_SYNC: |
---|
386 |
state->tco_sync_status = FF_STATE_SYNC_SYNCED; break; |
---|
387 |
} |
---|
388 |
|
---|
389 |
// Report the state reported by the hardware if debug output is active. |
---|
390 |
// Only do this for the first few calls. |
---|
391 |
if (call_count < 2) { |
---|
392 |
debugOutput(DEBUG_LEVEL_VERBOSE, "State reported by hardware:\n"); |
---|
393 |
debugOutput(DEBUG_LEVEL_VERBOSE, " is_streaming: %d\n", state->is_streaming); |
---|
394 |
debugOutput(DEBUG_LEVEL_VERBOSE, " clock_mode: %s\n", state->clock_mode==FF_STATE_CLOCKMODE_MASTER?"master":"autosync/slave"); |
---|
395 |
debugOutput(DEBUG_LEVEL_VERBOSE, " autosync source: %d\n", state->autosync_source); |
---|
396 |
debugOutput(DEBUG_LEVEL_VERBOSE, " autosync freq: %d\n", state->autosync_freq); |
---|
397 |
debugOutput(DEBUG_LEVEL_VERBOSE, " spdif freq: %d\n", state->spdif_freq); |
---|
398 |
debugOutput(DEBUG_LEVEL_VERBOSE, " ADAT 1/2 status: %x, %x\n", state->adat1_sync_status, state->adat2_sync_status); |
---|
399 |
debugOutput(DEBUG_LEVEL_VERBOSE, " SDPIF status: %x\n", state->spdif_sync_status); |
---|
400 |
debugOutput(DEBUG_LEVEL_VERBOSE, " Wclk/tco status: %x, %x\n", state->wclk_sync_status, state->tco_sync_status); |
---|
401 |
call_count++; |
---|
402 |
} |
---|
403 |
return 0; |
---|
404 |
} |
---|
405 |
|
---|
406 |
signed int |
---|
407 |
Device::set_hardware_params(FF_software_settings_t *use_settings) |
---|
408 |
{ |
---|
409 |
// Initialises the hardware to the state defined by the supplied |
---|
410 |
// software settings structure (which will usually be the device's |
---|
411 |
// "settings" structure). This has the side effect of extinguishing the |
---|
412 |
// "Host" LED on the FF400 when done for the first time after the |
---|
413 |
// interface has been powered up. |
---|
414 |
// |
---|
415 |
// If use_settings is NULL, the device's current settings structure will |
---|
416 |
// be used to source the configuration information. |
---|
417 |
|
---|
418 |
FF_software_settings_t *sw_settings; |
---|
419 |
quadlet_t data[3] = {0, 0, 0}; |
---|
420 |
unsigned int conf_reg; |
---|
421 |
|
---|
422 |
if (use_settings == NULL) |
---|
423 |
sw_settings = settings; |
---|
424 |
else |
---|
425 |
sw_settings = use_settings; |
---|
426 |
|
---|
427 |
if (sw_settings->mic_phantom[0]) |
---|
428 |
data[0] |= CR0_PHANTOM_MIC0; |
---|
429 |
if (sw_settings->mic_phantom[1]) |
---|
430 |
data[0] |= CR0_PHANTOM_MIC1; |
---|
431 |
switch (m_rme_model) { |
---|
432 |
case RME_MODEL_FIREFACE800: |
---|
433 |
if (sw_settings->mic_phantom[2]) |
---|
434 |
data[0] |= CR0_FF800_PHANTOM_MIC9; |
---|
435 |
if (sw_settings->mic_phantom[3]) |
---|
436 |
data[0] |= CR0_FF800_PHANTOM_MIC10; |
---|
437 |
break; |
---|
438 |
case RME_MODEL_FIREFACE400: |
---|
439 |
if (sw_settings->ff400_input_pad[0]) |
---|
440 |
data[0] |= CR0_FF400_CH3_PAD; |
---|
441 |
if (sw_settings->ff400_input_pad[1]) |
---|
442 |
data[0] |= CR0_FF400_CH4_PAD; |
---|
443 |
break; |
---|
444 |
default: |
---|
445 |
break; |
---|
446 |
} |
---|
447 |
|
---|
448 |
/* Phones level */ |
---|
449 |
if (m_rme_model == RME_MODEL_FIREFACE400) { |
---|
450 |
switch (sw_settings->phones_level) { |
---|
451 |
case FF_SWPARAM_PHONESLEVEL_HIGAIN: |
---|
452 |
data[0] |= CRO_PHLEVEL_HIGAIN; |
---|
453 |
break; |
---|
454 |
case FF_SWPARAM_PHONESLEVEL_4dBU: |
---|
455 |
data[0] |= CR0_PHLEVEL_4dBU; |
---|
456 |
break; |
---|
457 |
case FF_SWPARAM_PHONESLEVEL_m10dBV: |
---|
458 |
data[0] |= CRO_PHLEVEL_m10dBV; |
---|
459 |
break; |
---|
460 |
} |
---|
461 |
} |
---|
462 |
|
---|
463 |
/* Input level */ |
---|
464 |
switch (sw_settings->input_level) { |
---|
465 |
case FF_SWPARAM_ILEVEL_LOGAIN: // Low gain |
---|
466 |
data[1] |= CR1_ILEVEL_CPLD_LOGAIN; // CPLD |
---|
467 |
data[0] |= CR0_ILEVEL_FPGA_LOGAIN; // LED control (used on FF800 only) |
---|
468 |
break; |
---|
469 |
case FF_SWPARAM_ILEVEL_4dBU: // +4 dBu |
---|
470 |
data[1] |= CR1_ILEVEL_CPLD_4dBU; |
---|
471 |
data[0] |= CR0_ILEVEL_FPGA_4dBU; |
---|
472 |
break; |
---|
473 |
case FF_SWPARAM_ILEVEL_m10dBV: // -10 dBV |
---|
474 |
data[1] |= CR1_ILEVEL_CPLD_m10dBV; |
---|
475 |
data[0] |= CR0_ILEVEL_FPGA_m10dBV; |
---|
476 |
break; |
---|
477 |
} |
---|
478 |
|
---|
479 |
/* Output level */ |
---|
480 |
switch (sw_settings->output_level) { |
---|
481 |
case FF_SWPARAM_OLEVEL_HIGAIN: // High gain |
---|
482 |
data[1] |= CR1_OLEVEL_CPLD_HIGAIN; // CPLD |
---|
483 |
data[0] |= CR0_OLEVEL_FPGA_HIGAIN; // LED control (used on FF800 only) |
---|
484 |
break; |
---|
485 |
case FF_SWPARAM_OLEVEL_4dBU: // +4 dBu |
---|
486 |
data[1] |= CR1_OLEVEL_CPLD_4dBU; |
---|
487 |
data[0] |= CR0_OLEVEL_FPGA_4dBU; |
---|
488 |
break; |
---|
489 |
case FF_SWPARAM_OLEVEL_m10dBV: // -10 dBV |
---|
490 |
data[1] |= CR1_OLEVEL_CPLD_m10dBV; |
---|
491 |
data[0] |= CR0_OLEVEL_FPGA_m10dBV; |
---|
492 |
break; |
---|
493 |
} |
---|
494 |
|
---|
495 |
/* Set input options. The meaning of the options differs between |
---|
496 |
* devices, so we use the generic identifiers here. |
---|
497 |
*/ |
---|
498 |
data[1] |= (sw_settings->input_opt[1] & FF_SWPARAM_INPUT_OPT_A) ? CR1_INPUT_OPT1_A : 0; |
---|
499 |
data[1] |= (sw_settings->input_opt[1] & FF_SWPARAM_INPUT_OPT_B) ? CR1_INPUT_OPT1_B : 0; |
---|
500 |
data[1] |= (sw_settings->input_opt[2] & FF_SWPARAM_INPUT_OPT_A) ? CR1_INPUT_OPT2_A : 0; |
---|
501 |
data[1] |= (sw_settings->input_opt[2] & FF_SWPARAM_INPUT_OPT_B) ? CR1_INPUT_OPT2_B : 0; |
---|
502 |
|
---|
503 |
// Drive the speaker emulation / filter LED via FPGA in FF800. In FF400 |
---|
504 |
// the same bit controls the channel 4 "instrument" option. |
---|
505 |
if (m_rme_model == RME_MODEL_FIREFACE800) { |
---|
506 |
data[0] |= (sw_settings->filter) ? CR0_FF800_FILTER_FPGA : 0; |
---|
507 |
} else |
---|
508 |
if (m_rme_model == RME_MODEL_FIREFACE400) { |
---|
509 |
data[0] |= (sw_settings->ff400_instr_input[1]) ? CR0_FF400_CH4_INSTR : 0; |
---|
510 |
} |
---|
511 |
|
---|
512 |
// Set the "rear" option for input 0 if selected |
---|
513 |
data[1] |= (sw_settings->input_opt[0] & FF_SWPARAM_FF800_INPUT_OPT_REAR) ? CR1_FF800_INPUT1_REAR : 0; |
---|
514 |
|
---|
515 |
// The input 0 "front" option is activated using one of two bits |
---|
516 |
// depending on whether the filter (aka "speaker emulation") setting is |
---|
517 |
// active. |
---|
518 |
if (sw_settings->input_opt[0] & FF_SWPARAM_FF800_INPUT_OPT_FRONT) { |
---|
519 |
data[1] |= (sw_settings->filter) ? CR1_FF800_INPUT1_FRONT_WITH_FILTER : CR1_FF800_INPUT1_FRONT; |
---|
520 |
} |
---|
521 |
|
---|
522 |
data[2] |= (sw_settings->spdif_output_emphasis==FF_SWPARAM_SPDIF_OUTPUT_EMPHASIS_ON) ? CR2_SPDIF_OUT_EMP : 0; |
---|
523 |
data[2] |= (sw_settings->spdif_output_pro==FF_SWPARAM_SPDIF_OUTPUT_PRO_ON) ? CR2_SPDIF_OUT_PRO : 0; |
---|
524 |
data[2] |= (sw_settings->spdif_output_nonaudio==FF_SWPARAM_SPDIF_OUTPUT_NONAUDIO_ON) ? CR2_SPDIF_OUT_NONAUDIO : 0; |
---|
525 |
data[2] |= (sw_settings->spdif_output_mode==FF_SWPARAM_SPDIF_OUTPUT_OPTICAL) ? CR2_SPDIF_OUT_ADAT2 : 0; |
---|
526 |
data[2] |= (sw_settings->clock_mode==FF_SWPARAM_CLOCK_MODE_AUTOSYNC) ? CR2_CLOCKMODE_AUTOSYNC : CR2_CLOCKMODE_MASTER; |
---|
527 |
data[2] |= (sw_settings->spdif_input_mode==FF_SWPARAM_SPDIF_INPUT_COAX) ? CR2_SPDIF_IN_COAX : CR2_SPDIF_IN_ADAT2; |
---|
528 |
data[2] |= (sw_settings->word_clock_single_speed=FF_SWPARAM_WORD_CLOCK_1x) ? CR2_WORD_CLOCK_1x : 0; |
---|
529 |
|
---|
530 |
/* TMS / TCO toggle bits in CR2 are not set by other drivers */ |
---|
531 |
|
---|
532 |
/* Drive / fuzz in FF800. In FF400, the CR0 bit used by "Drive" controls |
---|
533 |
* the channel 3 "instrument" option. |
---|
534 |
*/ |
---|
535 |
if (m_rme_model == RME_MODEL_FIREFACE800) { |
---|
536 |
if (sw_settings->fuzz) |
---|
537 |
data[0] |= CR0_FF800_DRIVE_FPGA; // FPGA LED control |
---|
538 |
else |
---|
539 |
data[1] |= CR1_INSTR_DRIVE; // CPLD |
---|
540 |
} else |
---|
541 |
if (m_rme_model == RME_MODEL_FIREFACE400) { |
---|
542 |
data[0] |= (sw_settings->ff400_instr_input[0]) ? CR0_FF400_CH3_INSTR : 0; |
---|
543 |
} |
---|
544 |
|
---|
545 |
/* Drop-and-stop is hardwired on in other drivers */ |
---|
546 |
data[2] |= CR2_DROP_AND_STOP; |
---|
547 |
|
---|
548 |
if (m_rme_model==RME_MODEL_FIREFACE400 && !provide_midi) { |
---|
549 |
// If libffado is not providing MIDI, configure the register to |
---|
550 |
// allow snd-fireface (Linux kernel >= 4.12) - or any other driver |
---|
551 |
// for the FF400 which might appear in future - to do so if desired. |
---|
552 |
// The choice of tx address 1 matches that which is coded in |
---|
553 |
// snd-fireface as of kernel 4.12. |
---|
554 |
data[2] &= ~CR2_FF400_DISABLE_MIDI_TX_MASK; |
---|
555 |
data[2] |= CR2_FF400_SELECT_MIDI_TX_ADDR_1; |
---|
556 |
} |
---|
557 |
|
---|
558 |
switch (sw_settings->sync_ref) { |
---|
559 |
case FF_SWPARAM_SYNCREF_WORDCLOCK: |
---|
560 |
data[2] |= CR2_SYNC_WORDCLOCK; |
---|
561 |
break; |
---|
562 |
case FF_SWPARAM_SYNCREF_ADAT1: |
---|
563 |
data[2] |= CR2_SYNC_ADAT1; |
---|
564 |
break; |
---|
565 |
case FF_SWPARAM_SYNCREF_ADAT2: |
---|
566 |
data[2] |= CR2_SYNC_ADAT2; |
---|
567 |
break; |
---|
568 |
case FF_SWPARAM_SYNCREF_SPDIF: |
---|
569 |
data[2] |= CR2_SYNC_SPDIF; |
---|
570 |
break; |
---|
571 |
case FF_SWPARAM_SYNCREC_TCO: |
---|
572 |
data[2] |= CR2_SYNC_TCO; |
---|
573 |
break; |
---|
574 |
} |
---|
575 |
|
---|
576 |
// This is hardwired in other drivers |
---|
577 |
data[2] |= (CR2_FREQ0 + CR2_FREQ1 + CR2_DSPEED + CR2_QSSPEED); |
---|
578 |
|
---|
579 |
// The FF800 limiter can only be disabled if the front panel instrument |
---|
580 |
// input is in use, so it only makes sense that it is disabled when that |
---|
581 |
// input is in use. |
---|
582 |
data[2] |= (sw_settings->limiter==0 && |
---|
583 |
(sw_settings->input_opt[0]==FF_SWPARAM_FF800_INPUT_OPT_FRONT)) ? |
---|
584 |
CR2_DISABLE_LIMITER : 0; |
---|
585 |
|
---|
586 |
//This is just for testing - it's a known consistent configuration |
---|
587 |
//data[0] = 0x00020810; // Phantom off |
---|
588 |
//data[0] = 0x00020811; // Phantom on |
---|
589 |
//data[1] = 0x0000031e; |
---|
590 |
//data[2] = 0xc400101f; |
---|
591 |
debugOutput(DEBUG_LEVEL_VERBOSE, "set hardware registers: 0x%08x 0x%08x 0x%08x\n", |
---|
592 |
data[0], data[1], data[2]); |
---|
593 |
|
---|
594 |
switch (m_rme_model) { |
---|
595 |
case RME_MODEL_FIREFACE800: conf_reg = RME_FF800_CONF_REG; break; |
---|
596 |
case RME_MODEL_FIREFACE400: conf_reg = RME_FF400_CONF_REG; break; |
---|
597 |
default: |
---|
598 |
debugOutput(DEBUG_LEVEL_ERROR, "unimplemented model %d\n", m_rme_model); |
---|
599 |
return -1; |
---|
600 |
} |
---|
601 |
if (writeBlock(conf_reg, data, 3) != 0) { |
---|
602 |
debugOutput(DEBUG_LEVEL_ERROR, "failed to write device settings\n"); |
---|
603 |
return -1; |
---|
604 |
} |
---|
605 |
|
---|
606 |
return 0; |
---|
607 |
} |
---|
608 |
|
---|
609 |
signed int |
---|
610 |
Device::read_tco(quadlet_t *tco_data, signed int size) |
---|
611 |
{ |
---|
612 |
// Read the TCO registers and return the respective values in *tco_data. |
---|
613 |
// Return value is 0 on success, or -1 if there is no TCO present. |
---|
614 |
// "size" is the size (in quadlets) of the array pointed to by tco_data. |
---|
615 |
// To obtain all TCO data "size" should be at least 4. If the caller |
---|
616 |
// doesn't care about the data returned by the TCO, tco_data can be |
---|
617 |
// NULL. |
---|
618 |
quadlet_t buf[4]; |
---|
619 |
signed int i; |
---|
620 |
|
---|
621 |
// Only the Fireface 800 can have the TCO fitted |
---|
622 |
if (m_rme_model != RME_MODEL_FIREFACE800) |
---|
623 |
return -1; |
---|
624 |
|
---|
625 |
if (readBlock(RME_FF_TCO_READ_REG, buf, 4) != 0) |
---|
626 |
return -1; |
---|
627 |
|
---|
628 |
if (tco_data != NULL) { |
---|
629 |
for (i=0; i<((size<4)?size:4); i++) |
---|
630 |
tco_data[i] = buf[i]; |
---|
631 |
} |
---|
632 |
|
---|
633 |
if ( (buf[0] & 0x80808080) == 0x80808080 && |
---|
634 |
(buf[1] & 0x80808080) == 0x80808080 && |
---|
635 |
(buf[2] & 0x80808080) == 0x80808080 && |
---|
636 |
(buf[3] & 0x8000FFFF) == 0x80008000) { |
---|
637 |
// A TCO is present |
---|
638 |
return 0; |
---|
639 |
} |
---|
640 |
|
---|
641 |
return -1; |
---|
642 |
} |
---|
643 |
|
---|
644 |
signed int |
---|
645 |
Device::write_tco(quadlet_t *tco_data, signed int size) |
---|
646 |
{ |
---|
647 |
// Writes data to the TCO. No check is made as to whether a TCO is |
---|
648 |
// present in the current device. Return value is 0 on success or -1 on |
---|
649 |
// error. "size" is the size (in quadlets) of the data pointed to by |
---|
650 |
// "tco_data". The first 4 quadlets of tco_data are significant; all |
---|
651 |
// others are ignored. If fewer than 4 quadlets are supplied (as |
---|
652 |
// indicated by the "size" parameter, -1 will be returned. |
---|
653 |
if (size < 4) |
---|
654 |
return -1; |
---|
655 |
|
---|
656 |
// Don't bother trying to write if the device is not a FF800 since the |
---|
657 |
// TCO can only be fitted to a FF800. |
---|
658 |
if (m_rme_model != RME_MODEL_FIREFACE800) |
---|
659 |
return -1; |
---|
660 |
|
---|
661 |
if (writeBlock(RME_FF_TCO_WRITE_REG, tco_data, 4) != 0) |
---|
662 |
return -1; |
---|
663 |
|
---|
664 |
return 0; |
---|
665 |
} |
---|
666 |
|
---|
667 |
signed int |
---|
668 |
Device::hardware_is_streaming(void) |
---|
669 |
{ |
---|
670 |
// Return 1 if the hardware is streaming, 0 if not. |
---|
671 |
return dev_config->is_streaming; |
---|
672 |
} |
---|
673 |
|
---|
674 |
signed int |
---|
675 |
Device::read_tco_state(FF_TCO_state_t *tco_state) |
---|
676 |
{ |
---|
677 |
// Reads the current TCO state into the supplied state structure |
---|
678 |
|
---|
679 |
quadlet_t tc[4]; |
---|
680 |
unsigned int PLL_phase; |
---|
681 |
|
---|
682 |
if (read_tco(tc, 4) != 0) |
---|
683 |
return -1; |
---|
684 |
|
---|
685 |
// The timecode is stored in BCD (binary coded decimal) in register 0. |
---|
686 |
tco_state->frames = (tc[0] & 0xf) + ((tc[0] & 0x30) >> 4)*10; |
---|
687 |
tco_state->seconds = ((tc[0] & 0xf00) >> 8) + ((tc[0] & 0x7000) >> 12)*10; |
---|
688 |
tco_state->minutes = ((tc[0] & 0xf0000) >> 16) + ((tc[0] & 0x700000) >> 20)*10; |
---|
689 |
tco_state->hours = ((tc[0] & 0xf000000) >> 24) + ((tc[0] & 0x30000000) >> 28)*10; |
---|
690 |
|
---|
691 |
tco_state->locked = (tc[1] & FF_TCO1_TCO_lock) != 0; |
---|
692 |
tco_state->ltc_valid = (tc[1] & FF_TCO1_LTC_INPUT_VALID) != 0; |
---|
693 |
|
---|
694 |
switch (tc[1] & FF_TCO1_LTC_FORMAT_MASK) { |
---|
695 |
case FF_TC01_LTC_FORMAT_24fps: |
---|
696 |
tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_24fps; break; |
---|
697 |
case FF_TCO1_LTC_FORMAT_25fps: |
---|
698 |
tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_25fps; break; |
---|
699 |
case FF_TC01_LTC_FORMAT_29_97fps: |
---|
700 |
tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_29_97fps; break; |
---|
701 |
case FF_TCO1_LTC_FORMAT_30fps: |
---|
702 |
tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_30fps; break; |
---|
703 |
} |
---|
704 |
|
---|
705 |
tco_state->drop_frame = (tc[1] & FF_TCO1_SET_DROPFRAME) != 0; |
---|
706 |
|
---|
707 |
switch (tc[1] & FF_TCO1_VIDEO_INPUT_MASK) { |
---|
708 |
case FF_TCO1_VIDEO_INPUT_NTSC: |
---|
709 |
tco_state->video_input = FF_TCOSTATE_VIDEO_NTSC; break; |
---|
710 |
case FF_TCO1_VIDEO_INPUT_PAL: |
---|
711 |
tco_state->video_input = FF_TCOSTATE_VIDEO_PAL; break; |
---|
712 |
default: |
---|
713 |
tco_state->video_input = FF_TCOSTATE_VIDEO_NONE; |
---|
714 |
} |
---|
715 |
|
---|
716 |
if ((tc[1] & FF_TCO1_WORD_CLOCK_INPUT_VALID) == 0) { |
---|
717 |
tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_NONE; |
---|
718 |
} else { |
---|
719 |
switch (tc[1] & FF_TCO1_WORD_CLOCK_INPUT_MASK) { |
---|
720 |
case FF_TCO1_WORD_CLOCK_INPUT_1x: |
---|
721 |
tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_1x; break; |
---|
722 |
case FF_TCO1_WORD_CLOCK_INPUT_2x: |
---|
723 |
tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_2x; break; |
---|
724 |
case FF_TCO1_WORD_CLOCK_INPUT_4x: |
---|
725 |
tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_4x; break; |
---|
726 |
} |
---|
727 |
} |
---|
728 |
|
---|
729 |
PLL_phase = (tc[2] & 0x7f) + ((tc[2] & 0x7f00) >> 1); |
---|
730 |
tco_state->sample_rate = (25000000.0 * 16.0)/PLL_phase; |
---|
731 |
|
---|
732 |
return 0; |
---|
733 |
} |
---|
734 |
|
---|
735 |
signed int |
---|
736 |
Device::write_tco_settings(FF_TCO_settings_t *tco_settings) |
---|
737 |
{ |
---|
738 |
// Writes the supplied application-level settings to the device's TCO |
---|
739 |
// (Time Code Option). Don't bother doing anything if the device doesn't |
---|
740 |
// have a TCO fitted. Returns 0 on success, -1 on error. |
---|
741 |
|
---|
742 |
quadlet_t tc[4] = {0, 0, 0, 0}; |
---|
743 |
|
---|
744 |
if (!dev_config->tco_present) { |
---|
745 |
return -1; |
---|
746 |
} |
---|
747 |
|
---|
748 |
if (tco_settings->MTC) |
---|
749 |
tc[0] |= FF_TCO0_MTC; |
---|
750 |
|
---|
751 |
switch (tco_settings->input) { |
---|
752 |
case FF_TCOPARAM_INPUT_LTC: |
---|
753 |
tc[2] |= FF_TCO2_INPUT_LTC; break; |
---|
754 |
case FF_TCOPARAM_INPUT_VIDEO: |
---|
755 |
tc[2] |= FF_TCO2_INPUT_VIDEO; break; |
---|
756 |
case FF_TCOPARAM_INPUT_WCK: |
---|
757 |
tc[2] |= FF_TCO2_INPUT_WORD_CLOCK; break; |
---|
758 |
} |
---|
759 |
|
---|
760 |
switch (tco_settings->frame_rate) { |
---|
761 |
case FF_TCOPARAM_FRAMERATE_24fps: |
---|
762 |
tc[1] |= FF_TC01_LTC_FORMAT_24fps; break; |
---|
763 |
case FF_TCOPARAM_FRAMERATE_25fps: |
---|
764 |
tc[1] |= FF_TCO1_LTC_FORMAT_25fps; break; |
---|
765 |
case FF_TCOPARAM_FRAMERATE_29_97fps: |
---|
766 |
tc[1] |= FF_TC01_LTC_FORMAT_29_97fps; break; |
---|
767 |
case FF_TCOPARAM_FRAMERATE_29_97dfps: |
---|
768 |
tc[1] |= FF_TCO1_LTC_FORMAT_29_97dpfs; break; |
---|
769 |
case FF_TCOPARAM_FRAMERATE_30fps: |
---|
770 |
tc[1] |= FF_TCO1_LTC_FORMAT_30fps; break; |
---|
771 |
case FF_TCOPARAM_FRAMERATE_30dfps: |
---|
772 |
tc[1] |= FF_TCO1_LTC_FORMAT_30dfps; break; |
---|
773 |
} |
---|
774 |
|
---|
775 |
switch (tco_settings->word_clock) { |
---|
776 |
case FF_TCOPARAM_WORD_CLOCK_CONV_1_1: |
---|
777 |
tc[2] |= FF_TCO2_WORD_CLOCK_CONV_1_1; break; |
---|
778 |
case FF_TCOPARAM_WORD_CLOCK_CONV_44_48: |
---|
779 |
tc[2] |= FF_TCO2_WORD_CLOCK_CONV_44_48; break; |
---|
780 |
case FF_TCOPARAM_WORD_CLOCK_CONV_48_44: |
---|
781 |
tc[2] |= FF_TCO2_WORD_CLOCK_CONV_48_44; break; |
---|
782 |
} |
---|
783 |
|
---|
784 |
switch (tco_settings->sample_rate) { |
---|
785 |
case FF_TCOPARAM_SRATE_44_1: |
---|
786 |
tc[2] |= FF_TCO2_SRATE_44_1; break; |
---|
787 |
case FF_TCOPARAM_SRATE_48: |
---|
788 |
tc[2] |= FF_TCO2_SRATE_48; break; |
---|
789 |
case FF_TCOPARAM_SRATE_FROM_APP: |
---|
790 |
tc[2] |= FF_TCO2_SRATE_FROM_APP; break; |
---|
791 |
} |
---|
792 |
|
---|
793 |
switch (tco_settings->pull) { |
---|
794 |
case FF_TCOPARAM_PULL_NONE: |
---|
795 |
tc[2] |= FF_TCO2_PULL_0; break; |
---|
796 |
case FF_TCOPARAM_PULL_UP_01: |
---|
797 |
tc[2] |= FF_TCO2_PULL_UP_01; break; |
---|
798 |
case FF_TCOPARAM_PULL_DOWN_01: |
---|
799 |
tc[2] |= FF_TCO2_PULL_DOWN_01; break; |
---|
800 |
case FF_TCOPARAM_PULL_UP_40: |
---|
801 |
tc[2] |= FF_TCO2_PULL_UP_40; break; |
---|
802 |
case FF_TCOPARAM_PULL_DOWN_40: |
---|
803 |
tc[2] |= FF_TCO2_PULL_DOWN_40; break; |
---|
804 |
} |
---|
805 |
|
---|
806 |
if (tco_settings->termination == FF_TCOPARAM_TERMINATION_ON) |
---|
807 |
tc[2] |= FF_TCO2_SET_TERMINATION; |
---|
808 |
|
---|
809 |
return write_tco(tc, 4); |
---|
810 |
} |
---|
811 |
|
---|
812 |
signed int |
---|
813 |
Device::set_hardware_dds_freq(signed int freq) |
---|
814 |
{ |
---|
815 |
// Set the device's DDS to the given frequency (which in turn determines |
---|
816 |
// the sampling frequency). Returns 0 on success, -1 on error. |
---|
817 |
|
---|
818 |
unsigned int ret = 0; |
---|
819 |
|
---|
820 |
if (freq < MIN_SPEED || freq > MAX_SPEED) |
---|
821 |
return -1; |
---|
822 |
|
---|
823 |
switch (m_rme_model) { |
---|
824 |
case RME_MODEL_FIREFACE400: |
---|
825 |
ret = writeRegister(RME_FF400_STREAM_SRATE, freq); break; |
---|
826 |
case RME_MODEL_FIREFACE800: |
---|
827 |
ret = writeRegister(RME_FF800_STREAM_SRATE, freq); break; |
---|
828 |
default: |
---|
829 |
debugOutput(DEBUG_LEVEL_ERROR, "unimplemented model %d\n", m_rme_model); |
---|
830 |
ret = -1; |
---|
831 |
} |
---|
832 |
if (ret == 0) |
---|
833 |
dev_config->hardware_freq = freq; |
---|
834 |
else |
---|
835 |
debugOutput(DEBUG_LEVEL_ERROR, "failed to write DDS register\n"); |
---|
836 |
|
---|
837 |
return ret; |
---|
838 |
} |
---|
839 |
|
---|
840 |
signed int |
---|
841 |
Device::hardware_init_streaming(unsigned int sample_rate, |
---|
842 |
unsigned int tx_channel) |
---|
843 |
{ |
---|
844 |
// tx_channel is the ISO channel the PC will transmit on. |
---|
845 |
quadlet_t buf[5]; |
---|
846 |
fb_nodeaddr_t addr; |
---|
847 |
unsigned int size; |
---|
848 |
signed int ret; |
---|
849 |
|
---|
850 |
debugOutput(DEBUG_LEVEL_VERBOSE, "*** stream init: %d, %d, %d\n", |
---|
851 |
sample_rate, num_channels, tx_channel); |
---|
852 |
|
---|
853 |
buf[0] = sample_rate; |
---|
854 |
buf[1] = (num_channels << 11) + tx_channel; |
---|
855 |
buf[2] = num_channels; |
---|
856 |
buf[3] = 0; |
---|
857 |
buf[4] = 0; |
---|
858 |
if (speed800) { |
---|
859 |
buf[2] |= RME_FF800_STREAMING_SPEED_800; |
---|
860 |
} |
---|
861 |
|
---|
862 |
if (m_rme_model == RME_MODEL_FIREFACE400) { |
---|
863 |
addr = RME_FF400_STREAM_INIT_REG; |
---|
864 |
size = RME_FF400_STREAM_INIT_SIZE; |
---|
865 |
} else |
---|
866 |
if (m_rme_model == RME_MODEL_FIREFACE800) { |
---|
867 |
addr = RME_FF800_STREAM_INIT_REG; |
---|
868 |
size = RME_FF800_STREAM_INIT_SIZE; |
---|
869 |
} else { |
---|
870 |
debugOutput(DEBUG_LEVEL_ERROR, "unimplemented model %d\n", m_rme_model); |
---|
871 |
return -1; |
---|
872 |
} |
---|
873 |
|
---|
874 |
ret = writeBlock(addr, buf, size); |
---|
875 |
if (ret != 0) |
---|
876 |
debugOutput(DEBUG_LEVEL_ERROR, "failed to write streaming parameters\n"); |
---|
877 |
return ret; |
---|
878 |
} |
---|
879 |
|
---|
880 |
signed int |
---|
881 |
Device::hardware_start_streaming(unsigned int listen_channel) |
---|
882 |
{ |
---|
883 |
signed int ret = 0; |
---|
884 |
// Listen_channel is the ISO channel the PC will listen on for data sent |
---|
885 |
// by the Fireface. |
---|
886 |
fb_nodeaddr_t addr; |
---|
887 |
quadlet_t data = num_channels; |
---|
888 |
|
---|
889 |
config_lock(); |
---|
890 |
if (not(hardware_is_streaming())) { |
---|
891 |
debugOutput(DEBUG_LEVEL_VERBOSE,"*** starting: listen=%d, num_ch=%d\n", listen_channel, num_channels); |
---|
892 |
if (m_rme_model == RME_MODEL_FIREFACE400) { |
---|
893 |
addr = RME_FF400_STREAM_START_REG; |
---|
894 |
data |= (listen_channel << 5); |
---|
895 |
} else |
---|
896 |
if (m_rme_model == RME_MODEL_FIREFACE800) { |
---|
897 |
addr = RME_FF800_STREAM_START_REG; |
---|
898 |
if (speed800) |
---|
899 |
data |= RME_FF800_STREAMING_SPEED_800; // Flag 800 Mbps speed |
---|
900 |
} else { |
---|
901 |
debugOutput(DEBUG_LEVEL_ERROR, "unimplemented model %d\n", m_rme_model); |
---|
902 |
return -1; |
---|
903 |
} |
---|
904 |
|
---|
905 |
debugOutput(DEBUG_LEVEL_VERBOSE, "start 0x%016" PRIx64 " data: %08x\n", addr, data); |
---|
906 |
ret = writeRegister(addr, data); |
---|
907 |
debugOutput(DEBUG_LEVEL_VERBOSE, " ret=%d\n", ret); |
---|
908 |
if (ret == 0) { |
---|
909 |
dev_config->is_streaming = 1; |
---|
910 |
} else |
---|
911 |
debugOutput(DEBUG_LEVEL_ERROR, "failed to write for streaming start\n"); |
---|
912 |
|
---|
913 |
set_hardware_channel_mute(-1, 0); |
---|
914 |
|
---|
915 |
} else |
---|
916 |
ret = 0; |
---|
917 |
config_unlock(); |
---|
918 |
|
---|
919 |
return ret; |
---|
920 |
} |
---|
921 |
|
---|
922 |
signed int |
---|
923 |
Device::hardware_stop_streaming(void) |
---|
924 |
{ |
---|
925 |
fb_nodeaddr_t addr; |
---|
926 |
quadlet_t buf[4] = {0, 0, 0, 1}; |
---|
927 |
unsigned int size, ret = 0; |
---|
928 |
|
---|
929 |
config_lock(); |
---|
930 |
if (hardware_is_streaming()) { |
---|
931 |
if (m_rme_model == RME_MODEL_FIREFACE400) { |
---|
932 |
addr = RME_FF400_STREAM_END_REG; |
---|
933 |
size = RME_FF400_STREAM_END_SIZE; |
---|
934 |
} else |
---|
935 |
if (m_rme_model == RME_MODEL_FIREFACE800) { |
---|
936 |
addr = RME_FF800_STREAM_END_REG; |
---|
937 |
size = RME_FF800_STREAM_END_SIZE; |
---|
938 |
} else { |
---|
939 |
debugOutput(DEBUG_LEVEL_ERROR, "unimplemented model %d\n", m_rme_model); |
---|
940 |
return -1; |
---|
941 |
} |
---|
942 |
|
---|
943 |
ret = writeBlock(addr, buf, size); |
---|
944 |
if (ret == 0) { |
---|
945 |
dev_config->is_streaming = 0; |
---|
946 |
} else |
---|
947 |
debugOutput(DEBUG_LEVEL_ERROR, "failed to write for streaming stop\n"); |
---|
948 |
|
---|
949 |
set_hardware_channel_mute(-1, 1); |
---|
950 |
|
---|
951 |
} else |
---|
952 |
ret = 0; |
---|
953 |
config_unlock(); |
---|
954 |
|
---|
955 |
return ret; |
---|
956 |
} |
---|
957 |
|
---|
958 |
signed int |
---|
959 |
Device::set_hardware_ampgain(unsigned int index, signed int val) { |
---|
960 |
// "index" indicates the hardware amplifier gain to set. Values of 0-3 |
---|
961 |
// correspond to input amplifier gains. Values from 4 on relate to output |
---|
962 |
// volume. |
---|
963 |
// |
---|
964 |
// "val" is in dB except for inputs 3/4 where it's in units of 0.5 dB. This |
---|
965 |
// function is responsible for converting to/from the scale used by the |
---|
966 |
// device. |
---|
967 |
// |
---|
968 |
// Only the FF400 has the hardware gain register which is controlled by this |
---|
969 |
// function. |
---|
970 |
quadlet_t regval = 0; |
---|
971 |
signed int devval = 0; |
---|
972 |
signed int ret; |
---|
973 |
if (val > 120) |
---|
974 |
val = 120; |
---|
975 |
if (val < -120) |
---|
976 |
val = -120; |
---|
977 |
if (index <= FF400_AMPGAIN_MIC2) { |
---|
978 |
if (val >= 10) |
---|
979 |
devval = val; |
---|
980 |
else |
---|
981 |
devval = 0; |
---|
982 |
} else |
---|
983 |
if (index <= FF400_AMPGAIN_INPUT4) { |
---|
984 |
devval = val; |
---|
985 |
} else { |
---|
986 |
devval = 6 - val; |
---|
987 |
if (devval > 53) |
---|
988 |
devval = 0x3f; // Mute |
---|
989 |
} |
---|
990 |
regval |= devval; |
---|
991 |
regval |= (index << 16); |
---|
992 |
ret = writeRegister(RME_FF400_GAIN_REG, regval); |
---|
993 |
if (ret != 0) |
---|
994 |
debugOutput(DEBUG_LEVEL_ERROR, "failed to write amp gains\n"); |
---|
995 |
return ret; |
---|
996 |
} |
---|
997 |
|
---|
998 |
signed int |
---|
999 |
Device::set_hardware_mixergain(unsigned int ctype, unsigned int src_channel, |
---|
1000 |
unsigned int dest_channel, signed int val) { |
---|
1001 |
// Set the value of a matrix mixer control. ctype is one of the RME_FF_MM_* |
---|
1002 |
// defines: |
---|
1003 |
// RME_FF_MM_INPUT: source is a physical input |
---|
1004 |
// RME_FF_MM_PLAYBACK: source is playback from PC |
---|
1005 |
// RME_FF_MM_OUTPUT: source is the physical output whose gain is to be |
---|
1006 |
// changed, destination is ignored |
---|
1007 |
// Val is the integer value sent to the device. The amount of gain (in dB) |
---|
1008 |
// applied can be calculated using |
---|
1009 |
// dB = 20.log10(val/32768) |
---|
1010 |
// The maximum value of val is 0x10000, corresponding to +6dB of gain. |
---|
1011 |
// The minimum is 0x00000 corresponding to mute. |
---|
1012 |
|
---|
1013 |
unsigned int n_channels; |
---|
1014 |
signed int ram_output_block_size; |
---|
1015 |
unsigned int ram_addr; |
---|
1016 |
|
---|
1017 |
if (m_rme_model == RME_MODEL_FIREFACE400) { |
---|
1018 |
n_channels = RME_FF400_MAX_CHANNELS; |
---|
1019 |
ram_output_block_size = 0x48; |
---|
1020 |
} else |
---|
1021 |
if (m_rme_model == RME_MODEL_FIREFACE800) { |
---|
1022 |
n_channels = RME_FF800_MAX_CHANNELS; |
---|
1023 |
ram_output_block_size = 0x80; |
---|
1024 |
} else { |
---|
1025 |
debugOutput(DEBUG_LEVEL_ERROR, "unimplemented model %d\n", m_rme_model); |
---|
1026 |
return -1; |
---|
1027 |
} |
---|
1028 |
|
---|
1029 |
if (src_channel>n_channels || dest_channel>n_channels) |
---|
1030 |
return -1; |
---|
1031 |
if (abs(val)>0x10000) |
---|
1032 |
return -1; |
---|
1033 |
|
---|
1034 |
ram_addr = RME_FF_MIXER_RAM; |
---|
1035 |
switch (ctype) { |
---|
1036 |
case RME_FF_MM_INPUT: |
---|
1037 |
case RME_FF_MM_PLAYBACK: |
---|
1038 |
ram_addr += (dest_channel*2*ram_output_block_size) + 4*src_channel; |
---|
1039 |
if (ctype == RME_FF_MM_PLAYBACK) |
---|
1040 |
ram_addr += ram_output_block_size; |
---|
1041 |
break; |
---|
1042 |
case RME_FF_MM_OUTPUT: |
---|
1043 |
if (m_rme_model == RME_MODEL_FIREFACE400) |
---|
1044 |
ram_addr += 0x0f80; |
---|
1045 |
else |
---|
1046 |
ram_addr += 0x1f80; |
---|
1047 |
ram_addr += 4*src_channel; |
---|
1048 |
break; |
---|
1049 |
} |
---|
1050 |
|
---|
1051 |
if (writeRegister(ram_addr, val) != 0) { |
---|
1052 |
debugOutput(DEBUG_LEVEL_ERROR, "failed to write mixer gain element\n"); |
---|
1053 |
} |
---|
1054 |
|
---|
1055 |
// If setting the output volume and the device is the FF400, keep |
---|
1056 |
// the separate gain register in sync. |
---|
1057 |
if (ctype==RME_FF_MM_OUTPUT && m_rme_model==RME_MODEL_FIREFACE400) { |
---|
1058 |
signed int dB; |
---|
1059 |
if (val < 0) |
---|
1060 |
val = -val; |
---|
1061 |
if (val==0) |
---|
1062 |
dB = -90; |
---|
1063 |
else |
---|
1064 |
dB = roundl(20.0*log10(val/32768.0)); |
---|
1065 |
set_hardware_ampgain(FF400_AMPGAIN_OUTPUT1+src_channel, dB); |
---|
1066 |
} |
---|
1067 |
|
---|
1068 |
return 0; |
---|
1069 |
} |
---|
1070 |
|
---|
1071 |
signed int |
---|
1072 |
Device::set_hardware_channel_mute(signed int chan, signed int mute) { |
---|
1073 |
|
---|
1074 |
// Mute hardware channels as instructed. This mute probably relates to the |
---|
1075 |
// sampled input channels as delivered to the PC. If "chan" is -1 the |
---|
1076 |
// supplied "mute" status is applied to all channels. This is the only |
---|
1077 |
// supported "chan" value for now. Down the track, if there's a need, |
---|
1078 |
// this could be extended to allow individual channel control. |
---|
1079 |
quadlet_t buf[28]; |
---|
1080 |
signed int i; |
---|
1081 |
signed int n_channels; |
---|
1082 |
|
---|
1083 |
if (m_rme_model == RME_MODEL_FIREFACE400) |
---|
1084 |
n_channels = RME_FF400_MAX_CHANNELS; |
---|
1085 |
else |
---|
1086 |
if (m_rme_model == RME_MODEL_FIREFACE800) |
---|
1087 |
n_channels = RME_FF800_MAX_CHANNELS; |
---|
1088 |
else { |
---|
1089 |
debugOutput(DEBUG_LEVEL_ERROR, "unimplemented model %d\n", m_rme_model); |
---|
1090 |
return -1; |
---|
1091 |
} |
---|
1092 |
|
---|
1093 |
i = 0; |
---|
1094 |
if (chan < 0) { |
---|
1095 |
while (i<n_channels && i<28) { |
---|
1096 |
buf[i++] = (mute!=0); |
---|
1097 |
} |
---|
1098 |
} else { |
---|
1099 |
return 0; |
---|
1100 |
} |
---|
1101 |
|
---|
1102 |
while (i < 28) { |
---|
1103 |
buf[i++] = 0x00000001; |
---|
1104 |
} |
---|
1105 |
|
---|
1106 |
// Write 28 quadlets even for FF400 |
---|
1107 |
i = writeBlock(RME_FF_CHANNEL_MUTE_MASK, buf, 28); |
---|
1108 |
if (i != 0) |
---|
1109 |
debugOutput(DEBUG_LEVEL_ERROR, "failed to write channel mute\n"); |
---|
1110 |
return i; |
---|
1111 |
} |
---|
1112 |
|
---|
1113 |
signed int |
---|
1114 |
Device::set_hardware_output_rec(signed int rec) { |
---|
1115 |
// Explicitly record (mute!=1) outputs, or not. |
---|
1116 |
// TODO: fill the details in to allow individual outputs to be recorded as |
---|
1117 |
// required. |
---|
1118 |
quadlet_t buf[28]; |
---|
1119 |
signed int i; |
---|
1120 |
|
---|
1121 |
for (i=0; i<28; i++) |
---|
1122 |
buf[i] = (rec!=0); |
---|
1123 |
|
---|
1124 |
// Write 28 quadlets even for FF400 |
---|
1125 |
i = writeBlock(RME_FF_OUTPUT_REC_MASK, buf, 28); |
---|
1126 |
if (i != 0) |
---|
1127 |
debugOutput(DEBUG_LEVEL_ERROR, "failed to write output record flags\n"); |
---|
1128 |
return i; |
---|
1129 |
} |
---|
1130 |
|
---|
1131 |
} |
---|