root/trunk/libffado/src/rme/fireface_hw.cpp

Revision 1698, 31.9 kB (checked in by jwoithe, 14 years ago)

RME: hacks to try to convince the device to start streaming. They didn't work.

Line 
1 /*
2  * Copyright (C) 2009 by Jonathan Woithe
3  *
4  * This file is part of FFADO
5  * FFADO = Free Firewire (pro-)audio drivers for linux
6  *
7  * FFADO is based upon FreeBoB.
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation, either version 2 of the License, or
12  * (at your option) version 3 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23
24 /* This file implements miscellaneous lower-level hardware functions for the Fireface */
25
26 #include <math.h>
27
28 #include "libieee1394/configrom.h"
29 #include "libieee1394/ieee1394service.h"
30
31 #include "rme/rme_avdevice.h"
32 #include "rme/fireface_def.h"
33
34 #include "debugmodule/debugmodule.h"
35
36 namespace Rme {
37
38 unsigned int
39 Device::multiplier_of_freq(unsigned int freq)
40 {
41     if (freq > MIN_QUAD_SPEED)
42       return 4;
43     if (freq > MIN_DOUBLE_SPEED)
44       return 2;
45     return 1;
46 }
47
48 void
49 Device::config_lock(void) {
50     rme_shm_lock(dev_config);
51 }
52
53 void
54 Device::config_unlock(void) {
55     rme_shm_unlock(dev_config);
56 }
57
58 signed int
59 Device::init_hardware(void)
60 {
61     signed int ret = 0;
62     signed int src, dest;
63     signed int n_channels = (m_rme_model==RME_MODEL_FIREFACE400)?
64                    RME_FF400_MAX_CHANNELS:RME_FF800_MAX_CHANNELS;
65     signed int i;
66
67     // Initialises the device's settings structure to a known state and then
68     // sets the hardware to reflect this state.
69
70     config_lock();
71
72     // In time this function may read a cached device setup and initialise
73     // based on that.  It may also read the device configuration from the
74     // device flash and adopt that.  For now (for initial testing purposes)
75     // we'll go with a static state.
76     if (dev_config->settings_valid==0) {
77         memset(settings, 0, sizeof(*settings));
78         settings->spdif_input_mode = FF_SWPARAM_SPDIF_INPUT_COAX;
79         settings->spdif_output_mode = FF_SWPARAM_SPDIF_OUTPUT_COAX;
80         settings->clock_mode = FF_SWPARAM_CLOCK_MODE_MASTER;
81         settings->sync_ref = FF_SWPARAM_SYNCREF_WORDCLOCK;
82         settings->input_level = FF_SWPARAM_ILEVEL_LOGAIN;
83         settings->output_level = FF_SWPARAM_OLEVEL_HIGAIN;
84         settings->phones_level = FF_SWPARAM_PHONESLEVEL_HIGAIN;
85         settings->limit_bandwidth = FF_SWPARAM_BWLIMIT_SEND_ALL_CHANNELS;
86
87         // A default sampling rate.  An explicit DDS frequency is not enabled
88         // by default.
89         dev_config->software_freq = 44100;
90         dev_config->dds_freq = 0;
91
92         // TODO: set input amplifier gains to a value other than 0?
93
94         // TODO: store and set matrix mixer values
95         // TODO: store and manipulate channel mute/rec flags
96
97         // Configure the hardware to match the current software status.
98         // This is only done if the settings valid flag is 0; if it is 1 it
99         // indicates that something has already set the device up to match
100         // the software settings so there's no need to do it again.
101
102         if (set_hardware_params(settings) != 0)
103             ret = -1;
104
105         if (ret==0 && m_rme_model==RME_MODEL_FIREFACE400) {
106             unsigned int node_id = getConfigRom().getNodeId();
107             unsigned int midi_hi_addr;
108             // For now we'll fix this since that's what's done under other
109             // systems.
110             midi_hi_addr = 0x01;
111             if (writeRegister(RME_FF400_MIDI_HIGH_ADDR, (node_id<<16) | midi_hi_addr) != 0)
112                 ret = -1;
113         }
114
115 readRegister(0xfffff0000410LL);
116
117         if (ret==0) {
118             signed freq = dev_config->software_freq;
119             if (dev_config->dds_freq > 0)
120                 freq = dev_config->dds_freq;
121             if (set_hardware_dds_freq(freq) != 0)
122                 ret = -1;
123         }
124
125 for (i=0;i<9;i++)
126   readRegister(0xfffff0000410LL);
127 readRegister(0x801c0000LL);
128
129         if (m_rme_model == RME_MODEL_FIREFACE400) {
130             signed int i;
131             for (i=FF400_AMPGAIN_MIC1; i<=FF400_AMPGAIN_INPUT4; i++) {
132                 set_hardware_ampgain(i, settings->amp_gains[i]);
133             }
134         }
135
136 for (i=0;i<7;i++) {
137   set_hardware_ampgain(FF400_AMPGAIN_MIC1,0);
138   set_hardware_ampgain(FF400_AMPGAIN_MIC2,0);
139 }
140 readRegister(0xfffff0000404LL);
141 readRegister(0x801c0000LL);
142 readRegister(0xfffff0000410LL);
143 readRegister(0x801c0000LL);
144 readRegister(0xfffff0000410LL);
145 readRegister(0xfffff000040cLL);
146 readRegister(0xfffff000040cLL);
147
148         // Matrix mixer settings
149         for (dest=0; dest<n_channels; dest++) {
150             for (src=0; src<n_channels; src++) {
151                 set_hardware_mixergain(RME_FF_MM_INPUT, src, dest, 0);
152 readRegister(0xfffff0000410LL);
153             }
154             for (src=0; src<n_channels; src++) {
155                 set_hardware_mixergain(RME_FF_MM_PLAYBACK, src, dest, 0);
156 readRegister(0xfffff0000410LL);
157             }
158         }
159         for (src=0; src<n_channels; src++) {
160             set_hardware_mixergain(RME_FF_MM_OUTPUT, src, 0, 0);
161 readRegister(0xfffff0000410LL);
162         }
163
164         set_hardware_output_rec(0);
165
166         dev_config->settings_valid = 1;
167     }
168
169
170     // Also configure the TCO (Time Code Option) settings for those devices
171     // which have a TCO.
172     if (ret==0 && dev_config->tco_settings_valid==0) {
173         if (dev_config->tco_present) {
174             memset(tco_settings, 0, sizeof(*tco_settings));
175             write_tco_settings(tco_settings);
176         }
177         dev_config->tco_settings_valid = 1;
178     }
179
180     config_unlock();
181
182     return ret;
183 }
184
185 signed int
186 Device::get_hardware_status(unsigned int *stat0, unsigned int *stat1)
187 {
188     unsigned int buf[2];
189     if (readBlock(RME_FF_STATUS_REG0, buf, 2) != 0)
190         return -1;
191     *stat0 = buf[0];
192     *stat1 = buf[1];
193     return 0;
194 }
195
196 signed int
197 Device::get_hardware_streaming_status(unsigned int *stat, unsigned int n)
198 {
199     // Get the hardware status as it applies to the streaming system.  This
200     // involves a request of 4 quadlets from the status register.  It
201     // appears that the first register's definition is slightly different in
202     // this situation compared to when only 2 quadlets are requested as is
203     // done in get_hardware_status().
204     //
205     // "n" is the size of the passed-in stat array.  It must be >= 4.
206     if (n < 4)
207         return -1;
208     if (readBlock(RME_FF_STATUS_REG0, stat, 4) != 0)
209         return -1;
210     return 0;
211 }
212
213 signed int
214 Device::get_hardware_state(FF_state_t *state)
215 {
216     // Retrieve the hardware status and deduce the device state.  Return
217     // -1 on error, 0 on success.  The given state structure will be
218     // cleared by this call.
219     unsigned int stat0, stat1;
220     memset(state, 0, sizeof(*state));
221     if (get_hardware_status(&stat0, &stat1) != 0)
222         return -1;
223
224     state->is_streaming = dev_config->is_streaming;
225
226     state->clock_mode = (settings->clock_mode == FF_SWPARAM_CLOCK_MODE_MASTER)?FF_STATE_CLOCKMODE_MASTER:FF_STATE_CLOCKMODE_AUTOSYNC;
227
228     switch (stat0 & SR0_AUTOSYNC_SRC_MASK) {
229         case SR0_AUTOSYNC_SRC_ADAT1:
230             state->autosync_source = FF_STATE_AUTOSYNC_SRC_ADAT1;
231             break;
232         case SR0_AUTOSYNC_SRC_ADAT2:
233             state->autosync_source = FF_STATE_AUTOSYNC_SRC_ADAT2;
234             break;
235         case SR0_AUTOSYNC_SRC_SPDIF:
236             state->autosync_source = FF_STATE_AUTOSYNC_SRC_SPDIF;
237             break;
238         case SR0_AUTOSYNC_SRC_WCLK:
239             state->autosync_source = FF_STATE_AUTOSYNC_SRC_WCLK;
240             break;
241         case SR0_AUTOSYNC_SRC_TCO:
242             state->autosync_source = FF_STATE_AUTOSYNC_SRC_TCO;
243             break;
244         default: state->autosync_source = FF_STATE_AUTOSYNC_SRC_NOLOCK;
245     }
246
247     switch (stat0 & SR0_AUTOSYNC_FREQ_MASK) {
248         case SR0_AUTOSYNC_FREQ_32k:  state->autosync_freq = 32000; break;
249         case SR0_AUTOSYNC_FREQ_44k1: state->autosync_freq = 44100; break;
250         case SR0_AUTOSYNC_FREQ_48k:  state->autosync_freq = 48000; break;
251         case SR0_AUTOSYNC_FREQ_64k:  state->autosync_freq = 64000; break;
252         case SR0_AUTOSYNC_FREQ_88k2: state->autosync_freq = 88200; break;
253         case SR0_AUTOSYNC_FREQ_96k:  state->autosync_freq = 96000; break;
254         case SR0_AUTOSYNC_FREQ_128k: state->autosync_freq = 128000; break;
255         case SR0_AUTOSYNC_FREQ_176k4:state->autosync_freq = 176400; break;
256         case SR0_AUTOSYNC_FREQ_192k: state->autosync_freq = 192000; break;
257     }
258
259     switch (stat0 & SR0_SPDIF_FREQ_MASK) {
260         case SR0_SPDIF_FREQ_32k:  state->spdif_freq = 32000; break;
261         case SR0_SPDIF_FREQ_44k1: state->spdif_freq = 41000; break;
262         case SR0_SPDIF_FREQ_48k:  state->spdif_freq = 48000; break;
263         case SR0_SPDIF_FREQ_64k:  state->spdif_freq = 64000; break;
264         case SR0_SPDIF_FREQ_88k2: state->spdif_freq = 88200; break;
265         case SR0_SPDIF_FREQ_96k:  state->spdif_freq = 96000; break;
266         case SR0_SPDIF_FREQ_128k: state->spdif_freq = 128000; break;
267         case SR0_SPDIF_FREQ_176k4:state->spdif_freq = 176400; break;
268         case SR0_SPDIF_FREQ_192k: state->spdif_freq = 192000; break;
269     }
270
271     switch (stat0 & SR0_ADAT1_STATUS_MASK) {
272         case SR0_ADAT1_STATUS_NOLOCK:
273             state->adat1_sync_status = FF_STATE_SYNC_NOLOCK; break;
274         case SR0_ADAT1_STATUS_LOCK:
275             state->adat1_sync_status = FF_STATE_SYNC_LOCKED; break;
276         case SR0_ADAT1_STATUS_SYNC:
277             state->adat1_sync_status = FF_STATE_SYNC_SYNCED; break;
278     }
279     switch (stat0 & SR0_ADAT2_STATUS_MASK) {
280         case SR0_ADAT2_STATUS_NOLOCK:
281             state->adat2_sync_status = FF_STATE_SYNC_NOLOCK; break;
282         case SR0_ADAT2_STATUS_LOCK:
283             state->adat2_sync_status = FF_STATE_SYNC_LOCKED; break;
284         case SR0_ADAT2_STATUS_SYNC:
285             state->adat2_sync_status = FF_STATE_SYNC_SYNCED; break;
286     }
287     switch (stat0 & SR0_SPDIF_STATUS_MASK) {
288         case SR0_SPDIF_STATUS_NOLOCK:
289             state->spdif_sync_status = FF_STATE_SYNC_NOLOCK; break;
290         case SR0_SPDIF_STATUS_LOCK:
291             state->spdif_sync_status = FF_STATE_SYNC_LOCKED; break;
292         case SR0_SPDIF_STATUS_SYNC:
293             state->spdif_sync_status = FF_STATE_SYNC_SYNCED; break;
294     }
295     switch (stat0 & SR0_WCLK_STATUS_MASK) {
296         case SR0_WCLK_STATUS_NOLOCK:
297             state->wclk_sync_status = FF_STATE_SYNC_NOLOCK; break;
298         case SR0_WCLK_STATUS_LOCK:
299             state->wclk_sync_status = FF_STATE_SYNC_LOCKED; break;
300         case SR0_WCLK_STATUS_SYNC:
301             state->wclk_sync_status = FF_STATE_SYNC_SYNCED; break;
302     }
303     switch (stat1 & SR1_TCO_STATUS_MASK) {
304        case SR1_TCO_STATUS_NOLOCK:
305            state->tco_sync_status = FF_STATE_SYNC_NOLOCK; break;
306        case SR1_TCO_STATUS_LOCK:
307            state->tco_sync_status = FF_STATE_SYNC_LOCKED; break;
308        case SR1_TCO_STATUS_SYNC:
309            state->tco_sync_status = FF_STATE_SYNC_SYNCED; break;
310     }
311
312     return 0;
313 }
314
315 signed int
316 Device::set_hardware_params(FF_software_settings_t *use_settings)
317 {
318     // Initialises the hardware to the state defined by the supplied
319     // software settings structure (which will usually be the device's
320     // "settings" structure).  This has the side effect of extinguishing the
321     // "Host" LED on the FF400 when done for the first time after the
322     // interface has been powered up.
323     //
324     // If use_settings is NULL, the device's current settings structure will
325     // be used to source the configuration information.
326
327     FF_software_settings_t *sw_settings;
328     quadlet_t data[3] = {0, 0, 0};
329     unsigned int conf_reg;
330
331     if (use_settings == NULL)
332       sw_settings = settings;
333     else
334       sw_settings = use_settings;
335
336     if (sw_settings->mic_phantom[0])
337       data[0] |= CR0_PHANTOM_MIC0;
338     if (sw_settings->mic_phantom[1])
339       data[0] |= CR0_PHANTOM_MIC1;
340     if (m_rme_model == RME_MODEL_FIREFACE800) {
341         if (sw_settings->mic_phantom[2])
342             data[0] |= CR0_FF800_PHANTOM_MIC9;
343         if (sw_settings->mic_phantom[3])
344             data[0] |= CR0_FF800_PHANTOM_MIC10;
345     } else {
346         if (sw_settings->ff400_input_pad[0])
347             data[0] |= CR0_FF400_CH3_PAD;
348         if (sw_settings->ff400_input_pad[1])
349             data[0] |= CR0_FF400_CH4_PAD;
350     }
351
352     /* Phones level */
353     switch (sw_settings->phones_level) {
354         case FF_SWPARAM_PHONESLEVEL_HIGAIN:
355             data[0] |= CRO_PHLEVEL_HIGAIN;
356             break;
357         case FF_SWPARAM_PHONESLEVEL_4dBU:
358             data[0] |= CR0_PHLEVEL_4dBU;
359             break;
360         case FF_SWPARAM_PHONESLEVEL_m10dBV:
361             data[0] |= CRO_PHLEVEL_m10dBV;
362             break;
363     }
364
365     /* Input level */
366     switch (sw_settings->input_level) {
367         case FF_SWPARAM_ILEVEL_LOGAIN: // Low gain
368             data[1] |= CR1_ILEVEL_CPLD_LOGAIN;    // CPLD
369             data[0] |= CR0_ILEVEL_FPGA_LOGAIN;    // LED control (used on FF800 only)
370             break;
371         case FF_SWPARAM_ILEVEL_4dBU:   // +4 dBu
372             data[1] |= CR1_ILEVEL_CPLD_4dBU;
373             data[0] |= CR0_ILEVEL_FPGA_4dBU;
374             break;
375         case FF_SWPARAM_ILEVEL_m10dBV: // -10 dBV
376             data[1] |= CR1_ILEVEL_CPLD_m10dBV;
377             data[0] |= CR0_ILEVEL_FPGA_m10dBV;
378             break;
379     }
380
381     /* Output level */
382     switch (sw_settings->output_level) {
383         case FF_SWPARAM_OLEVEL_HIGAIN: // High gain
384             data[1] |= CR1_OLEVEL_CPLD_HIGAIN;   // CPLD
385             data[0] |= CR0_OLEVEL_FPGA_HIGAIN;   // LED control (used on FF800 only)
386             break;
387         case FF_SWPARAM_OLEVEL_4dBU:   // +4 dBu
388             data[1] |= CR1_OLEVEL_CPLD_4dBU;
389             data[0] |= CR0_OLEVEL_FPGA_4dBU;
390             break;
391         case FF_SWPARAM_OLEVEL_m10dBV: // -10 dBV
392             data[1] |= CR1_OLEVEL_CPLD_m10dBV;
393             data[0] |= CR0_OLEVEL_FPGA_m10dBV;
394             break;
395     }
396
397     /* Set input options.  The meaning of the options differs between
398      * devices, so we use the generic identifiers here.
399      */
400     data[1] |= (sw_settings->input_opt[1] & FF_SWPARAM_INPUT_OPT_A) ? CR1_INPUT_OPT1_A : 0;
401     data[1] |= (sw_settings->input_opt[1] & FF_SWPARAM_INPUT_OPT_B) ? CR1_INPUT_OPT1_B : 0;
402     data[1] |= (sw_settings->input_opt[2] & FF_SWPARAM_INPUT_OPT_A) ? CR1_INPUT_OPT2_A : 0;
403     data[1] |= (sw_settings->input_opt[2] & FF_SWPARAM_INPUT_OPT_B) ? CR1_INPUT_OPT2_B : 0;
404
405     // Drive the speaker emulation / filter LED via FPGA in FF800.  In FF400
406     // the same bit controls the channel 4 "instrument" option.
407     if (m_rme_model == RME_MODEL_FIREFACE800) {
408         data[0] |= (sw_settings->filter) ? CR0_FF800_FILTER_FPGA : 0;
409     } else {
410         data[0] |= (sw_settings->ff400_instr_input[1]) ? CR0_FF400_CH4_INSTR : 0;
411     }
412
413     // Set the "rear" option for input 0 if selected
414     data[1] |= (sw_settings->input_opt[0] & FF_SWPARAM_FF800_INPUT_OPT_REAR) ? CR1_FF800_INPUT1_REAR : 0;
415
416     // The input 0 "front" option is activated using one of two bits
417     // depending on whether the filter (aka "speaker emulation") setting is
418     // active.
419     if (sw_settings->input_opt[0] & FF_SWPARAM_FF800_INPUT_OPT_FRONT) {
420         data[1] |= (sw_settings->filter) ? CR1_FF800_INPUT1_FRONT_WITH_FILTER : CR1_FF800_INPUT1_FRONT;
421     }
422
423     data[2] |= (sw_settings->spdif_output_emphasis==FF_SWPARAM_SPDIF_OUTPUT_EMPHASIS_ON) ? CR2_SPDIF_OUT_EMP : 0;
424     data[2] |= (sw_settings->spdif_output_pro==FF_SWPARAM_SPDIF_OUTPUT_PRO_ON) ? CR2_SPDIF_OUT_PRO : 0;
425     data[2] |= (sw_settings->spdif_output_nonaudio==FF_SWPARAM_SPDIF_OUTPUT_NONAUDIO_ON) ? CR2_SPDIF_OUT_NONAUDIO : 0;
426     data[2] |= (sw_settings->spdif_output_mode==FF_SWPARAM_SPDIF_OUTPUT_OPTICAL) ? CR2_SPDIF_OUT_ADAT2 : 0;
427     data[2] |= (sw_settings->clock_mode==FF_SWPARAM_CLOCK_MODE_AUTOSYNC) ? CR2_CLOCKMODE_AUTOSYNC : CR2_CLOCKMODE_MASTER;
428     data[2] |= (sw_settings->spdif_input_mode==FF_SWPARAM_SPDIF_INPUT_COAX) ? CR2_SPDIF_IN_COAX : CR2_SPDIF_IN_ADAT2;
429     data[2] |= (sw_settings->word_clock_single_speed=FF_SWPARAM_WORD_CLOCK_1x) ? CR2_WORD_CLOCK_1x : 0;
430
431     /* TMS / TCO toggle bits in CR2 are not set by other drivers */
432
433     /* Drive / fuzz in FF800.  In FF400, the CR0 bit used by "Drive" controls
434      * the channel 3 "instrument" option.
435      */
436     if (m_rme_model == RME_MODEL_FIREFACE800) {
437         if (sw_settings->fuzz)
438             data[0] |= CR0_FF800_DRIVE_FPGA; // FPGA LED control
439         else
440             data[1] |= CR1_INSTR_DRIVE;      // CPLD
441     } else {
442         data[0] |= (sw_settings->ff400_instr_input[0]) ? CR0_FF400_CH3_INSTR : 0;
443     }
444
445     /* Drop-and-stop is hardwired on in other drivers */
446     data[2] |= CR2_DROP_AND_STOP;
447
448     if (m_rme_model == RME_MODEL_FIREFACE400) {
449         data[2] |= CR2_FF400_BIT;
450     }
451
452     switch (sw_settings->sync_ref) {
453         case FF_SWPARAM_SYNCREF_WORDCLOCK:
454             data[2] |= CR2_SYNC_WORDCLOCK;
455             break;
456         case FF_SWPARAM_SYNCREF_ADAT1:
457             data[2] |= CR2_SYNC_ADAT1;
458             break;
459         case FF_SWPARAM_SYNCREF_ADAT2:
460             data[2] |= CR2_SYNC_ADAT2;
461             break;
462         case FF_SWPARAM_SYNCREF_SPDIF:
463             data[2] |= CR2_SYNC_SPDIF;
464             break;
465         case FF_SWPARAM_SYNCREC_TCO:
466             data[2] |= CR2_SYNC_TCO;
467             break;
468     }
469
470     // This is hardwired in other drivers
471     data[2] |= (CR2_FREQ0 + CR2_FREQ1 + CR2_DSPEED + CR2_QSSPEED);
472
473     // The FF800 limiter applies to the front panel instrument input, so it
474     // only makes sense that it is disabled when that input is in use.
475     data[2] |= (sw_settings->limiter_disable &&
476                 (sw_settings->input_opt[0] & FF_SWPARAM_FF800_INPUT_OPT_FRONT)) ?
477                 CR2_DISABLE_LIMITER : 0;
478
479 //This is just for testing - it's a known consistent configuration
480 //data[0] = 0x00020810;      // Phantom off
481 //data[0] = 0x00020811;      // Phantom on
482 //data[1] = 0x0000031e;
483 //data[2] = 0xc400101f;
484     debugOutput(DEBUG_LEVEL_VERBOSE, "set hardware registers: 0x%08x 0x%08x 0x%08x\n",
485       data[0], data[1], data[2]);
486
487     conf_reg = (m_rme_model==RME_MODEL_FIREFACE800)?RME_FF800_CONF_REG:RME_FF400_CONF_REG;
488     if (writeBlock(conf_reg, data, 3) != 0)
489         return -1;
490
491     return 0;
492 }
493
494 signed int
495 Device::read_tco(quadlet_t *tco_data, signed int size)
496 {
497     // Read the TCO registers and return the respective values in *tco_data.
498     // Return value is 0 on success, or -1 if there is no TCO present.
499     // "size" is the size (in quadlets) of the array pointed to by tco_data.
500     // To obtain all TCO data "size" should be at least 4.  If the caller
501     // doesn't care about the data returned by the TCO, tco_data can be
502     // NULL.
503     quadlet_t buf[4];
504     signed int i;
505
506     // The Fireface 400 can't have the TCO fitted
507     if (m_rme_model==RME_MODEL_FIREFACE400)
508         return -1;
509
510     if (readBlock(RME_FF_TCO_READ_REG, buf, 4) != 0)
511         return -1;
512
513     if (tco_data != NULL) {
514         for (i=0; i<(size<4)?size:4; i++)
515             tco_data[i] = buf[i];
516     }
517
518     if ( (buf[0] & 0x80808080) == 0x80808080 &&
519          (buf[1] & 0x80808080) == 0x80808080 &&
520          (buf[2] & 0x80808080) == 0x80808080 &&
521          (buf[3] & 0x8000FFFF) == 0x80008000) {
522         // A TCO is present
523         return 0;
524     }
525
526     return -1;
527 }
528
529 signed int
530 Device::write_tco(quadlet_t *tco_data, signed int size)
531 {
532     // Writes data to the TCO.  No check is made as to whether a TCO is
533     // present in the current device.  Return value is 0 on success or -1 on
534     // error.  "size" is the size (in quadlets) of the data pointed to by
535     // "tco_data".  The first 4 quadlets of tco_data are significant; all
536     // others are ignored.  If fewer than 4 quadlets are supplied (as
537     // indicated by the "size" parameter, -1 will be returned.
538     if (size < 4)
539         return -1;
540
541     // Don't bother trying to write if the device is a FF400 since the TCO
542     // can't be fitted to this device.
543     if (m_rme_model==RME_MODEL_FIREFACE400)
544         return -1;
545
546     if (writeBlock(RME_FF_TCO_WRITE_REG, tco_data, 4) != 0)
547         return -1;
548
549     return 0;
550 }
551
552 signed int
553 Device::hardware_is_streaming(void)
554 {
555     // Return 1 if the hardware is streaming, 0 if not.
556     return dev_config->is_streaming;
557 }
558
559 signed int
560 Device::read_tco_state(FF_TCO_state_t *tco_state)
561 {
562     // Reads the current TCO state into the supplied state structure
563
564     quadlet_t tc[4];
565     unsigned int PLL_phase;
566
567     if (read_tco(tc, 4) != 0)
568       return -1;
569
570     // The timecode is stored in BCD (binary coded decimal) in register 0.
571     tco_state->frames = (tc[0] & 0xf) + ((tc[0] & 0x30) >> 4)*10;
572     tco_state->seconds = ((tc[0] & 0xf00) >> 8) + ((tc[0] & 0x7000) >> 12)*10;
573     tco_state->minutes = ((tc[0] & 0xf0000) >> 16) + ((tc[0] & 0x700000) >> 20)*10;
574     tco_state->hours = ((tc[0] & 0xf000000) >> 24) + ((tc[0] & 0x30000000) >> 28)*10;
575
576     tco_state->locked = (tc[1] & FF_TCO1_TCO_lock) != 0;
577     tco_state->ltc_valid = (tc[1] & FF_TCO1_LTC_INPUT_VALID) != 0;
578
579     switch (tc[1] & FF_TCO1_LTC_FORMAT_MASK) {
580         case FF_TC01_LTC_FORMAT_24fps:
581           tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_24fps; break;
582         case FF_TCO1_LTC_FORMAT_25fps:
583           tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_25fps; break;
584         case FF_TC01_LTC_FORMAT_29_97fps:
585           tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_29_97fps; break;
586         case FF_TCO1_LTC_FORMAT_30fps:
587           tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_30fps; break;
588     }
589
590     tco_state->drop_frame = (tc[1] & FF_TCO1_SET_DROPFRAME) != 0;
591
592     switch (tc[1] & FF_TCO1_VIDEO_INPUT_MASK) {
593         case FF_TCO1_VIDEO_INPUT_NTSC:
594             tco_state->video_input = FF_TCOSTATE_VIDEO_NTSC; break;
595         case FF_TCO1_VIDEO_INPUT_PAL:
596             tco_state->video_input = FF_TCOSTATE_VIDEO_PAL; break;
597         default:
598             tco_state->video_input = FF_TCOSTATE_VIDEO_NONE;
599     }
600
601     if ((tc[1] & FF_TCO1_WORD_CLOCK_INPUT_VALID) == 0) {
602         tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_NONE;
603     } else {
604         switch (tc[1] & FF_TCO1_WORD_CLOCK_INPUT_MASK) {
605             case FF_TCO1_WORD_CLOCK_INPUT_1x:
606                 tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_1x; break;
607             case FF_TCO1_WORD_CLOCK_INPUT_2x:
608                 tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_2x; break;
609             case FF_TCO1_WORD_CLOCK_INPUT_4x:
610                 tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_4x; break;
611         }
612     }
613
614     PLL_phase = (tc[2] & 0x7f) + ((tc[2] & 0x7f00) >> 1);
615     tco_state->sample_rate = (25000000.0 * 16.0)/PLL_phase;
616
617     return 0;
618 }
619
620 signed int
621 Device::write_tco_settings(FF_TCO_settings_t *tco_settings)
622 {
623     // Writes the supplied application-level settings to the device's TCO
624     // (Time Code Option).  Don't bother doing anything if the device doesn't
625     // have a TCO fitted.  Returns 0 on success, -1 on error.
626
627     quadlet_t tc[4] = {0, 0, 0, 0};
628
629     if (!dev_config->tco_present) {
630         return -1;
631     }
632
633     if (tco_settings->MTC)
634         tc[0] |= FF_TCO0_MTC;
635
636     switch (tco_settings->input) {
637         case FF_TCOPARAM_INPUT_LTC:
638             tc[2] |= FF_TCO2_INPUT_LTC; break;
639         case FF_TCOPARAM_INPUT_VIDEO:
640             tc[2] |= FF_TCO2_INPUT_VIDEO; break;
641         case FF_TCOPARAM_INPUT_WCK:
642             tc[2] |= FF_TCO2_INPUT_WORD_CLOCK; break;
643     }
644
645     switch (tco_settings->frame_rate) {
646         case FF_TCOPARAM_FRAMERATE_24fps:
647             tc[1] |= FF_TC01_LTC_FORMAT_24fps; break;
648         case FF_TCOPARAM_FRAMERATE_25fps:
649             tc[1] |= FF_TCO1_LTC_FORMAT_25fps; break;
650         case FF_TCOPARAM_FRAMERATE_29_97fps:
651             tc[1] |= FF_TC01_LTC_FORMAT_29_97fps; break;
652         case FF_TCOPARAM_FRAMERATE_29_97dfps:
653             tc[1] |= FF_TCO1_LTC_FORMAT_29_97dpfs; break;
654         case FF_TCOPARAM_FRAMERATE_30fps:
655             tc[1] |= FF_TCO1_LTC_FORMAT_30fps; break;
656         case FF_TCOPARAM_FRAMERATE_30dfps:
657             tc[1] |= FF_TCO1_LTC_FORMAT_30dfps; break;
658     }
659
660     switch (tco_settings->word_clock) {
661         case FF_TCOPARAM_WORD_CLOCK_CONV_1_1:
662             tc[2] |= FF_TCO2_WORD_CLOCK_CONV_1_1; break;
663         case FF_TCOPARAM_WORD_CLOCK_CONV_44_48:
664             tc[2] |= FF_TCO2_WORD_CLOCK_CONV_44_48; break;
665         case FF_TCOPARAM_WORD_CLOCK_CONV_48_44:
666             tc[2] |= FF_TCO2_WORD_CLOCK_CONV_48_44; break;
667     }
668
669     switch (tco_settings->sample_rate) {
670         case FF_TCOPARAM_SRATE_44_1:
671             tc[2] |= FF_TCO2_SRATE_44_1; break;
672         case FF_TCOPARAM_SRATE_48:
673             tc[2] |= FF_TCO2_SRATE_48; break;
674         case FF_TCOPARAM_SRATE_FROM_APP:
675             tc[2] |= FF_TCO2_SRATE_FROM_APP; break;
676     }
677
678     switch (tco_settings->pull) {
679         case FF_TCPPARAM_PULL_NONE:
680             tc[2] |= FF_TCO2_PULL_0; break;
681         case FF_TCOPARAM_PULL_UP_01:
682             tc[2] |= FF_TCO2_PULL_UP_01; break;
683         case FF_TCOPARAM_PULL_DOWN_01:
684             tc[2] |= FF_TCO2_PULL_DOWN_01; break;
685         case FF_TCOPARAM_PULL_UP_40:
686             tc[2] |= FF_TCO2_PULL_UP_40; break;
687         case FF_TCOPARAM_PULL_DOWN_40:
688             tc[2] |= FF_TCO2_PULL_DOWN_40; break;
689     }
690
691     if (tco_settings->termination == FF_TCOPARAM_TERMINATION_ON)
692         tc[2] |= FF_TCO2_SET_TERMINATION;
693
694     return write_tco(tc, 4);
695 }
696
697 signed int
698 Device::set_hardware_dds_freq(signed int freq)
699 {
700     // Set the device's DDS to the given frequency (which in turn determines
701     // the sampling frequency).  Returns 0 on success, -1 on error.
702
703     unsigned int ret = 0;
704
705     if (freq < MIN_SPEED || freq > MAX_SPEED)
706         return -1;
707
708     if (m_rme_model == RME_MODEL_FIREFACE400)
709         ret = writeRegister(RME_FF400_STREAM_SRATE, freq);
710     else
711         ret = writeRegister(RME_FF800_STREAM_SRATE, freq);
712
713     if (ret == 0)
714         dev_config->hardware_freq = freq;
715
716     return ret;
717 }
718
719 signed int
720 Device::hardware_init_streaming(unsigned int sample_rate,
721     unsigned int tx_channel)
722 {
723     // tx_channel is the ISO channel the PC will transmit on.
724     quadlet_t buf[5];
725     fb_nodeaddr_t addr;
726     unsigned int size;
727
728 debugOutput(DEBUG_LEVEL_VERBOSE, "*** stream init: %d, %d, %d\n",
729   sample_rate, num_channels, tx_channel);
730
731     buf[0] = sample_rate;
732     buf[1] = (num_channels << 11) + tx_channel;
733     buf[2] = num_channels;
734     buf[3] = 0;
735     buf[4] = 0;
736     if (speed800) {
737         buf[2] |= RME_FF800_STREAMING_SPEED_800;
738     }
739
740     if (m_rme_model == RME_MODEL_FIREFACE400) {
741         addr = RME_FF400_STREAM_INIT_REG;
742         size = RME_FF400_STREAM_INIT_SIZE;
743     } else {
744         addr = RME_FF800_STREAM_INIT_REG;
745         size = RME_FF800_STREAM_INIT_SIZE;
746     }
747
748 {signed int i;
749   printf("addr %016llx\n", addr);
750   for (i=0; i<5; i++)
751     printf("0x%08x ", buf[i]);
752   printf("\n");
753 }
754
755 readRegister(0xfffff000040cLL);
756 readRegister(0xfffff000040cLL);
757 readRegister(0xfffff000040cLL);
758
759     return writeBlock(addr, buf, size);
760 }
761
762 signed int
763 Device::hardware_start_streaming(unsigned int listen_channel)
764 {
765     signed int ret = 0;
766     // Listen_channel is the ISO channel the PC will listen on for data sent
767     // by the Fireface.
768     fb_nodeaddr_t addr;
769     quadlet_t data = num_channels;
770
771     config_lock();
772     if (not(hardware_is_streaming())) {
773 debugOutput(DEBUG_LEVEL_VERBOSE,"*** starting: listen=%d, num_ch=%d\n", listen_channel, num_channels);
774         if (m_rme_model == RME_MODEL_FIREFACE400) {
775             addr = RME_FF400_STREAM_START_REG;
776             data |= (listen_channel << 5);
777         } else {
778             addr = RME_FF800_STREAM_START_REG;
779             if (speed800)
780                 data |= RME_FF800_STREAMING_SPEED_800; // Flag 800 Mbps speed
781         }
782
783 readRegister(0x801c0000LL);
784
785 printf("start 0x%016llx data: %08x\n", addr, data);
786         ret = writeRegister(addr, data);
787         if (ret == 0) {
788             dev_config->is_streaming = 1;
789         }
790
791         set_hardware_channel_mute(0);
792
793     } else
794         ret = -1;
795     config_unlock();
796
797     return ret;
798 }
799
800 signed int
801 Device::hardware_stop_streaming(void)
802 {
803     fb_nodeaddr_t addr;
804     quadlet_t buf[4] = {0, 0, 0, 1};
805     unsigned int size, ret = 0;
806
807     config_lock();
808     if (hardware_is_streaming()) {
809         if (m_rme_model == RME_MODEL_FIREFACE400) {
810             addr = RME_FF400_STREAM_END_REG;
811             size = RME_FF400_STREAM_END_SIZE;
812         } else {
813             addr = RME_FF800_STREAM_END_REG;
814             size = RME_FF800_STREAM_END_SIZE;
815         }
816
817         ret = writeBlock(addr, buf, size);
818         if (ret == 0) {
819             dev_config->is_streaming = 0;
820         }
821
822         set_hardware_channel_mute(1);
823
824     } else
825         ret = -1;
826     config_unlock();
827
828     return ret;
829 }
830
831 signed int
832 Device::set_hardware_ampgain(unsigned int index, signed int val) {
833 // "index" indicates the hardware amplifier gain to set.  Values of 0-3
834 // correspond to input amplifier gains.  Values from 4 on relate to output
835 // volume.
836 //
837 // "val" is in dB except for inputs 3/4 where it's in units of 0.5 dB. This
838 // function is responsible for converting to/from the scale used by the
839 // device.
840 //
841 // Only the FF400 has the hardware gain register which is controlled by this
842 // function.
843     quadlet_t regval = 0;
844     signed int devval = 0;
845     if (val > 120)
846       val = 120;
847     if (val < -120)
848       val = -120;
849     if (index <= FF400_AMPGAIN_MIC2) {
850         if (val >= 10)
851             devval = val;
852         else
853             devval = 0;
854     } else
855     if (index <= FF400_AMPGAIN_INPUT4) {
856         devval = val;
857     } else {
858         devval = 6 - val;
859         if (devval > 53)
860             devval = 0x3f;  // Mute
861     }
862     regval |= devval;
863     regval |= (index << 16);
864     return writeRegister(RME_FF400_GAIN_REG, regval);
865 }
866
867 signed int
868 Device::set_hardware_mixergain(unsigned int ctype, unsigned int src_channel,
869   unsigned int dest_channel, signed int val) {
870 // Set the value of a matrix mixer control.  ctype is one of the RME_FF_MM_*
871 // defines:
872 //   RME_FF_MM_INPUT: source is a physical input
873 //   RME_FF_MM_PLAYBACK: source is playback from PC
874 //   RME_FF_MM_OUTPUT: source is the physical output whose gain is to be
875 //     changed, destination is ignored
876 // Val is the integer value sent to the device.  The amount of gain (in dB)
877 // applied can be calculated using
878 //   dB = 20.log10(val/32768)
879 // The maximum value of val is 0x10000, corresponding to +6dB of gain.
880 // The minimum is 0x00000 corresponding to mute.
881
882     unsigned int n_channels;
883     signed int ram_output_block_size;
884     unsigned int ram_addr;
885
886     n_channels = (m_rme_model==RME_MODEL_FIREFACE400)?
887         RME_FF400_MAX_CHANNELS:RME_FF800_MAX_CHANNELS;
888     if (src_channel>n_channels || dest_channel>n_channels)
889         return -1;
890     if (val<0 || val>0x10000)
891         return -1;
892
893     if (m_rme_model == RME_MODEL_FIREFACE400) {
894         ram_output_block_size = 0x48;
895     } else {
896         ram_output_block_size = 0x80;
897     }
898
899     ram_addr = RME_FF_MIXER_RAM;
900     switch (ctype) {
901         case RME_FF_MM_INPUT:
902         case RME_FF_MM_PLAYBACK:
903             ram_addr += (dest_channel*2*ram_output_block_size) + 4*src_channel;
904             if (ctype == RME_FF_MM_PLAYBACK)
905                  ram_addr += ram_output_block_size;
906             break;
907         case RME_FF_MM_OUTPUT:
908             ram_addr += 0x0f80 + 4*src_channel;
909             break;
910     }
911     writeRegister(ram_addr, val);
912
913     // If setting the output volume and the device is the FF400, keep
914     // the separate gain register in sync.
915     if (ctype==RME_FF_MM_OUTPUT && m_rme_model==RME_MODEL_FIREFACE400) {
916         signed int dB;
917         if (val==0)
918             dB = -90;
919         else
920             dB = roundl(20.0*log10(val/32768.0));
921         set_hardware_ampgain(FF400_AMPGAIN_OUTPUT1+src_channel, dB);
922     }
923
924     return 0;
925 }
926
927 signed int
928 Device::set_hardware_channel_mute(signed int mute) {
929 // Explicitly mute (mute!=0) or unmute (mute=0) all channels.
930 // TODO: fill the details in to allow individual channels to be muted as
931 // required.
932     quadlet_t buf[28];
933     signed int i;
934
935     for (i=0; i<28; i++)
936         buf[i] = (mute!=0);
937
938     // Write 28 quadlets even for FF400
939     return writeBlock(RME_FF_CHANNEL_MUTE_MASK, buf, 28);
940 }
941
942 signed int
943 Device::set_hardware_output_rec(signed int rec) {
944 // Explicitly record (mute!=1) outputs, or not.
945 // TODO: fill the details in to allow individual outputs to be recorded as
946 // required.
947     quadlet_t buf[28];
948     signed int i;
949
950     for (i=0; i<28; i++)
951         buf[i] = (rec!=0);
952
953     // Write 28 quadlets even for FF400
954     return writeBlock(RME_FF_OUTPUT_REC_MASK, buf, 28);
955 }
956
957 }
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