root/trunk/libffado/src/rme/fireface_hw.cpp

Revision 2016, 32.0 kB (checked in by jwoithe, 9 years ago)

rme: refine mute hardware mute controls. Add mute support for mixer outputs. Create dbus mixer objects to control channel muting and inversion.
matrixmixer: prepare infrastructure to allow channel muting to be controlled if enabled by the caller.

Line 
1 /*
2  * Copyright (C) 2009 by Jonathan Woithe
3  *
4  * This file is part of FFADO
5  * FFADO = Free Firewire (pro-)audio drivers for linux
6  *
7  * FFADO is based upon FreeBoB.
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation, either version 2 of the License, or
12  * (at your option) version 3 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23
24 /* This file implements miscellaneous lower-level hardware functions for the Fireface */
25
26 #include <math.h>
27
28 #include "libieee1394/configrom.h"
29 #include "libieee1394/ieee1394service.h"
30
31 #include "rme/rme_avdevice.h"
32 #include "rme/fireface_def.h"
33
34 #include "debugmodule/debugmodule.h"
35
36 namespace Rme {
37
38 unsigned int
39 Device::multiplier_of_freq(unsigned int freq)
40 {
41     if (freq > MIN_QUAD_SPEED)
42       return 4;
43     if (freq > MIN_DOUBLE_SPEED)
44       return 2;
45     return 1;
46 }
47
48 void
49 Device::config_lock(void) {
50     rme_shm_lock(dev_config);
51 }
52
53 void
54 Device::config_unlock(void) {
55     rme_shm_unlock(dev_config);
56 }
57
58 signed int
59 Device::init_hardware(void)
60 {
61     signed int ret = 0;
62     signed int src, dest;
63     signed int n_channels = (m_rme_model==RME_MODEL_FIREFACE400)?
64                    RME_FF400_MAX_CHANNELS:RME_FF800_MAX_CHANNELS;
65
66     // Initialises the device's settings structure to a known state and then
67     // sets the hardware to reflect this state.
68
69     config_lock();
70
71     // In time this function may read a cached device setup and initialise
72     // based on that.  It may also read the device configuration from the
73     // device flash and adopt that.  For now (for initial testing purposes)
74     // we'll go with a static state.
75     if (dev_config->settings_valid==0) {
76         memset(settings, 0, sizeof(*settings));
77         settings->spdif_input_mode = FF_SWPARAM_SPDIF_INPUT_COAX;
78         settings->spdif_output_mode = FF_SWPARAM_SPDIF_OUTPUT_COAX;
79         settings->clock_mode = FF_SWPARAM_CLOCK_MODE_MASTER;
80         settings->sync_ref = FF_SWPARAM_SYNCREF_WORDCLOCK;
81         settings->input_level = FF_SWPARAM_ILEVEL_LOGAIN;
82         settings->output_level = FF_SWPARAM_OLEVEL_HIGAIN;
83         settings->phones_level = FF_SWPARAM_PHONESLEVEL_HIGAIN;
84         settings->limit_bandwidth = FF_SWPARAM_BWLIMIT_SEND_ALL_CHANNELS;
85
86         // A default sampling rate.  An explicit DDS frequency is not enabled
87         // by default.
88         dev_config->software_freq = 44100;
89         dev_config->dds_freq = 0;
90
91         // TODO: set input amplifier gains to a value other than 0?
92
93         // TODO: store and set matrix mixer values
94         // TODO: store and manipulate channel mute/rec flags
95
96         // Configure the hardware to match the current software status.
97         // This is only done if the settings valid flag is 0; if it is 1 it
98         // indicates that something has already set the device up to match
99         // the software settings so there's no need to do it again.
100
101         if (set_hardware_params(settings) != 0)
102             ret = -1;
103
104         if (ret==0 && m_rme_model==RME_MODEL_FIREFACE400) {
105             unsigned int node_id = getConfigRom().getNodeId();
106             unsigned int midi_hi_addr;
107             // For now we'll fix this since that's what's done under other
108             // systems.
109             midi_hi_addr = 0x01;
110             if (writeRegister(RME_FF400_MIDI_HIGH_ADDR, (node_id<<16) | midi_hi_addr) != 0)
111                 ret = -1;
112         }
113
114         if (ret==0) {
115             signed freq = dev_config->software_freq;
116             if (dev_config->dds_freq > 0)
117                 freq = dev_config->dds_freq;
118             if (set_hardware_dds_freq(freq) != 0)
119                 ret = -1;
120         }
121
122         if (m_rme_model == RME_MODEL_FIREFACE400) {
123             signed int i;
124             for (i=FF400_AMPGAIN_MIC1; i<=FF400_AMPGAIN_INPUT4; i++) {
125                 set_hardware_ampgain(i, settings->amp_gains[i]);
126             }
127         }
128
129         // Matrix mixer settings
130         for (dest=0; dest<n_channels; dest++) {
131             for (src=0; src<n_channels; src++) {
132                 settings->input_faders[getMixerGainIndex(src, dest)] = 0;
133                 set_hardware_mixergain(RME_FF_MM_INPUT, src, dest, 0);
134             }
135             for (src=0; src<n_channels; src++) {
136                 settings->playback_faders[getMixerGainIndex(src, dest)] =
137                   src==dest?0x8000:0;
138                 set_hardware_mixergain(RME_FF_MM_PLAYBACK, src, dest,
139                   src==dest?0x8000:0);
140             }
141         }
142         for (src=0; src<n_channels; src++) {
143             settings->output_faders[src] = 0x8000;
144             set_hardware_mixergain(RME_FF_MM_OUTPUT, src, 0, 0x8000);
145         }
146
147         set_hardware_output_rec(0);
148
149         dev_config->settings_valid = 1;
150     }
151
152
153     // Also configure the TCO (Time Code Option) settings for those devices
154     // which have a TCO.
155     if (ret==0 && dev_config->tco_settings_valid==0) {
156         if (dev_config->tco_present) {
157             memset(tco_settings, 0, sizeof(*tco_settings));
158             write_tco_settings(tco_settings);
159         }
160         dev_config->tco_settings_valid = 1;
161     }
162
163     config_unlock();
164
165     return ret;
166 }
167
168 signed int
169 Device::get_hardware_status(unsigned int *stat0, unsigned int *stat1)
170 {
171     unsigned int buf[2];
172     if (readBlock(RME_FF_STATUS_REG0, buf, 2) != 0)
173         return -1;
174     *stat0 = buf[0];
175     *stat1 = buf[1];
176     return 0;
177 }
178
179 signed int
180 Device::get_hardware_streaming_status(unsigned int *stat, unsigned int n)
181 {
182     // Get the hardware status as it applies to the streaming system.  This
183     // involves a request of 4 quadlets from the status register.  It
184     // appears that the first register's definition is slightly different in
185     // this situation compared to when only 2 quadlets are requested as is
186     // done in get_hardware_status().
187     //
188     // "n" is the size of the passed-in stat array.  It must be >= 4.
189     if (n < 4)
190         return -1;
191     if (readBlock(RME_FF_STATUS_REG0, stat, 4) != 0)
192         return -1;
193     return 0;
194 }
195
196 signed int
197 Device::get_hardware_state(FF_state_t *state)
198 {
199     // Retrieve the hardware status and deduce the device state.  Return
200     // -1 on error, 0 on success.  The given state structure will be
201     // cleared by this call.
202     unsigned int stat0, stat1;
203     memset(state, 0, sizeof(*state));
204     if (get_hardware_status(&stat0, &stat1) != 0)
205         return -1;
206
207     state->is_streaming = dev_config->is_streaming;
208
209     state->clock_mode = (settings->clock_mode == FF_SWPARAM_CLOCK_MODE_MASTER)?FF_STATE_CLOCKMODE_MASTER:FF_STATE_CLOCKMODE_AUTOSYNC;
210
211     switch (stat0 & SR0_AUTOSYNC_SRC_MASK) {
212         case SR0_AUTOSYNC_SRC_ADAT1:
213             state->autosync_source = FF_STATE_AUTOSYNC_SRC_ADAT1;
214             break;
215         case SR0_AUTOSYNC_SRC_ADAT2:
216             state->autosync_source = FF_STATE_AUTOSYNC_SRC_ADAT2;
217             break;
218         case SR0_AUTOSYNC_SRC_SPDIF:
219             state->autosync_source = FF_STATE_AUTOSYNC_SRC_SPDIF;
220             break;
221         case SR0_AUTOSYNC_SRC_WCLK:
222             state->autosync_source = FF_STATE_AUTOSYNC_SRC_WCLK;
223             break;
224         case SR0_AUTOSYNC_SRC_TCO:
225             state->autosync_source = FF_STATE_AUTOSYNC_SRC_TCO;
226             break;
227         default: state->autosync_source = FF_STATE_AUTOSYNC_SRC_NOLOCK;
228     }
229
230     switch (stat0 & SR0_AUTOSYNC_FREQ_MASK) {
231         case SR0_AUTOSYNC_FREQ_32k:  state->autosync_freq = 32000; break;
232         case SR0_AUTOSYNC_FREQ_44k1: state->autosync_freq = 44100; break;
233         case SR0_AUTOSYNC_FREQ_48k:  state->autosync_freq = 48000; break;
234         case SR0_AUTOSYNC_FREQ_64k:  state->autosync_freq = 64000; break;
235         case SR0_AUTOSYNC_FREQ_88k2: state->autosync_freq = 88200; break;
236         case SR0_AUTOSYNC_FREQ_96k:  state->autosync_freq = 96000; break;
237         case SR0_AUTOSYNC_FREQ_128k: state->autosync_freq = 128000; break;
238         case SR0_AUTOSYNC_FREQ_176k4:state->autosync_freq = 176400; break;
239         case SR0_AUTOSYNC_FREQ_192k: state->autosync_freq = 192000; break;
240     }
241
242     switch (stat0 & SR0_SPDIF_FREQ_MASK) {
243         case SR0_SPDIF_FREQ_32k:  state->spdif_freq = 32000; break;
244         case SR0_SPDIF_FREQ_44k1: state->spdif_freq = 41000; break;
245         case SR0_SPDIF_FREQ_48k:  state->spdif_freq = 48000; break;
246         case SR0_SPDIF_FREQ_64k:  state->spdif_freq = 64000; break;
247         case SR0_SPDIF_FREQ_88k2: state->spdif_freq = 88200; break;
248         case SR0_SPDIF_FREQ_96k:  state->spdif_freq = 96000; break;
249         case SR0_SPDIF_FREQ_128k: state->spdif_freq = 128000; break;
250         case SR0_SPDIF_FREQ_176k4:state->spdif_freq = 176400; break;
251         case SR0_SPDIF_FREQ_192k: state->spdif_freq = 192000; break;
252     }
253
254     switch (stat0 & SR0_ADAT1_STATUS_MASK) {
255         case SR0_ADAT1_STATUS_NOLOCK:
256             state->adat1_sync_status = FF_STATE_SYNC_NOLOCK; break;
257         case SR0_ADAT1_STATUS_LOCK:
258             state->adat1_sync_status = FF_STATE_SYNC_LOCKED; break;
259         case SR0_ADAT1_STATUS_SYNC:
260             state->adat1_sync_status = FF_STATE_SYNC_SYNCED; break;
261     }
262     switch (stat0 & SR0_ADAT2_STATUS_MASK) {
263         case SR0_ADAT2_STATUS_NOLOCK:
264             state->adat2_sync_status = FF_STATE_SYNC_NOLOCK; break;
265         case SR0_ADAT2_STATUS_LOCK:
266             state->adat2_sync_status = FF_STATE_SYNC_LOCKED; break;
267         case SR0_ADAT2_STATUS_SYNC:
268             state->adat2_sync_status = FF_STATE_SYNC_SYNCED; break;
269     }
270     switch (stat0 & SR0_SPDIF_STATUS_MASK) {
271         case SR0_SPDIF_STATUS_NOLOCK:
272             state->spdif_sync_status = FF_STATE_SYNC_NOLOCK; break;
273         case SR0_SPDIF_STATUS_LOCK:
274             state->spdif_sync_status = FF_STATE_SYNC_LOCKED; break;
275         case SR0_SPDIF_STATUS_SYNC:
276             state->spdif_sync_status = FF_STATE_SYNC_SYNCED; break;
277     }
278     switch (stat0 & SR0_WCLK_STATUS_MASK) {
279         case SR0_WCLK_STATUS_NOLOCK:
280             state->wclk_sync_status = FF_STATE_SYNC_NOLOCK; break;
281         case SR0_WCLK_STATUS_LOCK:
282             state->wclk_sync_status = FF_STATE_SYNC_LOCKED; break;
283         case SR0_WCLK_STATUS_SYNC:
284             state->wclk_sync_status = FF_STATE_SYNC_SYNCED; break;
285     }
286     switch (stat1 & SR1_TCO_STATUS_MASK) {
287        case SR1_TCO_STATUS_NOLOCK:
288            state->tco_sync_status = FF_STATE_SYNC_NOLOCK; break;
289        case SR1_TCO_STATUS_LOCK:
290            state->tco_sync_status = FF_STATE_SYNC_LOCKED; break;
291        case SR1_TCO_STATUS_SYNC:
292            state->tco_sync_status = FF_STATE_SYNC_SYNCED; break;
293     }
294
295     return 0;
296 }
297
298 signed int
299 Device::set_hardware_params(FF_software_settings_t *use_settings)
300 {
301     // Initialises the hardware to the state defined by the supplied
302     // software settings structure (which will usually be the device's
303     // "settings" structure).  This has the side effect of extinguishing the
304     // "Host" LED on the FF400 when done for the first time after the
305     // interface has been powered up.
306     //
307     // If use_settings is NULL, the device's current settings structure will
308     // be used to source the configuration information.
309
310     FF_software_settings_t *sw_settings;
311     quadlet_t data[3] = {0, 0, 0};
312     unsigned int conf_reg;
313
314     if (use_settings == NULL)
315       sw_settings = settings;
316     else
317       sw_settings = use_settings;
318
319     if (sw_settings->mic_phantom[0])
320       data[0] |= CR0_PHANTOM_MIC0;
321     if (sw_settings->mic_phantom[1])
322       data[0] |= CR0_PHANTOM_MIC1;
323     if (m_rme_model == RME_MODEL_FIREFACE800) {
324         if (sw_settings->mic_phantom[2])
325             data[0] |= CR0_FF800_PHANTOM_MIC9;
326         if (sw_settings->mic_phantom[3])
327             data[0] |= CR0_FF800_PHANTOM_MIC10;
328     } else {
329         if (sw_settings->ff400_input_pad[0])
330             data[0] |= CR0_FF400_CH3_PAD;
331         if (sw_settings->ff400_input_pad[1])
332             data[0] |= CR0_FF400_CH4_PAD;
333     }
334
335     /* Phones level */
336     switch (sw_settings->phones_level) {
337         case FF_SWPARAM_PHONESLEVEL_HIGAIN:
338             data[0] |= CRO_PHLEVEL_HIGAIN;
339             break;
340         case FF_SWPARAM_PHONESLEVEL_4dBU:
341             data[0] |= CR0_PHLEVEL_4dBU;
342             break;
343         case FF_SWPARAM_PHONESLEVEL_m10dBV:
344             data[0] |= CRO_PHLEVEL_m10dBV;
345             break;
346     }
347
348     /* Input level */
349     switch (sw_settings->input_level) {
350         case FF_SWPARAM_ILEVEL_LOGAIN: // Low gain
351             data[1] |= CR1_ILEVEL_CPLD_LOGAIN;    // CPLD
352             data[0] |= CR0_ILEVEL_FPGA_LOGAIN;    // LED control (used on FF800 only)
353             break;
354         case FF_SWPARAM_ILEVEL_4dBU:   // +4 dBu
355             data[1] |= CR1_ILEVEL_CPLD_4dBU;
356             data[0] |= CR0_ILEVEL_FPGA_4dBU;
357             break;
358         case FF_SWPARAM_ILEVEL_m10dBV: // -10 dBV
359             data[1] |= CR1_ILEVEL_CPLD_m10dBV;
360             data[0] |= CR0_ILEVEL_FPGA_m10dBV;
361             break;
362     }
363
364     /* Output level */
365     switch (sw_settings->output_level) {
366         case FF_SWPARAM_OLEVEL_HIGAIN: // High gain
367             data[1] |= CR1_OLEVEL_CPLD_HIGAIN;   // CPLD
368             data[0] |= CR0_OLEVEL_FPGA_HIGAIN;   // LED control (used on FF800 only)
369             break;
370         case FF_SWPARAM_OLEVEL_4dBU:   // +4 dBu
371             data[1] |= CR1_OLEVEL_CPLD_4dBU;
372             data[0] |= CR0_OLEVEL_FPGA_4dBU;
373             break;
374         case FF_SWPARAM_OLEVEL_m10dBV: // -10 dBV
375             data[1] |= CR1_OLEVEL_CPLD_m10dBV;
376             data[0] |= CR0_OLEVEL_FPGA_m10dBV;
377             break;
378     }
379
380     /* Set input options.  The meaning of the options differs between
381      * devices, so we use the generic identifiers here.
382      */
383     data[1] |= (sw_settings->input_opt[1] & FF_SWPARAM_INPUT_OPT_A) ? CR1_INPUT_OPT1_A : 0;
384     data[1] |= (sw_settings->input_opt[1] & FF_SWPARAM_INPUT_OPT_B) ? CR1_INPUT_OPT1_B : 0;
385     data[1] |= (sw_settings->input_opt[2] & FF_SWPARAM_INPUT_OPT_A) ? CR1_INPUT_OPT2_A : 0;
386     data[1] |= (sw_settings->input_opt[2] & FF_SWPARAM_INPUT_OPT_B) ? CR1_INPUT_OPT2_B : 0;
387
388     // Drive the speaker emulation / filter LED via FPGA in FF800.  In FF400
389     // the same bit controls the channel 4 "instrument" option.
390     if (m_rme_model == RME_MODEL_FIREFACE800) {
391         data[0] |= (sw_settings->filter) ? CR0_FF800_FILTER_FPGA : 0;
392     } else {
393         data[0] |= (sw_settings->ff400_instr_input[1]) ? CR0_FF400_CH4_INSTR : 0;
394     }
395
396     // Set the "rear" option for input 0 if selected
397     data[1] |= (sw_settings->input_opt[0] & FF_SWPARAM_FF800_INPUT_OPT_REAR) ? CR1_FF800_INPUT1_REAR : 0;
398
399     // The input 0 "front" option is activated using one of two bits
400     // depending on whether the filter (aka "speaker emulation") setting is
401     // active.
402     if (sw_settings->input_opt[0] & FF_SWPARAM_FF800_INPUT_OPT_FRONT) {
403         data[1] |= (sw_settings->filter) ? CR1_FF800_INPUT1_FRONT_WITH_FILTER : CR1_FF800_INPUT1_FRONT;
404     }
405
406     data[2] |= (sw_settings->spdif_output_emphasis==FF_SWPARAM_SPDIF_OUTPUT_EMPHASIS_ON) ? CR2_SPDIF_OUT_EMP : 0;
407     data[2] |= (sw_settings->spdif_output_pro==FF_SWPARAM_SPDIF_OUTPUT_PRO_ON) ? CR2_SPDIF_OUT_PRO : 0;
408     data[2] |= (sw_settings->spdif_output_nonaudio==FF_SWPARAM_SPDIF_OUTPUT_NONAUDIO_ON) ? CR2_SPDIF_OUT_NONAUDIO : 0;
409     data[2] |= (sw_settings->spdif_output_mode==FF_SWPARAM_SPDIF_OUTPUT_OPTICAL) ? CR2_SPDIF_OUT_ADAT2 : 0;
410     data[2] |= (sw_settings->clock_mode==FF_SWPARAM_CLOCK_MODE_AUTOSYNC) ? CR2_CLOCKMODE_AUTOSYNC : CR2_CLOCKMODE_MASTER;
411     data[2] |= (sw_settings->spdif_input_mode==FF_SWPARAM_SPDIF_INPUT_COAX) ? CR2_SPDIF_IN_COAX : CR2_SPDIF_IN_ADAT2;
412     data[2] |= (sw_settings->word_clock_single_speed=FF_SWPARAM_WORD_CLOCK_1x) ? CR2_WORD_CLOCK_1x : 0;
413
414     /* TMS / TCO toggle bits in CR2 are not set by other drivers */
415
416     /* Drive / fuzz in FF800.  In FF400, the CR0 bit used by "Drive" controls
417      * the channel 3 "instrument" option.
418      */
419     if (m_rme_model == RME_MODEL_FIREFACE800) {
420         if (sw_settings->fuzz)
421             data[0] |= CR0_FF800_DRIVE_FPGA; // FPGA LED control
422         else
423             data[1] |= CR1_INSTR_DRIVE;      // CPLD
424     } else {
425         data[0] |= (sw_settings->ff400_instr_input[0]) ? CR0_FF400_CH3_INSTR : 0;
426     }
427
428     /* Drop-and-stop is hardwired on in other drivers */
429     data[2] |= CR2_DROP_AND_STOP;
430
431     if (m_rme_model == RME_MODEL_FIREFACE400) {
432         data[2] |= CR2_FF400_BIT;
433     }
434
435     switch (sw_settings->sync_ref) {
436         case FF_SWPARAM_SYNCREF_WORDCLOCK:
437             data[2] |= CR2_SYNC_WORDCLOCK;
438             break;
439         case FF_SWPARAM_SYNCREF_ADAT1:
440             data[2] |= CR2_SYNC_ADAT1;
441             break;
442         case FF_SWPARAM_SYNCREF_ADAT2:
443             data[2] |= CR2_SYNC_ADAT2;
444             break;
445         case FF_SWPARAM_SYNCREF_SPDIF:
446             data[2] |= CR2_SYNC_SPDIF;
447             break;
448         case FF_SWPARAM_SYNCREC_TCO:
449             data[2] |= CR2_SYNC_TCO;
450             break;
451     }
452
453     // This is hardwired in other drivers
454     data[2] |= (CR2_FREQ0 + CR2_FREQ1 + CR2_DSPEED + CR2_QSSPEED);
455
456     // The FF800 limiter applies to the front panel instrument input, so it
457     // only makes sense that it is disabled when that input is in use.
458     data[2] |= (sw_settings->limiter_disable &&
459                 (sw_settings->input_opt[0] & FF_SWPARAM_FF800_INPUT_OPT_FRONT)) ?
460                 CR2_DISABLE_LIMITER : 0;
461
462 //This is just for testing - it's a known consistent configuration
463 //data[0] = 0x00020810;      // Phantom off
464 //data[0] = 0x00020811;      // Phantom on
465 //data[1] = 0x0000031e;
466 //data[2] = 0xc400101f;
467     debugOutput(DEBUG_LEVEL_VERBOSE, "set hardware registers: 0x%08x 0x%08x 0x%08x\n",
468       data[0], data[1], data[2]);
469
470     conf_reg = (m_rme_model==RME_MODEL_FIREFACE800)?RME_FF800_CONF_REG:RME_FF400_CONF_REG;
471     if (writeBlock(conf_reg, data, 3) != 0)
472         return -1;
473
474     return 0;
475 }
476
477 signed int
478 Device::read_tco(quadlet_t *tco_data, signed int size)
479 {
480     // Read the TCO registers and return the respective values in *tco_data.
481     // Return value is 0 on success, or -1 if there is no TCO present.
482     // "size" is the size (in quadlets) of the array pointed to by tco_data.
483     // To obtain all TCO data "size" should be at least 4.  If the caller
484     // doesn't care about the data returned by the TCO, tco_data can be
485     // NULL.
486     quadlet_t buf[4];
487     signed int i;
488
489     // The Fireface 400 can't have the TCO fitted
490     if (m_rme_model==RME_MODEL_FIREFACE400)
491         return -1;
492
493     if (readBlock(RME_FF_TCO_READ_REG, buf, 4) != 0)
494         return -1;
495
496     if (tco_data != NULL) {
497         for (i=0; i<(size<4)?size:4; i++)
498             tco_data[i] = buf[i];
499     }
500
501     if ( (buf[0] & 0x80808080) == 0x80808080 &&
502          (buf[1] & 0x80808080) == 0x80808080 &&
503          (buf[2] & 0x80808080) == 0x80808080 &&
504          (buf[3] & 0x8000FFFF) == 0x80008000) {
505         // A TCO is present
506         return 0;
507     }
508
509     return -1;
510 }
511
512 signed int
513 Device::write_tco(quadlet_t *tco_data, signed int size)
514 {
515     // Writes data to the TCO.  No check is made as to whether a TCO is
516     // present in the current device.  Return value is 0 on success or -1 on
517     // error.  "size" is the size (in quadlets) of the data pointed to by
518     // "tco_data".  The first 4 quadlets of tco_data are significant; all
519     // others are ignored.  If fewer than 4 quadlets are supplied (as
520     // indicated by the "size" parameter, -1 will be returned.
521     if (size < 4)
522         return -1;
523
524     // Don't bother trying to write if the device is a FF400 since the TCO
525     // can't be fitted to this device.
526     if (m_rme_model==RME_MODEL_FIREFACE400)
527         return -1;
528
529     if (writeBlock(RME_FF_TCO_WRITE_REG, tco_data, 4) != 0)
530         return -1;
531
532     return 0;
533 }
534
535 signed int
536 Device::hardware_is_streaming(void)
537 {
538     // Return 1 if the hardware is streaming, 0 if not.
539     return dev_config->is_streaming;
540 }
541
542 signed int
543 Device::read_tco_state(FF_TCO_state_t *tco_state)
544 {
545     // Reads the current TCO state into the supplied state structure
546
547     quadlet_t tc[4];
548     unsigned int PLL_phase;
549
550     if (read_tco(tc, 4) != 0)
551       return -1;
552
553     // The timecode is stored in BCD (binary coded decimal) in register 0.
554     tco_state->frames = (tc[0] & 0xf) + ((tc[0] & 0x30) >> 4)*10;
555     tco_state->seconds = ((tc[0] & 0xf00) >> 8) + ((tc[0] & 0x7000) >> 12)*10;
556     tco_state->minutes = ((tc[0] & 0xf0000) >> 16) + ((tc[0] & 0x700000) >> 20)*10;
557     tco_state->hours = ((tc[0] & 0xf000000) >> 24) + ((tc[0] & 0x30000000) >> 28)*10;
558
559     tco_state->locked = (tc[1] & FF_TCO1_TCO_lock) != 0;
560     tco_state->ltc_valid = (tc[1] & FF_TCO1_LTC_INPUT_VALID) != 0;
561
562     switch (tc[1] & FF_TCO1_LTC_FORMAT_MASK) {
563         case FF_TC01_LTC_FORMAT_24fps:
564           tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_24fps; break;
565         case FF_TCO1_LTC_FORMAT_25fps:
566           tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_25fps; break;
567         case FF_TC01_LTC_FORMAT_29_97fps:
568           tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_29_97fps; break;
569         case FF_TCO1_LTC_FORMAT_30fps:
570           tco_state->frame_rate = FF_TCOSTATE_FRAMERATE_30fps; break;
571     }
572
573     tco_state->drop_frame = (tc[1] & FF_TCO1_SET_DROPFRAME) != 0;
574
575     switch (tc[1] & FF_TCO1_VIDEO_INPUT_MASK) {
576         case FF_TCO1_VIDEO_INPUT_NTSC:
577             tco_state->video_input = FF_TCOSTATE_VIDEO_NTSC; break;
578         case FF_TCO1_VIDEO_INPUT_PAL:
579             tco_state->video_input = FF_TCOSTATE_VIDEO_PAL; break;
580         default:
581             tco_state->video_input = FF_TCOSTATE_VIDEO_NONE;
582     }
583
584     if ((tc[1] & FF_TCO1_WORD_CLOCK_INPUT_VALID) == 0) {
585         tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_NONE;
586     } else {
587         switch (tc[1] & FF_TCO1_WORD_CLOCK_INPUT_MASK) {
588             case FF_TCO1_WORD_CLOCK_INPUT_1x:
589                 tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_1x; break;
590             case FF_TCO1_WORD_CLOCK_INPUT_2x:
591                 tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_2x; break;
592             case FF_TCO1_WORD_CLOCK_INPUT_4x:
593                 tco_state->word_clock_state = FF_TCOSTATE_WORDCLOCK_4x; break;
594         }
595     }
596
597     PLL_phase = (tc[2] & 0x7f) + ((tc[2] & 0x7f00) >> 1);
598     tco_state->sample_rate = (25000000.0 * 16.0)/PLL_phase;
599
600     return 0;
601 }
602
603 signed int
604 Device::write_tco_settings(FF_TCO_settings_t *tco_settings)
605 {
606     // Writes the supplied application-level settings to the device's TCO
607     // (Time Code Option).  Don't bother doing anything if the device doesn't
608     // have a TCO fitted.  Returns 0 on success, -1 on error.
609
610     quadlet_t tc[4] = {0, 0, 0, 0};
611
612     if (!dev_config->tco_present) {
613         return -1;
614     }
615
616     if (tco_settings->MTC)
617         tc[0] |= FF_TCO0_MTC;
618
619     switch (tco_settings->input) {
620         case FF_TCOPARAM_INPUT_LTC:
621             tc[2] |= FF_TCO2_INPUT_LTC; break;
622         case FF_TCOPARAM_INPUT_VIDEO:
623             tc[2] |= FF_TCO2_INPUT_VIDEO; break;
624         case FF_TCOPARAM_INPUT_WCK:
625             tc[2] |= FF_TCO2_INPUT_WORD_CLOCK; break;
626     }
627
628     switch (tco_settings->frame_rate) {
629         case FF_TCOPARAM_FRAMERATE_24fps:
630             tc[1] |= FF_TC01_LTC_FORMAT_24fps; break;
631         case FF_TCOPARAM_FRAMERATE_25fps:
632             tc[1] |= FF_TCO1_LTC_FORMAT_25fps; break;
633         case FF_TCOPARAM_FRAMERATE_29_97fps:
634             tc[1] |= FF_TC01_LTC_FORMAT_29_97fps; break;
635         case FF_TCOPARAM_FRAMERATE_29_97dfps:
636             tc[1] |= FF_TCO1_LTC_FORMAT_29_97dpfs; break;
637         case FF_TCOPARAM_FRAMERATE_30fps:
638             tc[1] |= FF_TCO1_LTC_FORMAT_30fps; break;
639         case FF_TCOPARAM_FRAMERATE_30dfps:
640             tc[1] |= FF_TCO1_LTC_FORMAT_30dfps; break;
641     }
642
643     switch (tco_settings->word_clock) {
644         case FF_TCOPARAM_WORD_CLOCK_CONV_1_1:
645             tc[2] |= FF_TCO2_WORD_CLOCK_CONV_1_1; break;
646         case FF_TCOPARAM_WORD_CLOCK_CONV_44_48:
647             tc[2] |= FF_TCO2_WORD_CLOCK_CONV_44_48; break;
648         case FF_TCOPARAM_WORD_CLOCK_CONV_48_44:
649             tc[2] |= FF_TCO2_WORD_CLOCK_CONV_48_44; break;
650     }
651
652     switch (tco_settings->sample_rate) {
653         case FF_TCOPARAM_SRATE_44_1:
654             tc[2] |= FF_TCO2_SRATE_44_1; break;
655         case FF_TCOPARAM_SRATE_48:
656             tc[2] |= FF_TCO2_SRATE_48; break;
657         case FF_TCOPARAM_SRATE_FROM_APP:
658             tc[2] |= FF_TCO2_SRATE_FROM_APP; break;
659     }
660
661     switch (tco_settings->pull) {
662         case FF_TCPPARAM_PULL_NONE:
663             tc[2] |= FF_TCO2_PULL_0; break;
664         case FF_TCOPARAM_PULL_UP_01:
665             tc[2] |= FF_TCO2_PULL_UP_01; break;
666         case FF_TCOPARAM_PULL_DOWN_01:
667             tc[2] |= FF_TCO2_PULL_DOWN_01; break;
668         case FF_TCOPARAM_PULL_UP_40:
669             tc[2] |= FF_TCO2_PULL_UP_40; break;
670         case FF_TCOPARAM_PULL_DOWN_40:
671             tc[2] |= FF_TCO2_PULL_DOWN_40; break;
672     }
673
674     if (tco_settings->termination == FF_TCOPARAM_TERMINATION_ON)
675         tc[2] |= FF_TCO2_SET_TERMINATION;
676
677     return write_tco(tc, 4);
678 }
679
680 signed int
681 Device::set_hardware_dds_freq(signed int freq)
682 {
683     // Set the device's DDS to the given frequency (which in turn determines
684     // the sampling frequency).  Returns 0 on success, -1 on error.
685
686     unsigned int ret = 0;
687
688     if (freq < MIN_SPEED || freq > MAX_SPEED)
689         return -1;
690
691     if (m_rme_model == RME_MODEL_FIREFACE400)
692         ret = writeRegister(RME_FF400_STREAM_SRATE, freq);
693     else
694         ret = writeRegister(RME_FF800_STREAM_SRATE, freq);
695
696     if (ret == 0)
697         dev_config->hardware_freq = freq;
698
699     return ret;
700 }
701
702 signed int
703 Device::hardware_init_streaming(unsigned int sample_rate,
704     unsigned int tx_channel)
705 {
706     // tx_channel is the ISO channel the PC will transmit on.
707     quadlet_t buf[5];
708     fb_nodeaddr_t addr;
709     unsigned int size;
710
711 debugOutput(DEBUG_LEVEL_VERBOSE, "*** stream init: %d, %d, %d\n",
712   sample_rate, num_channels, tx_channel);
713
714     buf[0] = sample_rate;
715     buf[1] = (num_channels << 11) + tx_channel;
716     buf[2] = num_channels;
717     buf[3] = 0;
718     buf[4] = 0;
719     if (speed800) {
720         buf[2] |= RME_FF800_STREAMING_SPEED_800;
721     }
722
723     if (m_rme_model == RME_MODEL_FIREFACE400) {
724         addr = RME_FF400_STREAM_INIT_REG;
725         size = RME_FF400_STREAM_INIT_SIZE;
726     } else {
727         addr = RME_FF800_STREAM_INIT_REG;
728         size = RME_FF800_STREAM_INIT_SIZE;
729     }
730
731     return writeBlock(addr, buf, size);
732 }
733
734 signed int
735 Device::hardware_start_streaming(unsigned int listen_channel)
736 {
737     signed int ret = 0;
738     // Listen_channel is the ISO channel the PC will listen on for data sent
739     // by the Fireface.
740     fb_nodeaddr_t addr;
741     quadlet_t data = num_channels;
742
743     config_lock();
744     if (not(hardware_is_streaming())) {
745 debugOutput(DEBUG_LEVEL_VERBOSE,"*** starting: listen=%d, num_ch=%d\n", listen_channel, num_channels);
746         if (m_rme_model == RME_MODEL_FIREFACE400) {
747             addr = RME_FF400_STREAM_START_REG;
748             data |= (listen_channel << 5);
749         } else {
750             addr = RME_FF800_STREAM_START_REG;
751             if (speed800)
752                 data |= RME_FF800_STREAMING_SPEED_800; // Flag 800 Mbps speed
753         }
754
755 debugOutput(DEBUG_LEVEL_VERBOSE, "start 0x%016llx data: %08x\n", addr, data);
756         ret = writeRegister(addr, data);
757 debugOutput(DEBUG_LEVEL_VERBOSE, "  ret=%d\n", ret);
758         if (ret == 0) {
759             dev_config->is_streaming = 1;
760         }
761
762         set_hardware_channel_mute(-1, 0);
763
764     } else
765         ret = 0;
766     config_unlock();
767
768     return ret;
769 }
770
771 signed int
772 Device::hardware_stop_streaming(void)
773 {
774     fb_nodeaddr_t addr;
775     quadlet_t buf[4] = {0, 0, 0, 1};
776     unsigned int size, ret = 0;
777
778     config_lock();
779     if (hardware_is_streaming()) {
780         if (m_rme_model == RME_MODEL_FIREFACE400) {
781             addr = RME_FF400_STREAM_END_REG;
782             size = RME_FF400_STREAM_END_SIZE;
783         } else {
784             addr = RME_FF800_STREAM_END_REG;
785             size = RME_FF800_STREAM_END_SIZE;
786         }
787
788         ret = writeBlock(addr, buf, size);
789         if (ret == 0) {
790             dev_config->is_streaming = 0;
791         }
792
793         set_hardware_channel_mute(-1, 1);
794
795     } else
796         ret = 0;
797     config_unlock();
798
799     return ret;
800 }
801
802 signed int
803 Device::set_hardware_ampgain(unsigned int index, signed int val) {
804 // "index" indicates the hardware amplifier gain to set.  Values of 0-3
805 // correspond to input amplifier gains.  Values from 4 on relate to output
806 // volume.
807 //
808 // "val" is in dB except for inputs 3/4 where it's in units of 0.5 dB. This
809 // function is responsible for converting to/from the scale used by the
810 // device.
811 //
812 // Only the FF400 has the hardware gain register which is controlled by this
813 // function.
814     quadlet_t regval = 0;
815     signed int devval = 0;
816     if (val > 120)
817       val = 120;
818     if (val < -120)
819       val = -120;
820     if (index <= FF400_AMPGAIN_MIC2) {
821         if (val >= 10)
822             devval = val;
823         else
824             devval = 0;
825     } else
826     if (index <= FF400_AMPGAIN_INPUT4) {
827         devval = val;
828     } else {
829         devval = 6 - val;
830         if (devval > 53)
831             devval = 0x3f;  // Mute
832     }
833     regval |= devval;
834     regval |= (index << 16);
835     return writeRegister(RME_FF400_GAIN_REG, regval);
836 }
837
838 signed int
839 Device::set_hardware_mixergain(unsigned int ctype, unsigned int src_channel,
840   unsigned int dest_channel, signed int val) {
841 // Set the value of a matrix mixer control.  ctype is one of the RME_FF_MM_*
842 // defines:
843 //   RME_FF_MM_INPUT: source is a physical input
844 //   RME_FF_MM_PLAYBACK: source is playback from PC
845 //   RME_FF_MM_OUTPUT: source is the physical output whose gain is to be
846 //     changed, destination is ignored
847 // Val is the integer value sent to the device.  The amount of gain (in dB)
848 // applied can be calculated using
849 //   dB = 20.log10(val/32768)
850 // The maximum value of val is 0x10000, corresponding to +6dB of gain.
851 // The minimum is 0x00000 corresponding to mute.
852
853     unsigned int n_channels;
854     signed int ram_output_block_size;
855     unsigned int ram_addr;
856
857     n_channels = (m_rme_model==RME_MODEL_FIREFACE400)?
858         RME_FF400_MAX_CHANNELS:RME_FF800_MAX_CHANNELS;
859     if (src_channel>n_channels || dest_channel>n_channels)
860         return -1;
861     if (val<0 || val>0x10000)
862         return -1;
863
864     if (m_rme_model == RME_MODEL_FIREFACE400) {
865         ram_output_block_size = 0x48;
866     } else {
867         ram_output_block_size = 0x80;
868     }
869
870     ram_addr = RME_FF_MIXER_RAM;
871     switch (ctype) {
872         case RME_FF_MM_INPUT:
873         case RME_FF_MM_PLAYBACK:
874             ram_addr += (dest_channel*2*ram_output_block_size) + 4*src_channel;
875             if (ctype == RME_FF_MM_PLAYBACK)
876                  ram_addr += ram_output_block_size;
877             break;
878         case RME_FF_MM_OUTPUT:
879             ram_addr += 0x0f80 + 4*src_channel;
880             break;
881     }
882
883     writeRegister(ram_addr, val);
884
885     // If setting the output volume and the device is the FF400, keep
886     // the separate gain register in sync.
887     if (ctype==RME_FF_MM_OUTPUT && m_rme_model==RME_MODEL_FIREFACE400) {
888         signed int dB;
889         if (val==0)
890             dB = -90;
891         else
892             dB = roundl(20.0*log10(val/32768.0));
893         set_hardware_ampgain(FF400_AMPGAIN_OUTPUT1+src_channel, dB);
894     }
895
896     return 0;
897 }
898
899 signed int
900 Device::set_hardware_channel_mute(signed int chan, signed int mute) {
901
902 // Mute hardware channels as instructed.  This mute probably relates to the
903 // sampled input channels as delivered to the PC.  If "chan" is -1 the
904 // supplied "mute" status is applied to all channels.  This is the only
905 // supported "chan" value for now.  Down the track, if there's a need,
906 // this could be extended to allow individual channel control.
907     quadlet_t buf[28];
908     signed int i;
909     signed int n_channels = (m_rme_model==RME_MODEL_FIREFACE400)?
910         RME_FF400_MAX_CHANNELS:RME_FF800_MAX_CHANNELS;
911
912     i = 0;
913     if (chan < 0) {
914         while (i<n_channels && i<28) {
915             buf[i++] = (mute!=0);
916         }
917     } else {
918       return 0;
919     }
920
921     while (i < 28) {
922         buf[i++] = 0x00000001;
923     }
924
925     // Write 28 quadlets even for FF400
926     return writeBlock(RME_FF_CHANNEL_MUTE_MASK, buf, 28);
927 }
928
929 signed int
930 Device::set_hardware_output_rec(signed int rec) {
931 // Explicitly record (mute!=1) outputs, or not.
932 // TODO: fill the details in to allow individual outputs to be recorded as
933 // required.
934     quadlet_t buf[28];
935     signed int i;
936
937     for (i=0; i<28; i++)
938         buf[i] = (rec!=0);
939
940     // Write 28 quadlets even for FF400
941     return writeBlock(RME_FF_OUTPUT_REC_MASK, buf, 28);
942 }
943
944 }
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