| | 936 | 0x0c70 - gain trim / phase invert (Ultralite only, analog channels 1-4) |
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| | 937 | |
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| | 938 | On the Ultralite, gain trim is controlled using a different register than |
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| | 939 | with the other MOTU devices. This register controls gain trim and phase |
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| | 940 | inversion for analog channels 1-4. Byte 0 (the least significant byte) |
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| | 941 | controls analog channel 1. Bytes 1-3 are for analog channels 2-4 |
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| | 942 | respectively. |
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| | 943 | |
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| | 944 | Bit 7 in each byte appears to always be set to 1 when changing the |
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| | 945 | corresponding channel's setting. It therefore seems that bit 7 is a |
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| | 946 | write-enable bit for the channel's setting. |
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| | 947 | |
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| | 948 | Bit 6 of a byte controls the phase inversion setting. When set (ie: equal |
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| | 949 | to 1) phase inversion is active. When bit 6 is zero phase inversion is not |
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| | 950 | enagaged. |
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| | 951 | |
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| | 952 | Bits 0-5 set the gain trim value; 0 sets a gain of 0dB (the default). The |
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| | 953 | maximum gain available is determined by the type of channel. For analog |
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| | 954 | channels 1-2 (the mic inputs), the maximum effective setting is 0x18 (24). |
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| | 955 | For analog channels 3-8 the maximum is 0x12 (18) while for SPDIF channels |
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| | 956 | the maximum is 0x0c (12). The value written is in dB - thus each gain trim |
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| | 957 | control operates in steps of 1 dB. |
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| | 958 | |
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| | 959 | Setting a channel's byte to zero causes its settings to remain unchanged. |
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| | 960 | This allows any combination of the 4 channels to be changed without |
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| | 961 | interference to those not being changed. |
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| | 962 | |
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| | 963 | |
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| | 964 | 0x0c74 - gain trim / phase invert (Ultralite only, analog channels 5-8) |
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| | 965 | |
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| | 966 | This register operates as described for 0x0c70 except it controls analog |
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| | 967 | channes 5 to 8. The least significant byte corresponds to analog channel 5. |
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| | 968 | |
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| | 969 | |
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| | 970 | 0x0c78 - gain trim / phase invert (Ultralite only, SPDIF 1 and 2) |
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| | 971 | |
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| | 972 | This register operates as described for 0x0c70 except it controls SPDIF 1 |
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| | 973 | and SPDIF 2. The least significant byte corresponds to SPDIF 1. Bytes 2 |
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| | 974 | and 3 are currently unused and should always be set to zero when writing to |
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| | 975 | this register. |
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| | 976 | |
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| | 977 | |
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