| 51 | | #define RME_FF400_CONF_REG (RME_FF400_CMD_BUFFER + RME_FF_CONF1_OFS) |
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| 52 | | #define RME_FF800_CONF_REG (RME_FF800_CMD_BUFFER + RME_FF_CONF1_OFS) |
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| 53 | | |
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| 54 | | #define RME_FF400_STREAM_START_REG (RME_FF400_CMD_BUFFER + 0x001c) |
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| 55 | | #define RME_FF800_STREAM_START_REG 0x200000028LL |
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| 56 | | #define RME_FF400_STREAM_END_REG (RME_FF400_CMD_BUFFER + 0x0004) // 4 quadlets wide |
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| | 51 | #define RME_FF400_CONF_REG (RME_FF400_CMD_BUFFER + RME_FF_CONF1_OFS) |
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| | 52 | #define RME_FF800_CONF_REG (RME_FF800_CMD_BUFFER + RME_FF_CONF1_OFS) |
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| | 53 | |
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| | 54 | #define RME_FF400_STREAM_SRATE (RME_FF400_CMD_BUFFER) |
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| | 55 | #define RME_FF400_STREAM_CONF0 (RME_FF400_CMD_BUFFER+4) |
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| | 56 | #define RME_FF400_STREAM_CONF1 (RME_FF400_CMD_BUFFER+8) |
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| | 57 | #define RME_FF800_STREAM_SRATE 0x20000001c |
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| | 58 | #define RME_FF800_STREAM_CONF0 (0x20000001c+4) |
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| | 59 | #define RME_FF800_STREAM_CONF1 (0x20000001c+8) |
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| | 60 | #define RME_FF400_STREAM_START_REG0 (RME_FF400_CMD_BUFFER + 0x001c) |
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| | 61 | #define RME_FF800_STREAM_START_REG0 0x200000028LL |
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| | 62 | #define RME_FF400_STREAM_END_REG (RME_FF400_CMD_BUFFER + 0x0004) // 4 quadlets wide |
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| 102 | | /* FIXME: flesh this out once the details of how this gets used have been |
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| 103 | | * finalised |
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| 104 | | */ |
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| | 108 | // Configuration register 0 |
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| | 109 | #define CR0_PHANTOM_MIC0 0x00000001 |
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| | 110 | #define CR0_PHANTOM_MIC2 0x00000002 |
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| | 111 | #define CR0_SPEAKER_EMU_FPGA 0x00000004 |
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| | 112 | #define CR0_ILEVEL_FPGA_CTRL0 0x00000008 |
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| | 113 | #define CR0_ILEVEL_FPGA_CTRL1 0x00000010 |
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| | 114 | #define CR0_ILEVEL_FPGA_CTRL2 0x00000020 |
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| | 115 | #define CR0_ZEROBIT06 0x00000040 |
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| | 116 | #define CR0_PHANTOM_MIC1 0x00000080 |
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| | 117 | #define CR0_PHANTOM_MIC3 0x00000100 |
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| | 118 | #define CR0_ZEROBIT09 0x00000200 |
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| | 119 | #define CR0_INSTR_DRIVE_FPGA 0x00000400 |
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| | 120 | #define CRO_OLEVEL_FPGA_CTRL_0 0x00000800 |
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| | 121 | #define CRO_OLEVEL_FPGA_CTRL_1 0x00001000 |
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| | 122 | #define CRO_OLEVEL_FPGA_CTRL_2 0x00002000 |
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| | 123 | #define CRO_ZEROBIT14 0x00004000 |
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| | 124 | #define CRO_ZEROBIT15 0x00008000 |
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| | 125 | #define CRO_PHLEVEL_CTRL0 0x00010000 |
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| | 126 | #define CRO_PHLEVEL_CTRL1 0x00020000 |
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| | 127 | |
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| | 128 | #define CR0_PHANTOM_FF400_MIC0 CR0_PHANTOM_MIC0 |
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| | 129 | #define CR0_PHANTOM_FF400_MIC1 CR0_PHANTOM_MIC1 |
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| | 130 | #define CR0_PHANTOM_FF800_MIC7 CR0_PHANTOM_MIC0 |
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| | 131 | #define CR0_PHANTOM_FF800_MIC8 CR0_PHANTOM_MIC1 |
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| | 132 | #define CR0_PHANTOM_FF800_MIC9 CR0_PHANTOM_MIC2 |
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| | 133 | #define CR0_PHANTOM_FF800_MIC10 CR0_PHANTOM_MIC3 |
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| | 134 | #define CR0_ILEVEL_FPGA_LOGAIN CR0_ILEVEL_FPGA_CTRL0 |
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| | 135 | #define CR0_ILEVEL_FPGA_4dBU CR0_ILEVEL_FPGA_CTRL1 |
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| | 136 | #define CR0_ILEVEL_FPGA_m10dBV CR0_ILEVEL_FPGA_CTRL2 |
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| | 137 | #define CR0_OLEVEL_FPGA_HIGAIN CRO_OLEVEL_FPGA_CTRL_0 |
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| | 138 | #define CR0_OLEVEL_FPGA_4dBU CRO_OLEVEL_FPGA_CTRL_1 |
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| | 139 | #define CR0_OLEVEL_FPGA_m10dBV CRO_OLEVEL_FPGA_CTRL_2 |
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| | 140 | #define CR0_PHLEVEL_4dBU 0 |
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| | 141 | #define CRO_PHLEVEL_m10dBV CRO_PHLEVEL_CTRL0 |
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| | 142 | #define CRO_PHLEVEL_HIGAIN CRO_PHLEVEL_CTRL1 |
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| | 143 | |
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| | 144 | // Configuration register 1 |
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| | 145 | #define CR1_ILEVEL_CPLD_CTRL0 0x00000001 |
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| | 146 | #define CR1_ILEVEL_CPLD_CTRL1 0x00000002 |
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| | 147 | #define CR1_INPUT0_REAR 0x00000004 |
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| | 148 | #define CR1_OLEVEL_CPLD_CTRL0 0x00000008 |
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| | 149 | #define CR1_OLEVEL_CPLD_CTRL1 0x00000010 |
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| | 150 | #define CR1_INPUT1_FRONT 0x00000020 |
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| | 151 | #define CR1_INPUT1_REAR 0x00000040 |
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| | 152 | #define CR1_INPUT2_FRONT 0x00000080 |
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| | 153 | #define CR1_INPUT2_REAR 0x00000100 |
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| | 154 | #define CR1_INSTR_DRIVE 0x00000200 |
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| | 155 | #define CR1_ZEROBIT10 0x00000400 |
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| | 156 | #define CR1_INPUT0_FRONT 0x00000800 |
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| | 157 | |
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| | 158 | #define CR1_ILEVEL_CPLD_LOGAIN 0 |
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| | 159 | #define CR1_ILEVEL_CPLD_4dBU CR1_ILEVEL_CPLD_CTRL1 |
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| | 160 | #define CR1_ILEVEL_CPLD_m10dBV (CR1_ILEVEL_CPLD_CTRL0 | CR1_ILEVEL_CPLD_CTRL1) |
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| | 161 | #define CR1_OLEVEL_CPLD_m10dBV CR1_OLEVEL_CPLD_CTRL0 |
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| | 162 | #define CR1_OLEVEL_CPLD_HIGAIN CR1_OLEVEL_CPLD_CTRL1 |
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| | 163 | #define CR1_OLEVEL_CPLD_4dBU (CR1_OLEVEL_CPLD_CTRL0 | CR1_OLEVEL_CPLD_CTRL1) |
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| | 164 | #define CR1_FF800_INPUT1_FRONT CR1_INPUT0_FRONT |
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| | 165 | #define CR1_FF800_INPUT1_REAR CR1_INPUT0_REAR |
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| | 166 | #define CR1_FF800_INPUT7_FRONT CR1_INPUT1_FRONT |
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| | 167 | #define CR1_FF800_INPUT7_REAR CR1_INPUT1_REAR |
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| | 168 | #define CR1_FF800_INPUT8_FRONT CR1_INPUT2_FRONT |
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| | 169 | #define CR1_FF800_INPUT8_REAR CR1_INPUT2_REAR |
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| | 170 | |
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| | 171 | // Configuration register 2 |
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