Changeset 1570
- Timestamp:
- 05/29/09 07:18:55 (14 years ago)
- Files:
-
- trunk/libffado/doc/rme_notes/rme_config_register_map.txt (modified) (5 diffs)
- trunk/libffado/src/rme/fireface_def.h (modified) (9 diffs)
- trunk/libffado/src/rme/fireface_hw.cpp (modified) (5 diffs)
Legend:
- Unmodified
- Added
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trunk/libffado/doc/rme_notes/rme_config_register_map.txt
r1547 r1570 2 2 ============================================ 3 3 4 Version: 0. 94 Version: 0.10 5 5 Author: Jonathan Woithe 6 Date: 2 7 April20096 Date: 29 May 2009 7 7 8 8 … … 40 40 to be sent on the bus in big endian format (although this is to be 41 41 confirmed). 42 43 The FF800 includes a number of instrument options for input 1 which are 44 described using several different terms interchangeably: 45 - "Drive" (also referred to as "fuzz") activates 25 dB extra gain 46 - "Speaker emulation" (also referred to as "filter") removes LF noise and 47 some HF 48 - "Limiter" activates a soft-limiter with a threshold of -10 dBFS. This 49 can only be switched off if the Front input is used for channel 1. 42 50 43 51 … … 313 321 2 - ASIO latency (FF400=0x00000001) 314 322 3 - Samples per frame (FF400 default is 0x30) 315 4 SPDIF input mode ( 1=coax?, 0=optical?)323 4 SPDIF input mode (2=coax?, 1=optical?) 316 324 5 SPDIF output emphasis active 317 325 6 SPDIF output is "professional" (ie: AES/EBU) 318 7 Clock mode ( 0=master?, 1=autosync?)326 7 Clock mode (2=master?, 1=autosync?) 319 327 8 SPDIF output is non-audio (eg: AC3 passthrough) 320 328 9 Sync reference … … 335 343 27 - Bandwidth allocated (FF400=0x00000000) 336 344 28 Stop on dropout (FF400=0x00000000) 337 29 Input level (0= lo-gain)338 30 Output level (0= -10dBV)345 29 Input level (0=default, 1=lo-gain, 2=+4dBU, 3=-10dBV ???) 346 30 Output level (0=default, 1=hi-gain, 2=+4dBU, 3=-10dBV ???) 339 347 31 Mic level [0] - FF400:Phoneslevel-1 / F800:AnalogInput[1]* ??? 340 348 32 Mic level [1] - AnalogInput[2] ??? … … 352 360 47 - Number of channels (FF400=0x000000f0) 353 361 48 - Dropped samples 354 49 p12db_an[0] - Limiter==0&&AnalogInput[0]==2*: 1 else 0 ???362 49 p12db_an[0] - Disable limiter, settable only if input 1 front jack active 355 363 50 - p12db_an[1-9] 356 364 trunk/libffado/src/rme/fireface_def.h
r1553 r1570 111 111 #define CR0_PHANTOM_MIC0 0x00000001 112 112 #define CR0_PHANTOM_MIC2 0x00000002 113 #define CR0_ SPEAKER_EMU_FPGA0x00000004113 #define CR0_FILTER_FPGA 0x00000004 114 114 #define CR0_ILEVEL_FPGA_CTRL0 0x00000008 115 115 #define CR0_ILEVEL_FPGA_CTRL1 0x00000010 … … 148 148 #define CR1_ILEVEL_CPLD_CTRL0 0x00000001 149 149 #define CR1_ILEVEL_CPLD_CTRL1 0x00000002 150 #define CR1_INPUT 0_REAR 0x00000004150 #define CR1_INPUT_OPT0_B 0x00000004 // Input optionset 0, option B 151 151 #define CR1_OLEVEL_CPLD_CTRL0 0x00000008 152 152 #define CR1_OLEVEL_CPLD_CTRL1 0x00000010 153 #define CR1_INPUT 1_FRONT 0x00000020154 #define CR1_INPUT 1_REAR 0x00000040155 #define CR1_INPUT 2_FRONT 0x00000080156 #define CR1_INPUT 2_REAR 0x00000100153 #define CR1_INPUT_OPT1_A 0x00000020 // Input optionset 1, option A 154 #define CR1_INPUT_OPT1_B 0x00000040 // Input optionset 1, option B 155 #define CR1_INPUT_OPT2_A 0x00000080 // Input optionset 2, option A 156 #define CR1_INPUT_OPT2_B 0x00000100 // Input optionset 2, option B 157 157 #define CR1_INSTR_DRIVE 0x00000200 158 #define CR1_ ZEROBIT10 0x00000400159 #define CR1_INPUT 0_FRONT 0x00000800158 #define CR1_INPUT_OPT0_A1 0x00000400 // Input optionset 0, option A bit 1 159 #define CR1_INPUT_OPT0_A0 0x00000800 // Input optionset 0, option A bit 0 160 160 161 161 #define CR1_ILEVEL_CPLD_LOGAIN 0 … … 165 165 #define CR1_OLEVEL_CPLD_HIGAIN CR1_OLEVEL_CPLD_CTRL1 166 166 #define CR1_OLEVEL_CPLD_4dBU (CR1_OLEVEL_CPLD_CTRL0 | CR1_OLEVEL_CPLD_CTRL1) 167 #define CR1_FF800_INPUT1_FRONT CR1_INPUT0_FRONT 168 #define CR1_FF800_INPUT1_REAR CR1_INPUT0_REAR 169 #define CR1_FF800_INPUT7_FRONT CR1_INPUT1_FRONT 170 #define CR1_FF800_INPUT7_REAR CR1_INPUT1_REAR 171 #define CR1_FF800_INPUT8_FRONT CR1_INPUT2_FRONT 172 #define CR1_FF800_INPUT8_REAR CR1_INPUT2_REAR 167 #define CR1_FF800_INPUT7_FRONT CR1_INPUT_OPT1_A 168 #define CR1_FF800_INPUT7_REAR CR1_INPUT_OPT1_B 169 #define CR1_FF800_INPUT8_FRONT CR1_INPUT_OPT2_A 170 #define CR1_FF800_INPUT8_REAR CR1_INPUT_OPT2_B 171 #define CR1_FF400_INPUT3_INSTR CR1_INPUT_OPT1_B // To be confirmed 172 #define CR1_FF400_INPUT3_PAD CR1_INPUT_OPT1_A // To be confirmed 173 #define CR1_FF400_INPUT4_INSTR CR1_INPUT_OPT2_B // To be confirmed 174 #define CR1_FF400_INPUT4_PAD CR1_INPUT_OPT2_A // To be confirmed 175 176 // The input 1 "front" option is strange on the FF800 in that it is 177 // indicated using two bits. The actual bit set depends, curiously enough, 178 // on the "speaker emulation" (aka "filter") setting. How odd. 179 #define CR1_FF800_INPUT1_FRONT CR1_INPUT_OPT0_A0 180 #define CR1_FF800_INPUT1_FRONT_WITH_FILTER CR1_INPUT_OPT0_A1 181 #define CR1_FF800_INPUT1_REAR CR1_INPUT_OPT0_B 173 182 174 183 // Configuration register 2 175 #define CR2_CLOCKMODE_ MASTER0x00000000176 #define CR2_CLOCKMODE_ AUTOSYNC0x00000001184 #define CR2_CLOCKMODE_AUTOSYNC 0x00000000 185 #define CR2_CLOCKMODE_MASTER 0x00000001 177 186 #define CR2_FREQ0 0x00000002 178 187 #define CR2_FREQ1 0x00000004 … … 182 191 #define CR2_SPDIF_OUT_EMP 0x00000040 183 192 #define CR2_SPDIF_OUT_NONAUDIO 0x00000080 184 #define CR2_SPDIF_OUT_ADAT2 0x00000100 193 #define CR2_SPDIF_OUT_ADAT2 0x00000100 // Optical SPDIF on ADAT2 port 185 194 #define CR2_SPDIF_IN_COAX 0x00000000 186 #define CR2_SPDIF_IN_ADAT2 0x00000200 195 #define CR2_SPDIF_IN_ADAT2 0x00000200 // Optical SPDIF on ADAT2 port 187 196 #define CR2_SYNC_REF0 0x00000400 188 197 #define CR2_SYNC_REF1 0x00000800 … … 190 199 #define CR2_WORD_CLOCK_1x 0x00002000 191 200 #define CR2_TOGGLE_TCO 0x00004000 // Normally set to 0 192 #define CR2_P12DB_AN0 0x00010000 // Normally set to 0201 #define CR2_P12DB_AN0 0x00010000 // Disable soft-limiter. Normally set to 0 193 202 #define CR2_FF400_BIT 0x04000000 // Set on FF400, clear on FF800 194 203 #define CR2_TMS 0x40000000 // Unit option, normally 0 … … 200 209 #define CR2_SYNC_WORDCLOCK (CR2_SYNC_REF2) 201 210 #define CR2_SYNC_TCO (CR2_SYNC_REF0 | CR2_SYNC_REF2) 211 #define CR2_DISABLE_LIMITER CR2_P12DB_AN0 202 212 203 213 /* Structure used to store device settings in the device flash RAM. This … … 251 261 } FF_device_flash_settings_t; 252 262 253 // Defines used to interpret device flash settings 263 // Defines used to interpret device flash settings. These appear to be 264 // arbitary from the device's perspective since the device doesn't appear to 265 // directly use these stored settings. The driver loads the flash settings 266 // and then uses them to infer the appropriate values for the configuration 267 // registers. The actual values used here appear to correspond more or less 268 // to the "value" returns from the GUI elements used to represent the 269 // controls under other systems. 254 270 #define FF_DEV_FLASH_INVALID 0xffffffff 255 #define FF_DEV_FLASH_SPDIF_INPUT_COAX 0x0000000 1// To be confirmed256 #define FF_DEV_FLASH_SPDIF_INPUT_OPTICAL 0x0000000 0// To be confirmed271 #define FF_DEV_FLASH_SPDIF_INPUT_COAX 0x00000002 // To be confirmed 272 #define FF_DEV_FLASH_SPDIF_INPUT_OPTICAL 0x00000001 // To be confirmed 257 273 #define FF_DEV_FLASH_SPDIF_OUTPUT_COAX 0x00000000 // To be confirmed 258 274 #define FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL 0x00000001 // To be confirmed … … 260 276 #define FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON 0x00000001 261 277 #define FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON 0x00000001 262 #define FF_DEV_FLASH_CLOCK_MODE_MASTER 0x00000000 278 #define FF_DEV_FLASH_CLOCK_MODE_MASTER 0x00000002 279 #define FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC 0x00000001 263 280 #define FF_DEV_FLASH_CLOCK_MODE_SLAVE 0x00000001 281 #define FF_DEV_FLASH_SYNCREF_WORDCLOCK 0x00000001 282 #define FF_DEV_FLASH_SYNCREF_ADAT1 0x00000002 283 #define FF_DEV_FLASH_SYNCREF_ADAT2 0x00000003 284 #define FF_DEV_FLASH_SYNCREF_SPDIF 0x00000004 285 #define FF_DEV_FLASH_SYNCREC_TCO 0x00000005 286 #define FF_DEV_FLASH_ILEVEL_LOGAIN 0x00000001 287 #define FF_DEV_FLASH_ILEVEL_4dBU 0x00000002 288 #define FF_DEV_FLASH_ILEVEL_m10dBV 0x00000003 289 #define FF_DEV_FLASH_OLEVEL_HIGAIN 0x00000001 290 #define FF_DEV_FLASH_OLEVEL_4dBU 0x00000002 291 #define FF_DEV_FLASH_OLEVEL_m10dBV 0x00000003 264 292 #define FF_DEV_FLASH_MIC_PHANTOM_ON 0x00000001 293 #define FF_DEV_FLAS_WORD_CLOCK_1x 0x00000001 265 294 266 295 // Structure used by FFADO to keep track of the device status. This is … … 287 316 uint32_t filter; 288 317 uint32_t fuzz; 318 uint32_t limiter_disable; 289 319 uint32_t sample_rate; 290 320 uint32_t word_clock_single_speed; 321 uint32_t phones_level; // No equivalent in device flash 322 uint32_t input_opt[3]; // No equivalent in device flash 291 323 } FF_software_settings_t; 292 324 325 // Defines used to interpret the software settings structure. For now we 326 // use the same values as used by the device flash settings to remove the 327 // need for translation between reading the flash and copying it to the 328 // software settings structure, but in principle different values could be 329 // used given translation code. 330 #define FF_SWPARAM_INVALID FF_DEV_FLASH_INVALID 331 #define FF_SWPARAM_SPDIF_INPUT_COAX FF_DEV_FLASH_SPDIF_INPUT_COAX 332 #define FF_SWPARAM_SPDIF_INPUT_OPTICAL FF_DEV_FLASH_SPDIF_INPUT_OPTICAL 333 #define FF_SWPARAM_SPDIF_OUTPUT_COAX FF_DEV_FLASH_SPDIF_OUTPUT_COAX 334 #define FF_SWPARAM_SPDIF_OUTPUT_OPTICAL FF_DEV_FLASH_SPDIF_OUTPUT_OPTICAL 335 #define FF_SWPARAM_SPDIF_OUTPUT_EMPHASIS_ON FF_DEV_FLASH_SPDIF_OUTPUT_EMPHASIS_ON 336 #define FF_SWPARAM_SPDIF_OUTPUT_PRO_ON FF_DEV_FLASH_SPDIF_OUTPUT_PRO_ON 337 #define FF_SWPARAM_SPDIF_OUTPUT_NONAUDIO_ON FF_DEV_FLASH_SPDIF_OUTPUT_NONAUDIO_ON 338 #define FF_SWPARAM_SPDIF_CLOCK_MODE_MASTER FF_DEV_FLASH_CLOCK_MODE_MASTER 339 #define FF_SWPARAM_SPDIF_CLOCK_MODE_AUTOSYNC FF_DEV_FLASH_CLOCK_MODE_AUTOSYNC 340 #define FF_SWPARAM_SPDIF_CLOCK_MODE_SLAVE FF_DEV_FLASH_CLOCK_MODE_SLAVE 341 #define FF_SWPARAM_SYNCREF_WORDCLOCK FF_DEV_FLASH_SYNCREF_WORDCLOCK 342 #define FF_SWPARAM_SYNCREF_ADAT1 FF_DEV_FLASH_SYNCREF_ADAT1 343 #define FF_SWPARAM_SYNCREF_ADAT2 FF_DEV_FLASH_SYNCREF_ADAT2 344 #define FF_SWPARAM_SYNCREF_SPDIF FF_DEV_FLASH_SYNCREF_SPDIF 345 #define FF_SWPARAM_SYNCREC_TCO FF_DEV_FLASH_SYNCREC_TCO 346 #define FF_SWPARAM_ILEVEL_LOGAIN FF_DEV_FLASH_ILEVEL_LOGAIN 347 #define FF_SWPARAM_ILEVEL_4dBU FF_DEV_FLASH_ILEVEL_4dBU 348 #define FF_SWPARAM_ILEVEL_m10dBV FF_DEV_FLASH_ILEVEL_m10dBV 349 #define FF_SWPARAM_OLEVEL_HIGAIN FF_DEV_FLASH_OLEVEL_HIGAIN 350 #define FF_SWPARAM_OLEVEL_4dBU FF_DEV_FLASH_OLEVEL_4dBU 351 #define FF_SWPARAM_OLEVEL_m10dBV FF_DEV_FLASH_OLEVEL_m10dBV 352 #define FF_SWPARAM_MIC_PHANTOM_ON FF_DEV_FLASH_MIC_PHANTOM_ON 353 #define FF_SWPARAM_WORD_CLOCK_1x FF_DEV_FLAS_WORD_CLOCK_1x 354 // 355 // The following defines refer to fields in the software parameter record which have no 356 // equivalent in the device flash. 357 #define FF_SWPARAM_PHONESLEVEL_HIGAIN 0x00000001 358 #define FF_SWPARAM_PHONESLEVEL_4dBU 0x00000002 359 #define FF_SWPARAM_PHONESLEVEL_m10dBV 0x00000003 360 #define FF_SWPARAM_INPUT_OPT_B 0x00000001 361 #define FF_SWPARAM_INPUT_OPT_A 0x00000002 362 363 #define FF_SWPARAM_FF800_INPUT_OPT_FRONT FF_SWPARAM_INPUT_OPT_A 364 #define FF_SWPARAM_FF800_INPUT_OPT_REAR FF_SWPARAM_INPUT_OPT_B 293 365 #endif trunk/libffado/src/rme/fireface_hw.cpp
r1553 r1570 53 53 data[0] |= CR0_PHANTOM_MIC3; 54 54 55 /* Phones level */ 56 switch (settings.phones_level) { 57 case FF_SWPARAM_PHONESLEVEL_HIGAIN: 58 data[0] |= CRO_PHLEVEL_HIGAIN; 59 break; 60 case FF_SWPARAM_PHONESLEVEL_4dBU: 61 data[0] |= CR0_PHLEVEL_4dBU; 62 break; 63 case FF_SWPARAM_PHONESLEVEL_m10dBV: 64 data[0] |= CRO_PHLEVEL_m10dBV; 65 break; 66 } 67 55 68 /* Input level */ 56 69 switch (settings.input_level) { 57 case 1: // Low gain70 case FF_SWPARAM_ILEVEL_LOGAIN: // Low gain 58 71 data[1] |= CR1_ILEVEL_CPLD_LOGAIN; // CPLD 59 72 data[0] |= CR0_ILEVEL_FPGA_LOGAIN; // LED control (used on FF800 only) 60 73 break; 61 case 2:// +4 dBu74 case FF_SWPARAM_ILEVEL_4dBU: // +4 dBu 62 75 data[1] |= CR1_ILEVEL_CPLD_4dBU; 63 76 data[0] |= CR0_ILEVEL_FPGA_4dBU; 64 77 break; 65 case 3: // -10 dBV78 case FF_SWPARAM_ILEVEL_m10dBV: // -10 dBV 66 79 data[1] |= CR1_ILEVEL_CPLD_m10dBV; 67 80 data[0] |= CR0_ILEVEL_FPGA_m10dBV; … … 71 84 /* Output level */ 72 85 switch (settings.output_level) { 73 case 1: // High gain86 case FF_SWPARAM_OLEVEL_HIGAIN: // High gain 74 87 data[1] |= CR1_OLEVEL_CPLD_HIGAIN; // CPLD 75 88 data[0] |= CR0_OLEVEL_FPGA_HIGAIN; // LED control (used on FF800 only) 76 89 break; 77 case 2:// +4 dBu90 case FF_SWPARAM_OLEVEL_4dBU: // +4 dBu 78 91 data[1] |= CR1_OLEVEL_CPLD_4dBU; 79 92 data[0] |= CR0_OLEVEL_FPGA_4dBU; 80 93 break; 81 case 3: // -10 dBV94 case FF_SWPARAM_OLEVEL_m10dBV: // -10 dBV 82 95 data[1] |= CR1_OLEVEL_CPLD_m10dBV; 83 96 data[0] |= CR0_OLEVEL_FPGA_m10dBV; … … 85 98 } 86 99 87 /* S peaker emulation / filter FIXME: needs filling out, is tied in88 * with analog input settings.100 /* Set input options. The meaning of the options differs between 101 * devices, so we use the generic identifiers here. 89 102 */ 90 data[1] = 0xf; 103 data[1] |= (settings.input_opt[1] & FF_SWPARAM_INPUT_OPT_A) ? CR1_INPUT_OPT1_A : 0; 104 data[1] |= (settings.input_opt[1] & FF_SWPARAM_INPUT_OPT_B) ? CR1_INPUT_OPT1_B : 0; 105 data[1] |= (settings.input_opt[2] & FF_SWPARAM_INPUT_OPT_A) ? CR1_INPUT_OPT2_A : 0; 106 data[1] |= (settings.input_opt[2] & FF_SWPARAM_INPUT_OPT_B) ? CR1_INPUT_OPT2_B : 0; 107 108 // Drive the speaker emulation / filter LED via FPGA 109 data[0] |= (settings.filter) ? CR0_FILTER_FPGA : 0; 110 111 // Set the "rear" option for input 0 if selected 112 data[1] |= (settings.input_opt[0] & FF_SWPARAM_FF800_INPUT_OPT_REAR) ? CR1_FF800_INPUT1_REAR : 0; 113 114 // The input 0 "front" option is activated using one of two bits 115 // depending on whether the filter (aka "speaker emulation") setting is 116 // active. 117 if (settings.input_opt[0] & FF_SWPARAM_FF800_INPUT_OPT_FRONT) { 118 data[1] |= (settings.filter) ? CR1_FF800_INPUT1_FRONT_WITH_FILTER : CR1_FF800_INPUT1_FRONT; 119 } 120 121 data[2] |= (settings.spdif_output_emphasis==FF_SWPARAM_SPDIF_OUTPUT_EMPHASIS_ON) ? CR2_SPDIF_OUT_EMP : 0; 122 data[2] |= (settings.spdif_output_pro==FF_SWPARAM_SPDIF_OUTPUT_PRO_ON) ? CR2_SPDIF_OUT_PRO : 0; 123 data[2] |= (settings.spdif_output_nonaudio==FF_SWPARAM_SPDIF_OUTPUT_NONAUDIO_ON) ? CR2_SPDIF_OUT_NONAUDIO : 0; 124 data[2] |= (settings.spdif_output_mode==FF_SWPARAM_SPDIF_OUTPUT_OPTICAL) ? CR2_SPDIF_OUT_ADAT2 : 0; 125 data[2] |= (settings.clock_mode==FF_SWPARAM_SPDIF_CLOCK_MODE_AUTOSYNC) ? CR2_CLOCKMODE_AUTOSYNC : CR2_CLOCKMODE_MASTER; 126 data[2] |= (settings.spdif_input_mode==FF_SWPARAM_SPDIF_INPUT_COAX) ? CR2_SPDIF_IN_COAX : CR2_SPDIF_IN_ADAT2; 127 data[2] |= (settings.word_clock_single_speed=FF_SWPARAM_WORD_CLOCK_1x) ? CR2_WORD_CLOCK_1x : 0; 128 129 /* TMS / TCO toggle bits in CR2 are not set by other drivers */ 91 130 92 131 /* Drive / fuzz */ … … 96 135 data[1] |= CR1_INSTR_DRIVE; // CPLD 97 136 98 /* Drop-and-stop is hardwired on */137 /* Drop-and-stop is hardwired on in other drivers */ 99 138 data[2] |= CR2_DROP_AND_STOP; 100 139 … … 103 142 } 104 143 144 switch (settings.sync_ref) { 145 case FF_SWPARAM_SYNCREF_WORDCLOCK: 146 data[2] |= CR2_SYNC_WORDCLOCK; 147 break; 148 case FF_SWPARAM_SYNCREF_ADAT1: 149 data[2] |= CR2_SYNC_ADAT1; 150 break; 151 case FF_SWPARAM_SYNCREF_ADAT2: 152 data[2] |= CR2_SYNC_ADAT2; 153 break; 154 case FF_SWPARAM_SYNCREF_SPDIF: 155 data[2] |= CR2_SYNC_SPDIF; 156 break; 157 case FF_SWPARAM_SYNCREC_TCO: 158 data[2] |= CR2_SYNC_TCO; 159 break; 160 } 161 162 // This is hardwired in other drivers 105 163 data[2] |= (CR2_FREQ0 + CR2_FREQ1 + CR2_DSPEED + CR2_QSSPEED); 106 164 165 data[2] |= (settings.limiter_disable && 166 (settings.input_opt[0] & FF_SWPARAM_FF800_INPUT_OPT_FRONT)) ? 167 CR2_DISABLE_LIMITER : 0; 168 169 //This is just for testing - it's a known consistent configuration 107 170 //data[0] = 0x00020811; // Phantom off 108 171 data[0] = 0x00020811; // Phantom on
