Changeset 1572

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Timestamp:
06/08/09 06:08:29 (15 years ago)
Author:
jwoithe
Message:

RME: more register address/value defines, mostly associated with the TCO

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  • trunk/libffado/src/rme/fireface_def.h

    r1570 r1572  
    7373#define RME_FF_STATUS_REG1           0x801c0004    // Read only 
    7474 
     75#define RME_FF_TCO_READ_REG          0x801f0000 
     76#define RME_FF_TCO_WRITE_REG         0x810f0020 
     77 
    7578/* Addresses of various blocks in memory-mapped flash */ 
    7679#define RME_FF400_FLASH_SETTINGS_ADDR       0x00060000 
     
    9295#define RME_FF400_FLASH_READ_BUFFER         0x80100290 
    9396 
    94 /* Erase control registers on the FF800 */ 
     97/* Flash erase control registers on the FF800 */ 
    9598#define RME_FF800_FLASH_ERASE_VOLUME_REG    0x3fffffff4LL 
    9699#define RME_FF800_FLASH_ERASE_SETTINGS_REG  0x3fffffff0LL 
     
    210213#define CR2_SYNC_TCO            (CR2_SYNC_REF0 | CR2_SYNC_REF2) 
    211214#define CR2_DISABLE_LIMITER     CR2_P12DB_AN0 
     215 
     216/* Defines for the status registers */ 
     217// Status register 0 
     218#define SR0_ADAT1_LOCK          0x00000400 
     219#define SR0_ADAT2_LOCK          0x00000800 
     220#define SR0_ADAT1_SYNC          0x00001000 
     221#define SR0_ADAT2_SYNC          0x00002000 
     222#define SR0_F0                  0x00004000 
     223#define SR0_F1                  0x00008000 
     224#define SR0_F2                  0x00010000 
     225#define SR0_F3                  0x00020000 
     226#define SR0_SPDIF_SYNC          0x00040000 
     227#define SR0_OVER                0x00080000 
     228#define SR0_SPDIF_LOCK          0x00100000 
     229#define SR0_SEL_SYNC_REF0       0x00200000 
     230#define SR0_SEL_SYNC_REF1       0x00400000 
     231#define SR0_SEL_SYNC_REF2       0x01000000 
     232#define SR0_INP_FREQ0           0x02000000 
     233#define SR0_INP_FREQ0           0x04000000 
     234#define SR0_INP_FREQ0           0x08000000 
     235#define SR0_INP_FREQ0           0x10000000 
     236#define SR0_WC_SYNC             0x20000000 
     237#define SR0_WC_LOCK             0x40000000 
     238 
     239// Status register 1 
     240#define SR1_TCO_LOCK            0x00800000 
     241#define SR1_TCO_SYNC            0x00400000 
    212242 
    213243/* Structure used to store device settings in the device flash RAM.  This 
     
    363393#define FF_SWPARAM_FF800_INPUT_OPT_FRONT       FF_SWPARAM_INPUT_OPT_A 
    364394#define FF_SWPARAM_FF800_INPUT_OPT_REAR        FF_SWPARAM_INPUT_OPT_B 
     395 
     396// Data structure for the TCO (Time Code Option) state 
     397typedef struct { 
     398    uint32_t input; 
     399    uint32_t frame_rate; 
     400    uint32_t word_clock; 
     401    uint32_t sample_rate; 
     402    uint32_t pull; 
     403    uint32_t termination; 
     404    uint32_t MTC; 
     405} FF_TCO_settings_t; 
     406 
     407// Defines used to configure selected quadlets of the TCO write space.  The 
     408// byte indices referenced in the define names are 0-based. 
     409#define FF_TCO1_TCO_lock                      0x00000001 
     410 
    365411#endif