Changeset 1592
- Timestamp:
- 07/09/09 05:42:30 (14 years ago)
- Files:
-
- trunk/libffado/src/rme/fireface_def.h (modified) (4 diffs)
- trunk/libffado/src/rme/fireface_hw.cpp (modified) (3 diffs)
- trunk/libffado/src/rme/rme_avdevice.cpp (modified) (4 diffs)
- trunk/libffado/src/rme/rme_avdevice.h (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
- Modified
- Copied
- Moved
trunk/libffado/src/rme/fireface_def.h
r1590 r1592 36 36 #define RME_FF800 1 37 37 38 #define MIN_SPEED 30000 39 #define MIN_DOUBLE_SPEED 56000 40 #define MIN_QUAD_SPEED 112000 41 #define MAX_SPEED 210000 42 38 43 /* The Command Buffer Address (CBA) is different for the two interfaces */ 39 44 #define RME_FF400_CMD_BUFFER 0x80100500 … … 220 225 /* Defines for the status registers */ 221 226 // Status register 0 227 #define SR0_IS_STREAMING 0x00000001 222 228 #define SR0_ADAT1_LOCK 0x00000400 223 229 #define SR0_ADAT2_LOCK 0x00000800 224 230 #define SR0_ADAT1_SYNC 0x00001000 225 231 #define SR0_ADAT2_SYNC 0x00002000 226 #define SR0_ F00x00004000227 #define SR0_ F10x00008000228 #define SR0_ F20x00010000229 #define SR0_ F30x00020000232 #define SR0_SPDIF_F0 0x00004000 233 #define SR0_SPDIF_F1 0x00008000 234 #define SR0_SPDIF_F2 0x00010000 235 #define SR0_SPDIF_F3 0x00020000 230 236 #define SR0_SPDIF_SYNC 0x00040000 231 237 #define SR0_OVER 0x00080000 … … 241 247 #define SR0_WC_LOCK 0x40000000 242 248 249 #define SR0_ADAT1_STATUS_MASK (SR0_ADAT1_LOCK|SR0_ADAT1_SYNC) 250 #define SR0_ADAT1_STATUS_NOLOCK 0 251 #define SR0_ADAT1_STATUS_LOCK SR0_ADAT1_LOCK 252 #define SR0_ADAT1_STATUS_SYNC (SR0_ADAT1_LOCK|SR0_ADAT1_SYNC) 253 #define SR0_ADAT2_STATUS_MASK (SR0_ADAT2_LOCK|SR0_ADAT2_SYNC) 254 #define SR0_ADAT2_STATUS_NOLOCK 0 255 #define SR0_ADAT2_STATUS_LOCK SR0_ADAT2_LOCK 256 #define SR0_ADAT2_STATUS_SYNC (SR0_ADAT2_LOCK|SR0_ADAT2_SYNC) 257 #define SR0_SPDIF_STATUS_MASK (SR0_SPDIF_LOCK|SR0_SPDIF_SYNC) 258 #define SR0_SPDIF_STATUS_NOLOCK 0 259 #define SR0_SPDIF_STATUS_LOCK SR0_SPDIF_LOCK 260 #define SR0_SPDIF_STATUS_SYNC (SR0_SPDIF_LOCK|SR0_SPDIF_SYNC) 261 #define SR0_WCLK_STATUS_MASK (SR0_WCLK_LOCK|SR0_WCLK_SYNC) 262 #define SR0_WCLK_STATUS_NOLOCK 0 263 #define SR0_WCLK_STATUS_LOCK SR0_WCLK_LOCK 264 #define SR0_WCLK_STATUS_SYNC (SR0_WCLK_LOCK|SR0_WCLK_SYNC) 265 266 #define SR0_AUTOSYNC_SRC_MASK (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF1|SR0_SEL_SYNC_REF2) 267 #define SR0_AUTOSYNC_SRC_ADAT1 0 268 #define SR0_AUTOSYNC_SRC_ADAT2 SR0_SEL_SYNC_REF0 269 #define SR0_AUTOSYNC_SRC_SPDIF (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF1) 270 #define SR0_AUTOSYNC_SRC_WCLK SR0_SEL_SYNC_REF2 271 #define SR0_AUTOSYNC_SRC_TCO (SR0_SEL_SYNC_REF0|SR0_SEL_SYNC_REF2) 272 273 #define SR0_AUTOSYNC_FREQ_MASK (SR0_INP_FREQ0|SR0_INP_FREQ1|SR0_INP_FREQ2|SR0_INP_FREQ3) 274 #define SR0_AUTOSYNC_FREQ_32k SR0_INP_FREQ0 275 #define SR0_AUTOSYNC_FREQ_44k1 SR0_INP_FREQ1 276 #define SR0_AUTOSYNC_FREQ_48k (SR0_INP_FREQ0|SR0_INP_FREQ1) 277 #define SR0_AUTOSYNC_FREQ_64k SR0_INP_FREQ2 278 #define SR0_AUTOSYNC_FREQ_88k2 (SR0_INP_FREQ0|SR0_INP_FREQ2) 279 #define SR0_AUTOSYNC_FREQ_96k (SR0_INP_FREQ1|SR0_INP_FREQ2) 280 #define SR0_AUTOSYNC_FREQ_128k (SR0_INP_FREQ0|SR0_INP_FREQ1|SR0_INP_FREQ2) 281 #define SR0_AUTOSYNC_FREQ_176k4 SR0_INP_FREQ3 282 #define SR0_AUTOSYNC_FREQ_192k (SR0_INP_FREQ0|SR0_INP_FREQ3) 283 243 284 // Status register 1 244 285 #define SR1_TCO_LOCK 0x00800000 245 286 #define SR1_TCO_SYNC 0x00400000 287 288 #define SR0_TCO_STATUS_MASK (SR0_TCO_LOCK|SR0_TCO_SYNC) 289 #define SR0_TCO_STATUS_NOLOCK 0 290 #define SR0_TCO_STATUS_LOCK SR0_TCO_LOCK 291 #define SR0_TCO_STATUS_SYNC (SR0_TCO_LOCK|SR0_TCO_SYNC) 246 292 247 293 /* Structure used to store device settings in the device flash RAM. This … … 401 447 #define FF_SWPARAM_FF800_INPUT_OPT_REAR FF_SWPARAM_INPUT_OPT_B 402 448 449 // The general Fireface state 450 typedef struct { 451 uint32_t clock_mode; 452 uint32_t autosync_source; 453 uint32_t autosync_freq; 454 uint32_t spdif_freq; 455 uint32_t adat1_sync_status, adat2_sync_status; 456 uint32_t spdif_sync_status; 457 uint32_t wclk_sync_status, tco_sync_status; 458 } FF_state_t; 459 460 #define FF_STATE_CLOCKMODE_MASTER 0 461 #define FF_STATE_CLOCKMODE_AUTOSYNC 1 462 #define FF_STATE_AUTOSYNC_SRC_ADAT1 0x01 463 #define FF_STATE_AUTOSYNC_SRC_ADAT2 0x02 464 #define FF_STATE_AUTOSYNC_SRC_SPDIF 0x03 465 #define FF_STATE_AUTOSYNC_SRC_WCLK 0x04 466 #define FF_STATE_AUTOSYNC_SRC_TCO 0x15 467 #define FF_STATE_SYNC_LOCKED 1 468 #define FF_STATE_SYNC_SYNCED 2 469 403 470 // Data structure for the TCO (Time Code Option) state 404 471 typedef struct { trunk/libffado/src/rme/fireface_hw.cpp
r1587 r1592 28 28 29 29 #include "debugmodule/debugmodule.h" 30 31 unsigned int multiplier(unsigned int freq) { 32 if (freq > MIN_QUAD_SPEED) 33 return 4; 34 if (freq > MIN_DOUBLE_SPEED) 35 return 2; 36 return 1; 37 } 30 38 31 39 namespace Rme { … … 52 60 } 53 61 62 signed int 63 Device::get_hardware_status(unsigned int *stat0, unsigned int *stat1) 64 { 65 unsigned int buf[2]; 66 if (readBlock(RME_FF_STATUS_REG0, buf, 2) != 0) 67 return -1; 68 *stat0 = buf[0]; 69 *stat1 = buf[1]; 70 return 0; 71 } 72 54 73 signed int 55 74 Device::set_hardware_params(FF_software_settings_t *sw_settings) … … 400 419 } 401 420 402 } 421 signed int 422 Device::set_hardware_dds_freq(signed int freq) 423 { 424 // Set the device's DDS to the given frequency (which in turn determines 425 // the sampling frequency). Returns 0 on success, -1 on error. 426 427 unsigned int ret = 0; 428 429 if (freq < MIN_SPEED || freq > MAX_SPEED) 430 return -1; 431 432 if (m_rme_model == RME_MODEL_FIREFACE400) 433 ret = writeRegister(RME_FF400_STREAM_SRATE, freq); 434 else 435 ret = writeRegister(RME_FF800_STREAM_SRATE, freq); 436 437 return ret; 438 } 439 440 } trunk/libffado/src/rme/rme_avdevice.cpp
r1589 r1592 96 96 : FFADODevice( d, configRom ) 97 97 , m_rme_model( RME_MODEL_NONE ) 98 , m_ddsFreq( -1 ) 99 , m_streaming_freq( -1 ) 98 , is_streaming( 0 ) 99 , m_dds_freq( -1 ) 100 , m_software_freq( -1 ) 100 101 , tco_present( 0 ) 101 102 { … … 200 201 * (the default value of m_ddsFreq). 201 202 */ 202 return m_s treaming_freq;203 return m_software_freq; 203 204 } 204 205 … … 212 213 Device::setSamplingFrequency( int samplingFrequency ) 213 214 { 214 /* 215 * Set the RME device's samplerate. The RME can do sampling frequencies of 216 * 32k, 44.1k and 48k along with the corresponding 2x and 4x rates. 217 * However, it can also do +/- 4% from any of these "base" frequencies using 218 * its DDS. This makes it a little long-winded to work out whether a given 219 * frequency is supported or not. 220 * 221 * This function is concerned with setting the device up for streaming, so the 222 * register we want to write to is in fact the streaming sample rate portion of 223 * the streaming initialisation function (as opposed to the DDS frequency register 224 * which is distinct on the FF800. How the FF800's DDS register will ultimately 225 * be controlled is yet to be determined. 226 */ 227 bool ret; 215 // Request a sampling rate on behalf of software. Software is limited 216 // to sample rates of 32k, 44.1k, 48k and the 2x/4x multiples of these. 217 // The user may lock the device to a much wider range of frequencies via 218 // the explicit DDS controls in the control panel. If the explicit DDS 219 // control is active the software is limited to the "standard" speeds 220 // corresponding to the multiplier in use by the DDS. 221 // 222 // Similarly, if the device is externally clocked the software is 223 // limited to the external clock frequency. 224 // 225 // Otherwise the software has free choice of the software speeds noted 226 // above. 227 228 bool ret = -1; 229 signed int i, j; 230 signed int mult[3] = {1, 2, 4}; 231 signed int freq[3] = {32000, 44100, 48000}; 228 232 229 233 /* Work out whether the requested rate is supported */ 230 /* FIXME: the +/- 4% range is only doable if the DDS is engaged */ 231 if (!((samplingFrequency >= 32000*0.96 && samplingFrequency <= 32000*1.04) || 232 (samplingFrequency >= 44100*0.96 && samplingFrequency <= 44100*1.04) || 233 (samplingFrequency >= 48000*0.96 && samplingFrequency <= 48000*1.04) || 234 (samplingFrequency >= 64000*0.96 && samplingFrequency <= 64000*1.04) || 235 (samplingFrequency >= 88200*0.96 && samplingFrequency <= 88200*1.04) || 236 (samplingFrequency >= 96000*0.96 && samplingFrequency <= 96000*1.04) || 237 (samplingFrequency >= 128000*0.96 && samplingFrequency <= 128000*1.04) || 238 (samplingFrequency >= 176000*0.96 && samplingFrequency <= 176000*1.04) || 239 (samplingFrequency >= 192000*0.96 && samplingFrequency <= 192000*1.04))) { 234 for (i=0; i<3; i++) { 235 for (j=0; j<3; i++) { 236 if (samplingFrequency==freq[j]*mult[i]) { 237 ret = 0; 238 break; 239 } 240 } 241 } 242 if (ret == -1) 240 243 return false; 241 } 242 243 /* Send the desired frequency to the RME */ 244 if (m_rme_model == RME_MODEL_FIREFACE400) 245 ret = writeRegister(RME_FF400_STREAM_SRATE, samplingFrequency); 246 else 247 ret = writeRegister(RME_FF800_STREAM_SRATE, samplingFrequency); 248 249 m_streaming_freq = samplingFrequency; 244 245 // FIXME: still have to verify compatibility with current rate if 246 // running, DDS if set or external clock if relevant. 247 248 if (set_hardware_dds_freq(samplingFrequency) != 0) 249 return false; 250 251 m_software_freq = samplingFrequency; 250 252 return true; 251 253 } 252 253 #define RME_CHECK_AND_ADD_SR(v, x) \254 { \255 if (((x >= 32000*0.96 && x <= 32000*1.04) || \256 (x >= 44100*0.96 && x <= 44100*1.04) || \257 (x >= 48000*0.96 && x <= 48000*1.04) || \258 (x >= 64000*0.96 && x <= 64000*1.04) || \259 (x >= 88200*0.96 && x <= 88200*1.04) || \260 (x >= 96000*0.96 && x <= 96000*1.04) || \261 (x >= 128000*0.96 && x <= 128000*1.04) || \262 (x >= 176000*0.96 && x <= 176000*1.04) || \263 (x >= 192000*0.96 && x <= 192000*1.04))) { \264 v.push_back(x); \265 };};266 254 267 255 std::vector<int> … … 269 257 { 270 258 std::vector<int> frequencies; 271 /* FIXME: the +/- 4% frequency range is only doable if the DDS is 272 * engaged. 273 */ 274 RME_CHECK_AND_ADD_SR(frequencies, 32000); 275 RME_CHECK_AND_ADD_SR(frequencies, 44100); 276 RME_CHECK_AND_ADD_SR(frequencies, 48000); 277 RME_CHECK_AND_ADD_SR(frequencies, 64000); 278 RME_CHECK_AND_ADD_SR(frequencies, 88200); 279 RME_CHECK_AND_ADD_SR(frequencies, 96000); 280 RME_CHECK_AND_ADD_SR(frequencies, 128000); 281 RME_CHECK_AND_ADD_SR(frequencies, 176400); 282 RME_CHECK_AND_ADD_SR(frequencies, 192000); 259 signed int i, j; 260 signed int mult[3] = {1, 2, 4}; 261 signed int freq[3] = {32000, 44100, 48000}; 262 263 // Generate the list of supported frequencies 264 // FIXME: this could be limited based on the device's current status 265 for (i=0; i<3; i++) { 266 for (j=0; j<3; i++) { 267 frequencies.push_back(freq[j]*mult[i]); 268 } 269 } 283 270 return frequencies; 284 271 } trunk/libffado/src/rme/rme_avdevice.h
r1589 r1592 91 91 enum ERmeModel m_rme_model; 92 92 93 signed int m_ddsFreq; 94 signed int m_streaming_freq; 93 signed int is_streaming; 94 signed int m_dds_freq; 95 signed int m_software_freq; // Sampling frequency requested by software 95 96 96 97 signed int tco_present; … … 120 121 /* Hardware functions */ 121 122 signed int init_hardware(void); 123 signed int get_hardware_status(unsigned int *stat0, unsigned int *stat1); 122 124 signed int set_hardware_params(FF_software_settings_t *sw_settings); 123 125 signed int read_tco(quadlet_t *tco_data, signed int size); … … 126 128 signed int read_tco_state(FF_TCO_state_t *tco_state); 127 129 signed int write_tco_settings(FF_TCO_settings_t *tco_settings); 128 130 131 signed int set_hardware_dds_freq(signed int freq); 129 132 }; 130 133