Changeset 1596
- Timestamp:
- 07/12/09 06:30:55 (14 years ago)
- Files:
-
- trunk/libffado/doc/rme_notes/rme_config_register_map.txt (modified) (3 diffs)
- trunk/libffado/src/rme/fireface_def.h (modified) (7 diffs)
- trunk/libffado/src/rme/fireface_hw.cpp (modified) (2 diffs)
- trunk/libffado/src/rme/rme_avdevice.cpp (modified) (1 diff)
- trunk/libffado/src/rme/rme_avdevice.h (modified) (3 diffs)
Legend:
- Unmodified
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trunk/libffado/doc/rme_notes/rme_config_register_map.txt
r1590 r1596 2 2 ============================================ 3 3 4 Version: 0.1 14 Version: 0.12 5 5 Author: Jonathan Woithe 6 Date: 27 June20096 Date: 12 July 2009 7 7 8 8 … … 73 73 Sample rate is controlled by writing the desired sample rate in Hz to the 74 74 sample rate control register located at offset 0 from the command buffer 75 address (0xfc88f000 on a FF800). Rates which have been observed are 32k, 76 44.056k, 44.144k, 44.1k, 45.937k, 46.080k, 47.952k, 48k and 48.048k, along 77 with corresponding 2x and 4x rates. This assumes the DDS has been enabled. 78 If DDS is not active it seems the audio system assumes a frequency of 44.1 79 kHz which cannot be changed. The value of disabling the DDS is therefore 80 not entirely understood. 81 82 The PC does not appear to request the device's current sample rate; in fact, 83 it doesn't appear to be available from the device itself (except from the 84 flash device setting record in the case where the DDS has been enabled). 85 When requesting the device status, the sample rate returned is based on the 86 PC's audio engine sample rate so long as the device status has been read 87 without error (if an error occurs the sample rate is hardcoded to 44.1 kHz). 88 It therefore seems that when DDS is in use the PC explicitly sets the device 89 to its desired sample rate and then caches the sample rate locally. If DDS 90 is not active it appears at this stage that the only internally generated 91 sample rate available is 44.1 kHz. 92 93 When using an external clock without DDS it's not clear how the PC works out 94 what sample rate to use. Presumedly it remains at 44.1 kHz. 75 address (0xfc88f000 on a FF800). The hardware DDS allows a wide range of 76 frequencies to be requested (possibly anything from 30 kHz up to 210 kHz). 77 The more common rates are of course 32k, 44.1k, 48k, the pull-up/down rates 78 (44.056k, 44.144k, 45.937k, 46.080k, 47.952k, 48.048k) and the corresponding 79 2x and 4x rates. 80 81 Software connecting to the Fireface device is restricted to the normal rates 82 of 32k, 44.1k, 48k and the related 2x and 4x rates. 83 84 If the device is in master clock mode and the user has not made an explicit 85 DDS setting, the hardware DDS will be determined by the sampling rate 86 requested by the application opening the device. If a DDS frequency has 87 been requested by the user the actual rate used by the device will be that 88 DDS frequency regardless of what the application has asked for. In this 89 case a device open will only succeed if the software has requested a speed 90 whose multiplier matches the DDS configuration. 91 92 If the device is locked to an external clock, a device open will succeed 93 only if the multiplier of the requested sampling rate matches that of the 94 external rate. 95 96 The device status registers allow the PC to determine the sampling rate when 97 an external clock is in use. However, there is no way to read the sampling 98 rate when in master clock mode. It is therefore necessary to cache this in 99 the driver so it can be provided when requested. 95 100 96 101 In terms of multipliers the RME treats sample rates greater than 112000 Hz 97 102 as 4x rates, with rates greater than 56000 Hz as 2x rates. Rates less than 98 103 30000 Hz and greater than 210000 Hz are invalid. 99 100 It is not yet known how the driver works out that the DDS is active since101 the device flash settings are not read and in any case, if the device flash102 settings have not been set they won't indicate anything useful about the103 current device state.104 104 105 105 … … 195 195 On the FF400, writing to these registers with valid values for the first 196 196 time after power up has the side effect of extingishing the "Host" LED. 197 198 199 Device status registers 200 ----------------------- 201 202 There are up to 4 read-only device status registers available, starting at 203 address 0x801c0000. There seems to be a slight difference in the mapping of 204 status register 0 depending on the size of the read. If only 2 registers 205 (quadlets) are read the "general" layout is assumed. If on the other hand 4 206 registers are used (used when determining the status of the device's 207 streaming system) the layout of register 0 is slightly different. 208 209 Status register 0: 210 bit 0: on a 2-quadlet read, this indicates whether the device is streaming 211 bits 1-9: on a 2-quadlet read these bits are all zero 212 bits 9-0: on a 4-quadlet read when in autosync mode, these bits contain 213 SR/250, where SR is the sample rate to be passed to the 214 streaming subsystem when starting streaming. 215 bit 10: ADAT1 lock achieved 216 bit 11: ADAT2 lock achieved 217 bit 12: Device is synced to ADAT1 218 bit 13: Device is synced to ADAT2 219 bits 17-14: SPDIF frequency: 220 0000 = undefined 0101 = 88.2k 221 0001 = 32k 0110 = 96k 222 0010 = 44.1k 0111 = 128k 223 0011 = 48k 1000 = 176.4k 224 0100 = 64k 1001 = 192k 225 bit 18: Device is synced to SPDIF 226 bit 19: Over detected 227 bit 20: SPDIF lock achieved 228 bit 21: undefined (read as zero) 229 bits 24-22: Primary sync source: 230 000 = ADAT1 100 = Word clock 231 001 = ADAT2 101 = TCO 232 011 = SPDIF 233 bits 28-25: autosync (external) frequency (defined as for SPDIF frequency) 234 bit 29: Device is synced to word clock 235 bit 30: Word clock lock achieved 236 bit 31: undefined (read as zero) 237 238 Status register 1: 239 bit 0: master clock mode active 240 bits 21-1: undefined 241 bit 22: Device is synced to TCO 242 bit 23: TCO lock achieved 243 bits 31-24: undefined 244 245 Status register 2: 246 bits 31-0: (FF800 only) firewire iso channel used for data from FF800 to PC 247 248 Status register 3: 249 bits 31-0: unused 197 250 198 251 trunk/libffado/src/rme/fireface_def.h
r1594 r1596 41 41 #define MAX_SPEED 210000 42 42 43 // A flag used to indicate the use of a 800 Mbps bus speed to various 44 // streaming registers of the FF800. 45 #define RME_FF800_STREAMING_SPEED_800 0x800 46 43 47 /* The Command Buffer Address (CBA) is different for the two interfaces */ 44 48 #define RME_FF400_CMD_BUFFER 0x80100500 … … 58 62 59 63 #define RME_FF400_STREAM_INIT_REG (RME_FF400_CMD_BUFFER) // 3 quadlets wide 64 #define RME_FF400_STREAM_INIT_SIZE 3 // Size in quadlets 60 65 #define RME_FF400_STREAM_SRATE (RME_FF400_CMD_BUFFER) 61 66 #define RME_FF400_STREAM_CONF0 (RME_FF400_CMD_BUFFER+4) 62 67 #define RME_FF400_STREAM_CONF1 (RME_FF400_CMD_BUFFER+8) 63 68 #define RME_FF800_STREAM_INIT_REG 0x20000001cLL // 3 quadlets wide 69 #define RME_FF800_STREAM_INIT_SIZE 3 // Size in quadlets 64 70 #define RME_FF800_STREAM_SRATE 0x20000001cLL 65 71 #define RME_FF800_STREAM_CONF0 (0x20000001cLL+4) … … 68 74 #define RME_FF800_STREAM_START_REG 0x200000028LL // 1 quadlet 69 75 #define RME_FF400_STREAM_END_REG (RME_FF400_CMD_BUFFER + 0x0004) // 4 quadlets wide 76 #define RME_FF400_STREAM_END_SIZE 4 // Size in quadlets 70 77 #define RME_FF800_STREAM_END_REG 0x200000034LL // 3 quadlets wide 78 #define RME_FF800_STREAM_END_SIZE 3 // Size in quadlets 71 79 72 80 #define RME_FF800_HOST_LED_REG 0x200000324LL … … 225 233 /* Defines for the status registers */ 226 234 // Status register 0 227 #define SR0_IS_STREAMING 0x00000001228 235 #define SR0_ADAT1_LOCK 0x00000400 229 236 #define SR0_ADAT2_LOCK 0x00000800 … … 237 244 #define SR0_OVER 0x00080000 238 245 #define SR0_SPDIF_LOCK 0x00100000 239 #define SR0_SEL_SYNC_REF0 0x00 200000240 #define SR0_SEL_SYNC_REF1 0x00 400000246 #define SR0_SEL_SYNC_REF0 0x00400000 247 #define SR0_SEL_SYNC_REF1 0x00800000 241 248 #define SR0_SEL_SYNC_REF2 0x01000000 242 249 #define SR0_INP_FREQ0 0x02000000 … … 246 253 #define SR0_WCLK_SYNC 0x20000000 247 254 #define SR0_WCLK_LOCK 0x40000000 255 256 // It seems the definition of SR0 is a little different depending on whether 257 // 2 or 4 status registers are read. In the case of a request for 2, the 258 // following additional bits are defined. 259 #define SR0_IS_STREAMING 0x00000001 260 // If 4 quadlets are requested (as is done when checking the streaming 261 // system status), the lowest 10 bits instead represent sample_rate/250 if 262 // locked to an external clock source. 263 #define SR0_STREAMING_FREQ_MASK 0x000003ff 248 264 249 265 #define SR0_ADAT1_STATUS_MASK (SR0_ADAT1_LOCK|SR0_ADAT1_SYNC) … … 292 308 #define SR0_AUTOSYNC_FREQ_176k4 SR0_INP_FREQ3 293 309 #define SR0_AUTOSYNC_FREQ_192k (SR0_INP_FREQ0|SR0_INP_FREQ3) 310 #define SR0_AUTOSYNC_FREQ_NONE 0 294 311 295 312 // Status register 1 313 #define SR1_CLOCK_MODE_MASTER 0x00000001 314 #define SR1_TCO_SYNC 0x00400000 296 315 #define SR1_TCO_LOCK 0x00800000 297 #define SR1_TCO_SYNC 0x00400000298 316 299 317 #define SR1_TCO_STATUS_MASK (SR1_TCO_LOCK|SR1_TCO_SYNC) trunk/libffado/src/rme/fireface_hw.cpp
r1594 r1596 79 79 80 80 signed int 81 Device::get_hardware_streaming_status(unsigned int *stat, unsigned int n) 82 { 83 // Get the hardware status as it applies to the streaming system. This 84 // involves a request of 4 quadlets from the status register. It 85 // appears that the first register's definition is slightly different in 86 // this situation compared to when only 2 quadlets are requested as is 87 // done in get_hardware_status(). 88 // 89 // "n" is the size of the passed-in stat array. It must be >= 4. 90 if (n < 4) 91 return -1; 92 if (readBlock(RME_FF_STATUS_REG0, stat, 4) != 0) 93 return -1; 94 return 0; 95 } 96 97 signed int 81 98 Device::get_hardware_state(FF_state_t *state) 82 99 { … … 557 574 } 558 575 559 } 576 signed int 577 Device::hardware_init_streaming(unsigned int sample_rate, 578 unsigned int tx_channel) 579 { 580 // tx_channel is the ISO channel the PC will transmit on. 581 quadlet_t buf[4]; 582 fb_nodeaddr_t addr; 583 unsigned int size; 584 585 buf[0] = sample_rate; 586 buf[1] = (num_channels << 11) + tx_channel; 587 buf[2] = num_channels; 588 buf[3] = 0; 589 buf[4] = 0; 590 if (speed800) { 591 buf[2] |= RME_FF800_STREAMING_SPEED_800; 592 } 593 594 if (m_rme_model == RME_MODEL_FIREFACE400) { 595 addr = RME_FF400_STREAM_INIT_REG; 596 size = RME_FF400_STREAM_INIT_SIZE; 597 } else { 598 addr = RME_FF800_STREAM_INIT_REG; 599 size = RME_FF800_STREAM_INIT_SIZE; 600 } 601 602 return writeBlock(addr, buf, size); 603 } 604 605 signed int 606 Device::hardware_start_streaming(unsigned int listen_channel) 607 { 608 // Listen_channel is the ISO channel the PC will listen on for data sent 609 // by the Fireface. 610 fb_nodeaddr_t addr; 611 quadlet_t data = num_channels; 612 613 if (m_rme_model == RME_MODEL_FIREFACE400) { 614 addr = RME_FF400_STREAM_START_REG; 615 data |= (listen_channel << 5); 616 } else { 617 addr = RME_FF800_STREAM_START_REG; 618 if (speed800) 619 data |= RME_FF800_STREAMING_SPEED_800; // Flag 800 Mbps speed 620 } 621 622 return writeRegister(addr, data); 623 } 624 625 signed int 626 Device::hardware_stop_streaming(void) 627 { 628 fb_nodeaddr_t addr; 629 quadlet_t buf[4] = {0, 0, 0, 1}; 630 unsigned int size; 631 632 if (m_rme_model == RME_MODEL_FIREFACE400) { 633 addr = RME_FF400_STREAM_END_REG; 634 size = RME_FF400_STREAM_END_SIZE; 635 } else { 636 addr = RME_FF800_STREAM_END_REG; 637 size = RME_FF800_STREAM_END_SIZE; 638 } 639 640 return writeBlock(addr, buf, size); 641 } 642 643 } trunk/libffado/src/rme/rme_avdevice.cpp
r1594 r1596 100 100 , m_software_freq( -1 ) 101 101 , tco_present( 0 ) 102 , num_channels( 0 ) 103 , samples_per_packet( 0 ) 104 , speed800( 0 ) 102 105 { 103 106 debugOutput( DEBUG_LEVEL_VERBOSE, "Created Rme::Device (NodeID %d)\n", trunk/libffado/src/rme/rme_avdevice.h
r1594 r1596 99 99 FF_software_settings_t settings; 100 100 101 signed int num_channels; 102 signed int samples_per_packet; 103 signed int speed800; 104 101 105 private: 102 106 unsigned long long int cmd_buffer_addr(); … … 124 128 signed int init_hardware(void); 125 129 signed int get_hardware_status(unsigned int *stat0, unsigned int *stat1); 130 signed int get_hardware_streaming_status(unsigned int *stat, unsigned int n); 126 131 signed int get_hardware_state(FF_state_t *state); 127 132 signed int set_hardware_params(FF_software_settings_t *sw_settings); … … 135 140 136 141 signed int set_hardware_dds_freq(signed int freq); 142 143 signed int hardware_init_streaming(unsigned int sample_rate, unsigned int tx_channel); 144 signed int hardware_start_streaming(unsigned int listen_channel); 145 signed int hardware_stop_streaming(void); 137 146 }; 138 147