Changeset 1609

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Timestamp:
08/02/09 06:48:07 (15 years ago)
Author:
jwoithe
Message:

RME: provide low-level support for the channel 3/4 pad/instrument options of the Fireface-400
RME: update device documentation

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  • trunk/libffado/doc/rme_notes/rme_config_register_map.txt

    r1596 r1609  
    22============================================ 
    33 
    4 Version: 0.12 
     4Version: 0.13 
    55Author: Jonathan Woithe 
    6 Date: 12 July 2009 
     6Date: 2 August 2009 
    77 
    88 
     
    119119block of 12 bytes starting at 0xfc88f014 with a block write operation. 
    120120 
    121 Configuration register 1 (FF800: 0xfc88f014, FF400: 0x8010014): 
     121Configuration register 1 (FF800: 0xfc88f014, FF400: 0x80100514): 
    122122 
    123123  bits 31-18: unknown, set to 0 
     
    131131    010 = +4dBU 
    132132    100 = -10dBV 
    133   bit 9: Instrument option: Drive (part 1 of 2: FPGA LED drive) (active = 1) 
    134   bit 8: Phantom power, mic 10 (active = 1) 
     133  bit 9: FF800: Instr option: Drive (part 1 of 2: FPGA LED drive) (active = 1) 
     134         FF400: Channel 3 "instrument" switch 
     135  bit 8: FF800: Phantom power, mic 10 (active = 1) 
     136         FF400: Channel 3 "pad" switch 
    135137  bit 7: Phantom power, mic 8 (active = 1) 
    136138  bit 6: unknown, set to 0 
     
    139141    010 = +4dBU 
    140142    100 = -10dbV 
    141   bit 2: Instrument option: speaker emulation (part 1 of 2: FPGA LED drive) 
    142     (active = 1) 
    143   bit 1: Phantom power, mic 9 (active = 1) 
     143  bit 2: FF800: Instrument option: speaker emulation (aka "filter") (part 1  
     144           of 2: FPGA LED drive) (active = 1) 
     145         FF400: Channel 4 "instrument" switch 
     146  bit 1: FF800: Phantom power, mic 9 (active = 1) 
     147         FF400: Channel 4 "pad" switch 
    144148  bit 0: Phantom power, mic 7 (active = 1) 
    145149 
  • trunk/libffado/src/rme/fireface_def.h

    r1602 r1609  
    127127// Configuration register 0 
    128128#define CR0_PHANTOM_MIC0        0x00000001 
     129 
    129130#define CR0_PHANTOM_MIC2        0x00000002 
    130131#define CR0_FILTER_FPGA         0x00000004 
     132#define CR0_BIT01               0x00000002  // Use depends on model - see below 
     133#define CR0_BIT02               0x00000004  // Use depends on model - see below 
    131134#define CR0_ILEVEL_FPGA_CTRL0   0x00000008 
    132135#define CR0_ILEVEL_FPGA_CTRL1   0x00000010 
     
    134137#define CR0_ZEROBIT06           0x00000040 
    135138#define CR0_PHANTOM_MIC1        0x00000080 
    136 #define CR0_PHANTOM_MIC3        0x00000100 
    137 #define CR0_ZEROBIT09           0x00000200 
    138 #define CR0_INSTR_DRIVE_FPGA    0x00000200 
     139#define CR0_BIT08               0x00000100  // Use depends on model - see below 
     140#define CR0_BIT09               0x00000200  // Use depends on model - see below 
    139141#define CRO_OLEVEL_FPGA_CTRL_0  0x00000400 
    140142#define CRO_OLEVEL_FPGA_CTRL_1  0x00000800 
     
    146148#define CRO_PHLEVEL_CTRL1       0x00020000 
    147149 
    148 #define CR0_PHANTOM_FF400_MIC0  CR0_PHANTOM_MIC0 
    149 #define CR0_PHANTOM_FF400_MIC1  CR0_PHANTOM_MIC1 
    150 #define CR0_PHANTOM_FF800_MIC7  CR0_PHANTOM_MIC0 
    151 #define CR0_PHANTOM_FF800_MIC8  CR0_PHANTOM_MIC1 
    152 #define CR0_PHANTOM_FF800_MIC9  CR0_PHANTOM_MIC2 
    153 #define CR0_PHANTOM_FF800_MIC10 CR0_PHANTOM_MIC3 
     150#define CR0_FF400_PHANTOM_MIC0  CR0_PHANTOM_MIC0 
     151#define CR0_FF400_PHANTOM_MIC1  CR0_PHANTOM_MIC1 
     152#define CR0_FF400_CH3_PAD       CR0_BIT08 
     153#define CR0_FF400_CH3_INSTR     CR0_BIT09 
     154#define CR0_FF400_CH4_PAD       CR0_BIT01 
     155#define CR0_FF400_CH4_INSTR     CR0_BIT02 
     156#define CR0_FF800_PHANTOM_MIC7  CR0_PHANTOM_MIC0 
     157#define CR0_FF800_PHANTOM_MIC8  CR0_PHANTOM_MIC1 
     158#define CR0_FF800_PHANTOM_MIC9  CR0_BIT01 
     159#define CR0_FF800_PHANTOM_MIC10 CR0_BIT08 
     160#define CR0_FF800_FILTER_FPGA   CR0_BIT02 
     161#define CR0_FF800_DRIVE_FPGA    CR0_BIT09 
    154162#define CR0_ILEVEL_FPGA_LOGAIN  CR0_ILEVEL_FPGA_CTRL0 
    155163#define CR0_ILEVEL_FPGA_4dBU    CR0_ILEVEL_FPGA_CTRL1 
     
    427435    uint32_t sample_rate; 
    428436    uint32_t word_clock_single_speed; 
     437    uint32_t ff400_input_pad[2];       // Channels 3/4, FF400 only 
     438    uint32_t ff400_instr_input[2];     // Channels 3/4, FF400 only 
    429439    uint32_t phones_level;             // Derived from fields in device flash 
    430440    uint32_t input_opt[3];             // Derived from fields in device flash 
  • trunk/libffado/src/rme/fireface_flash.cpp

    r1591 r1609  
    252252        // Copy hardware details to the software settings structure as 
    253253        // appropriate. 
    254         for (i=0; i<4; i++) 
     254        for (i=0; i<2; i++) 
    255255            settings->mic_phantom[i] = hw_settings.mic_phantom[i]; 
     256        if (m_rme_model == RME_MODEL_FIREFACE800) { 
     257            for (i=2; i<4; i++) 
     258                settings->mic_phantom[i] = hw_settings.mic_phantom[i]; 
     259        } else { 
     260            // TODO: confirm this is true 
     261            for (i=2; i<4; i++) 
     262                settings->ff400_input_pad[i-2] = hw_settings.mic_phantom[i]; 
     263        } 
    256264        settings->spdif_input_mode = hw_settings.spdif_input_mode; 
    257265        settings->spdif_output_emphasis = hw_settings.spdif_output_emphasis; 
     
    266274        settings->input_level = hw_settings.input_level; 
    267275        settings->output_level = hw_settings.output_level; 
    268         settings->filter = hw_settings.filter; 
    269         settings->fuzz = hw_settings.fuzz; 
     276        if (m_rme_model == RME_MODEL_FIREFACE800) { 
     277            settings->filter = hw_settings.filter; 
     278            settings->fuzz = hw_settings.fuzz; 
     279        } else { 
     280            // TODO: confirm this is true 
     281            settings->ff400_instr_input[0] = hw_settings.fuzz; 
     282            settings->ff400_instr_input[1] = hw_settings.filter; 
     283        } 
    270284        settings->limiter_disable = (hw_settings.p12db_an[0] == 0)?1:0; 
    271285        settings->sample_rate = hw_settings.sample_rate; 
  • trunk/libffado/src/rme/fireface_hw.cpp

    r1606 r1609  
    232232    if (sw_settings->mic_phantom[1]) 
    233233      data[0] |= CR0_PHANTOM_MIC1; 
    234     if (sw_settings->mic_phantom[2]) 
    235       data[0] |= CR0_PHANTOM_MIC2; 
    236     if (sw_settings->mic_phantom[3]) 
    237       data[0] |= CR0_PHANTOM_MIC3; 
     234    if (m_rme_model == RME_MODEL_FIREFACE800) { 
     235        if (sw_settings->mic_phantom[2]) 
     236            data[0] |= CR0_FF800_PHANTOM_MIC9; 
     237        if (sw_settings->mic_phantom[3]) 
     238            data[0] |= CR0_FF800_PHANTOM_MIC10; 
     239    } else { 
     240        if (sw_settings->ff400_input_pad[0]) 
     241            data[0] |= CR0_FF400_CH3_PAD; 
     242        if (sw_settings->ff400_input_pad[1]) 
     243            data[0] |= CR0_FF400_CH4_PAD; 
     244    } 
    238245 
    239246    /* Phones level */ 
     
    290297    data[1] |= (sw_settings->input_opt[2] & FF_SWPARAM_INPUT_OPT_B) ? CR1_INPUT_OPT2_B : 0; 
    291298 
    292     // Drive the speaker emulation / filter LED via FPGA 
    293     data[0] |= (sw_settings->filter) ? CR0_FILTER_FPGA : 0; 
     299    // Drive the speaker emulation / filter LED via FPGA in FF800.  In FF400 
     300    // the same bit controls the channel 4 "instrument" option. 
     301    if (m_rme_model == RME_MODEL_FIREFACE800) { 
     302        data[0] |= (sw_settings->filter) ? CR0_FF800_FILTER_FPGA : 0; 
     303    } else { 
     304        data[0] |= (sw_settings->ff400_instr_input[1]) ? CR0_FF400_CH4_INSTR : 0; 
     305    } 
    294306 
    295307    // Set the "rear" option for input 0 if selected 
     
    313325    /* TMS / TCO toggle bits in CR2 are not set by other drivers */ 
    314326 
    315     /* Drive / fuzz */ 
    316     if (sw_settings->fuzz) 
    317       data[0] |= CR0_INSTR_DRIVE_FPGA; // FPGA LED control 
    318     else 
    319       data[1] |= CR1_INSTR_DRIVE;      // CPLD 
     327    /* Drive / fuzz in FF800.  In FF400, the CR0 bit used by "Drive" controls 
     328     * the channel 3 "instrument" option. 
     329     */ 
     330    if (m_rme_model == RME_MODEL_FIREFACE800) { 
     331        if (sw_settings->fuzz) 
     332            data[0] |= CR0_FF800_DRIVE_FPGA; // FPGA LED control 
     333        else 
     334            data[1] |= CR1_INSTR_DRIVE;      // CPLD 
     335    } else { 
     336        data[0] |= (sw_settings->ff400_instr_input[0]) ? CR0_FF400_CH3_INSTR : 0; 
     337    } 
    320338 
    321339    /* Drop-and-stop is hardwired on in other drivers */