332 | | |
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333 | | #if 1 |
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334 | | // hardware interrupts occur when one DMA block is full, and the size of one DMA |
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335 | | // block = PAGE_SIZE. Setting the max_packet_size makes sure that the HW irq |
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336 | | // occurs at a period boundary (optimal CPU use) |
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337 | | |
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338 | | // NOTE: try and use MINIMUM_INTERRUPTS_PER_PERIOD hardware interrupts |
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339 | | // per period for better latency. |
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340 | | unsigned int max_packet_size=(MINIMUM_INTERRUPTS_PER_PERIOD * getpagesize()/2) / packets_per_period; |
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341 | | |
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342 | | if (max_packet_size < stream->getMaxPacketSize()) { |
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343 | | debugWarning("calculated max packet size (%u) < stream max packet size (%u)\n", |
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344 | | max_packet_size ,(unsigned int)stream->getMaxPacketSize()); |
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345 | | max_packet_size = stream->getMaxPacketSize(); |
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| 332 | unsigned int max_packet_size = stream->getMaxPacketSize(); |
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| 333 | unsigned int page_size = getpagesize() - 2; // for one reason or another this is necessary |
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| 334 | |
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| 335 | // hardware interrupts can only occur when one DMA descriptor is full, |
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| 336 | // and the size of one DMA descriptor in bufferfill mode is PAGE_SIZE. |
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| 337 | // the number of packets that fits into this descriptor is dependent on |
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| 338 | // the max_packet_size parameter: |
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| 339 | // packets_per_descriptor = PAGE_SIZE / max_packet_size |
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| 340 | // |
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| 341 | // Hence if we want N hardware IRQ's in one period, we have to ensure that |
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| 342 | // there are at least N descriptors for one period worth of packets |
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| 343 | // hence: |
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| 344 | // packets_per_interrupt = packets_per_period / MINIMUM_INTERRUPTS_PER_PERIOD |
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| 345 | // packets_per_descriptor <= packets_per_interrupt |
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| 346 | // |
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| 347 | // or: |
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| 348 | // => PAGE_SIZE / max_packet_size <= packets_per_period / MINIMUM_INTERRUPTS_PER_PERIOD |
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| 349 | // => PAGE_SIZE * MINIMUM_INTERRUPTS_PER_PERIOD / packets_per_period <= max_packet_size |
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| 350 | |
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| 351 | unsigned int min_max_packet_size=(MINIMUM_INTERRUPTS_PER_PERIOD * page_size) / packets_per_period; |
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| 352 | |
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| 353 | if (max_packet_size < min_max_packet_size) { |
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| 354 | debugOutput(DEBUG_LEVEL_VERBOSE, "correcting stream max packet size (%u) to (%u) to ensure enough interrupts\n", |
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| 355 | max_packet_size, min_max_packet_size); |
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| 356 | max_packet_size = min_max_packet_size; |
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357 | | // FIXME: test |
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358 | | // irq_interval=1; |
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359 | | |
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360 | | #else |
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361 | | // hardware interrupts occur when one DMA block is full, and the size of one DMA |
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362 | | // block = PAGE_SIZE. Setting the max_packet_size enables control over the IRQ |
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363 | | // frequency, as the controller uses max_packet_size, and not the effective size |
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364 | | // when writing to the DMA buffer. |
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365 | | |
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366 | | // configure it such that we have an irq for every PACKETS_PER_INTERRUPT packets |
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367 | | unsigned int irq_interval = packets_per_period/MINIMUM_INTERRUPTS_PER_PERIOD; |
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368 | | if(irq_interval <= 0) irq_interval = 1; |
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369 | | |
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370 | | unsigned int max_packet_size = getpagesize()/2; |
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371 | | |
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372 | | if (max_packet_size < stream->getMaxPacketSize()) { |
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373 | | debugError("Stream max packet size too large: %d\n", stream->getMaxPacketSize()); |
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374 | | return false; |
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375 | | } |
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376 | | |
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377 | | #endif |
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378 | | /* the receive buffer size doesn't matter for the latency, |
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379 | | but it has a minimal value in order for libraw to operate correctly (300) */ |
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| 368 | |
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| 369 | // the receive buffer size doesn't matter for the latency, |
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| 370 | // but it has a minimal value in order for libraw to operate correctly (300) |
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397 | | |
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398 | | #if 0 |
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399 | | // hardware interrupts occur when one DMA block is full, and the size of one DMA |
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400 | | // block = PAGE_SIZE. Setting the max_packet_size makes sure that the HW irq |
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401 | | // occurs at a period boundary (optimal CPU use) |
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402 | | // NOTE: try and use MINIMUM_INTERRUPTS_PER_PERIOD interrupts per period |
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403 | | // for better latency. |
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404 | | unsigned int max_packet_size=MINIMUM_INTERRUPTS_PER_PERIOD * getpagesize() / packets_per_period; |
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405 | | if (max_packet_size < stream->getMaxPacketSize()) { |
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406 | | max_packet_size = stream->getMaxPacketSize(); |
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| 387 | unsigned int max_packet_size = stream->getMaxPacketSize(); |
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| 388 | unsigned int page_size = getpagesize() - 2; // for one reason or another this is necessary |
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| 389 | |
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| 390 | // hardware interrupts can only occur when one DMA descriptor is full, |
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| 391 | // and the size of one DMA descriptor in bufferfill mode is PAGE_SIZE. |
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| 392 | // the number of packets that fits into this descriptor is dependent on |
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| 393 | // the max_packet_size parameter: |
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| 394 | // packets_per_descriptor = PAGE_SIZE / max_packet_size |
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| 395 | // |
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| 396 | // Hence if we want N hardware IRQ's in one period, we have to ensure that |
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| 397 | // there are at least N descriptors for one period worth of packets |
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| 398 | // hence: |
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| 399 | // packets_per_interrupt = packets_per_period / MINIMUM_INTERRUPTS_PER_PERIOD |
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| 400 | // packets_per_descriptor <= packets_per_interrupt |
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| 401 | // |
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| 402 | // or: |
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| 403 | // => PAGE_SIZE / max_packet_size <= packets_per_period / MINIMUM_INTERRUPTS_PER_PERIOD |
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| 404 | // => PAGE_SIZE * MINIMUM_INTERRUPTS_PER_PERIOD / packets_per_period <= max_packet_size |
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| 405 | |
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| 406 | unsigned int min_max_packet_size=(MINIMUM_INTERRUPTS_PER_PERIOD * page_size) / packets_per_period; |
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| 407 | |
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| 408 | if (max_packet_size < min_max_packet_size) { |
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| 409 | debugOutput(DEBUG_LEVEL_VERBOSE, "correcting stream max packet size (%u) to (%u) to ensure enough interrupts\n", |
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| 410 | max_packet_size, min_max_packet_size); |
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| 411 | max_packet_size = min_max_packet_size; |
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411 | | if (max_packet_size > (unsigned int)getpagesize()) |
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412 | | max_packet_size = getpagesize(); |
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413 | | |
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414 | | unsigned int irq_interval = packets_per_period / MINIMUM_INTERRUPTS_PER_PERIOD; |
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415 | | if(irq_interval <= 0) irq_interval = 1; |
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416 | | |
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417 | | // the transmit buffer size should be as low as possible for latency. |
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418 | | // note however that the raw1394 subsystem tries to keep this buffer |
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419 | | // full, so we have to make sure that we have enough events in our |
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420 | | // event buffers |
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421 | | |
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422 | | // FIXME: latency spoiler |
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423 | | // every irq_interval packets an interrupt will occur. that is when |
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424 | | // buffers get transfered, meaning that we should have at least some |
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425 | | // margin here |
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426 | | //irq_interval=2; |
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427 | | //int buffers=30; |
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428 | | //max_packet_size = getpagesize(); // HACK |
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429 | | #else |
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430 | | // configure it such that we have an irq for every PACKETS_PER_INTERRUPT packets |
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431 | | unsigned int irq_interval = packets_per_period/MINIMUM_INTERRUPTS_PER_PERIOD; |
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432 | | if(irq_interval <= 0) irq_interval = 1; |
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433 | | |
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434 | | unsigned int max_packet_size=MINIMUM_INTERRUPTS_PER_PERIOD * getpagesize() / packets_per_period; |
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435 | | if (max_packet_size < stream->getMaxPacketSize()) { |
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436 | | max_packet_size = stream->getMaxPacketSize(); |
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437 | | } |
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438 | | |
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439 | | if (max_packet_size < stream->getMaxPacketSize()) { |
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440 | | debugError("Max packet size too large! (%d)\n", stream->getMaxPacketSize()); |
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441 | | } |
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442 | | // irq_interval=2; |
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443 | | #endif |
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444 | | // the SP specifies how many packets to buffer |
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| 416 | if (max_packet_size > page_size) { |
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| 417 | debugError("max packet size (%u) > page size (%u)\n", max_packet_size, page_size); |
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| 418 | return false; |
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| 419 | } |
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| 420 | |
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| 421 | unsigned int irq_interval = packets_per_period / MINIMUM_INTERRUPTS_PER_PERIOD; |
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| 422 | if(irq_interval <= 0) irq_interval=1; |
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| 423 | |
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| 424 | // the SP specifies how many packets to ISO-buffer |
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