Version 28 (modified by damo22, 13 years ago)
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Digidesign 003 Rack

This page is to help develop support for the Digidesign 003 Rack.
003rack

I have identified the registers below:

#define R003_BASE_ADDR          0xffffe0000000ULL

#define R003_STREAMS_W_REG      0x00000004
#define R003_STREAMS_R_REG      0x00000000
#define R003_STREAMS_OFF        0x00000000
#define R003_STREAMS_ON         0x00000001
#define R003_STREAMS_INIT       0x00000002
#define R003_STREAMS_SHUTDOWN   0x00000003

#define R003_SAMPLERATE_REG     0x00000110
#define R003_SAMPLERATE_44100   0x00000000
#define R003_SAMPLERATE_48000   0x00000001
#define R003_SAMPLERATE_88200   0x00000002
#define R003_SAMPLERATE_96000   0x00000003

#define R003_CLOCKSOURCE_REG    0x00000118
#define R003_CLOCK_INTERNAL     0x00000000
#define R003_CLOCK_SPDIF        0x00000001
#define R003_CLOCK_ADAT         0x00000002
#define R003_CLOCK_WORDCLOCK    0x00000003

ISO Channels used: 2
0x0 (recv)
0x1 (send)

To initialise the device it seems you need to do the following:

Write: R003_BASE_ADDR + R003_STREAMS_W_REG,   R003_STREAMS_INIT

Wait until:

Read:  R003_BASE_ADDR + R003_STREAMS_R_REG 

returns

R003_STREAMS_OFF

Once this is done, the 1394 link light starts flashing on the device.

Then set the samplerate and clock source, eg 48000/internal clock

Write: R003_BASE_ADDR + R003_SAMPLERATE_REG,  R003_SAMPLERATE_48000
Write: R003_BASE_ADDR + R003_CLOCKSOURCE_REG, R003_CLOCK_INTERNAL

Then activate the streams:

Write: R003_BASE_ADDR + R003_STREAMS_W_REG,   R003_STREAMS_ON

Wait until:

Read:  R003_BASE_ADDR + R003_STREAMS_R_REG 

returns

R003_STREAMS_ON

But I have not yet been able to observe iso data on the bus after this is done.

Iso packets from the device are supposed to look like this:

418922  data_length=0x01d0, tag=0x1, channel=0x00, iso_data, sy=0x0, crc=0xd3082841, data=[00130090 90020000 80000000 40ffffab 4000002b 40fffd57 40ffff3f 40fffff0 40000006 40ffffef 40fffff1 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 80000000 40ffffeb 40ffffdb 4000015a 40ffffae 40ffffee 40fffff8 40fffff5 40fffffe 40000000 40000000 (336 more bytes)], crc=0x8ccc5134, no ack

419029  data_length=0x021c, tag=0x1, channel=0x01, iso_data, sy=0x0, crc=0xf2bcef97, data=[001300bb 90020000 80000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 80000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 (412 more bytes)], crc=0x8414747c, no ack

419045  data_length=0x01d0, tag=0x1, channel=0x00, iso_data, sy=0x0, crc=0xd3082841, data=[00130096 90020000 80000000 40ffffc0 40000048 400005c2 40ffff86 40fffffd 4000000a 40ffffe3 40fffff7 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 80000000 40000073 4000002b 40fffda7 40ffff78 40ffffe5 40ffffe4 40000014 40ffffe9 40000000 40000000 (336 more bytes)], crc=0x24851d3c, no ack

419154  data_length=0x021c, tag=0x1, channel=0x01, iso_data, sy=0x0, crc=0xf2bcef97, data=[001300c2 90020000 80000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 80000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 (412 more bytes)], crc=0x498d307d, no ack

These are standard CIP packets (with some missing fields) containing standard AMDTP data.

The first two quadlets of each iso packet are the CIP header:

bitsmeaning
31-30 00
29-24 should be source node ID, here 0
23-16 data block size in quadlets
15-8 00000000
7-0 data block count
31-30 10
29-24 format, 010000 = audio/music
23-16 format-dependent field: 00000xxx for "AM824"-labeled data, x = 32/44.1/48/88.2/96/176.4/192/reserved kHz
15-0 should be synchronization timestamp, here 0

A "data block" is all the data of one audio frame; e.g., at a rate of 44.1 kHz, there are 44100 data blocks per second, somehow distributed over 8000 FireWire iso packets.

The data block count is the number of the first data block in the packet, modulo 256; this is intended to help detecting missing packets.

Labeled AM824 data is 40xxxxxx for a 24-bit PCM sample, or 80000000 for no MIDI data, or 81xx0000 for one MIDI byte. Every eighth MIDI quadlet is for one MIDI port, i.e., (up to) eight MIDI channels are multiplexed into one AM824 channel. (The Digi003 is unusual in that the MIDI quadlet is first in the data block, not last.)

FFADO's AMDTP streaming processors should be able to handle this.


It seems that after patching libraw1394 with the start_cycle patch, the iso streams turn on.

Since the maximum number of bytes the device can stream is 624 per packet, and there are 8000 iso firewire packets per second, and the device only supports 8 frames per packet, the maximum sample rate is 48000Hz using all 19 channels. I believe the device does not support ADAT channels in modes above 48000Hz.


I have written a working ffado driver for playback. However there is one glitch: the device keeps sending the following async packet (during iso transmission) to the host expecting a response, and I don't know how to handle it, the pc just returns address error and the device continues sending the packets interrupting playback... :|

dest=0xffc2 (PC), write_block_request, src=0xffc1 (003Rack), offs=0xffff00000040, data=[00007051]
                                                             offs=0xXXXXXXXXXXXX
data=[00007058] if the stream dies.

where XXXXXXXXXXXX is a configurable address using a control packet which I have worked out.


Standard MIDI Map Preset
Table 13. Default Standard MIDI Map, presets A1 and B1
Controller MIDI Channel CC# Mode Name LoVal/HiVal
PAGE 1
EQ1 1 122 Latch Local 0–127
Dynmcs1 1 123 Latch AllOff 0–127
Insert1 1 124 Latch OmniOn 0–127
PanSnd1 1 125 Latch OmniOff 0–127
Page <1 1 126 Latch MonoOn 0–127
Page >1 1 127 Latch PolyOn 0–127
MstByp1 1 NoAsgn Latch MstByp N/A
Esc1 1 NoAsgn Latch Esc N/A
Slct 1 1 NoAsgn Latch Slct 1 N/A
Slct 2 1 NoAsgn Latch Slct 2 N/A
Slct 3 1 NoAsgn Latch Slct 3 N/A
Slct 4 1 NoAsgn Latch Slct 4 N/A
Slct 5 1 NoAsgn Latch Slct 5 N/A
Slct 6 1 NoAsgn Latch Slct 6 N/A
Slct 7 1 NoAsgn Latch Slct 7 N/A
Slct 8 1 NoAsgn Latch Slct 8 N/A
Solo 1 1 15 Latch Solo 1 0–127
Solo 2 2 15 Latch Solo 2 0–127
Solo 3 3 15 Latch Solo 3 0–127
Solo 4 4 15 Latch Solo 4 0–127
Solo 5 5 15 Latch Solo 5 0–127
Solo 6 6 15 Latch Solo 6 0–127
Solo 7 7 15 Latch Solo 7 0–127
Solo 8 8 15 Latch Solo 8 0–127
Mute 1 1 14 Latch Mute 1 0–127
Mute 2 2 14 Latch Mute 2 0–127
Mute 3 3 14 Latch Mute 3 0–127
Mute 4 4 14 Latch Mute 4 0–127
Mute 5 5 14 Latch Mute 5 0–127
Mute 6 6 14 Latch Mute 6 0–127
Mute 7 7 14 Latch Mute 7 0–127
Mute 8 8 14 Latch Mute 8 0–127
Encdr1 1 10 N/A Encdr1 0–127
Encdr2 2 10 N/A Encdr2 0–127
Encdr3 3 10 N/A Encdr3 0–127
Encdr4 4 10 N/A Encdr4 0–127
Encdr5 5 10 N/A Encdr5 0–127
Encdr6 6 10 N/A Encdr6 0–127
Encdr7 7 10 N/A Encdr7 0–127
Encdr8 8 10 N/A Encdr8 0–127
Fader1 1 7 N/A Fader1 0–127
Fader2 2 7 N/A Fader2 0–127
Fader3 3 7 N/A Fader3 0–127
Fader4 4 7 N/A Fader4 0–127
Fader5 5 7 N/A Fader5 0–127
Fader6 6 7 N/A Fader6 0–127
Fader7 7 7 N/A Fader7 0–127
Fader8 8 7 N/A Fader8 0–127
REW1 — MMC RW Moment REW N/A
FF1 — MMC FF Moment FF N/A
STOP1 — MMC ST Moment STOP N/A
PLAY1 — MMC PL Moment PLAY N/A
RECORD1 — MMC RC Moment RECORD N/A
RTZ1 — NoAsgn Moment RTZ N/A
Nav Up1 1 102 Moment Nav Up 0–127
Nav Down1 1 103 Moment Nav Dn 0–127
Nav Left1 1 104 Moment Nav L 0–127
Nav Right1 1 105 Moment Nav R 0–127
Rec Arm1 1 106 Latch RecArm 0–127
PanMd1 1 107 Latch Pans 0–127
SndMd1 1 108 Latch Sends 0–127
InsMd1 1 109 Latch Insert 0–127
A/F1 1 110 Latch A/F 0–127
B/G1 1 111 Latch B/G 0–127
C/H1 1 112 Latch C/H 0–127
D/I1 1 113 Latch D/I 0–127
E/J1 1 114 Latch F/J 0–127
Footswitch1 8 11 Moment Footsw 0–127

Damo

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