Version 40 (modified by damo22, 10 years ago)
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Digidesign 003 Rack

This page is to help develop support for the Digidesign 003 Rack.
003rack

I have identified the registers below:

#define R003_HARDWARE_ADDR      0xffff00000000ULL

#define VENDOR_DIGIDESIGN       0xa07e
#define VENDOR_DIGIDESIGN_NAME  " "
#define R003_MODEL_ID           0x00000002
#define R003_MODEL_NAME         " 003Rack "

#define R003_STREAMS_W_REG      0xe0000004
#define R003_STREAMS_R_REG      0xe0000000
#define R003_STREAMS_OFF        0x00000000
#define R003_STREAMS_ON         0x00000001
#define R003_STREAMS_INIT       0x00000002
#define R003_STREAMS_SHUTDOWN   0x00000003

#define R003_SAMPLERATE_REG     0xe0000110
#define R003_SAMPLERATE_44100   0x00000000
#define R003_SAMPLERATE_48000   0x00000001
#define R003_SAMPLERATE_88200   0x00000002
#define R003_SAMPLERATE_96000   0x00000003

#define R003_CLOCKSOURCE_REG    0xe0000118
#define R003_CLOCK_INTERNAL     0x00000000
#define R003_CLOCK_SPDIF        0x00000001
#define R003_CLOCK_ADAT         0x00000002
#define R003_CLOCK_WORDCLOCK    0x00000003

#define R003_MIX                (0xe0000300 | R003_HARDWARE_ADDR)
#define R003_MIX_ANALOG_1L      (0x00 | R003_MIX)
#define R003_MIX_ANALOG_1R      (0x04 | R003_MIX) 
#define R003_MIX_ANALOG_2L      (0x08 | R003_MIX)
#define R003_MIX_ANALOG_2R      (0x0c | R003_MIX)
#define R003_MIX_ANALOG_3L      (0x10 | R003_MIX)
#define R003_MIX_ANALOG_3R      (0x14 | R003_MIX)
#define R003_MIX_ANALOG_4L      (0x18 | R003_MIX)
#define R003_MIX_ANALOG_4R      (0x1c | R003_MIX)
#define R003_MIX_ANALOG_5L      (0x20 | R003_MIX)
#define R003_MIX_ANALOG_5R      (0x24 | R003_MIX)
#define R003_MIX_ANALOG_6L      (0x28 | R003_MIX)
#define R003_MIX_ANALOG_6R      (0x2c | R003_MIX)
#define R003_MIX_ANALOG_7L      (0x30 | R003_MIX)
#define R003_MIX_ANALOG_7R      (0x34 | R003_MIX)
#define R003_MIX_ANALOG_8L      (0x38 | R003_MIX)
#define R003_MIX_ANALOG_8R      (0x3c | R003_MIX)
#define R003_MIX_SPDIF_1L       (0x40 | R003_MIX)
#define R003_MIX_SPDIF_1R       (0x44 | R003_MIX)
#define R003_MIX_SPDIF_2L       (0x48 | R003_MIX)
#define R003_MIX_SPDIF_2R       (0x4c | R003_MIX)
#define R003_MIX_ADAT_1L        (0x50 | R003_MIX)
#define R003_MIX_ADAT_1R        (0x54 | R003_MIX)
#define R003_MIX_ADAT_2L        (0x58 | R003_MIX)
#define R003_MIX_ADAT_2R        (0x5c | R003_MIX)
#define R003_MIX_ADAT_3L        (0x60 | R003_MIX)
#define R003_MIX_ADAT_3R        (0x64 | R003_MIX)
#define R003_MIX_ADAT_4L        (0x68 | R003_MIX)
#define R003_MIX_ADAT_4R        (0x6c | R003_MIX)
#define R003_MIX_ADAT_5L        (0x70 | R003_MIX)
#define R003_MIX_ADAT_5R        (0x74 | R003_MIX)
#define R003_MIX_ADAT_6L        (0x78 | R003_MIX)
#define R003_MIX_ADAT_6R        (0x7c | R003_MIX)
#define R003_MIX_ADAT_7L        (0x80 | R003_MIX)
#define R003_MIX_ADAT_7R        (0x84 | R003_MIX)
#define R003_MIX_ADAT_8L        (0x88 | R003_MIX)
#define R003_MIX_ADAT_8R        (0x8c | R003_MIX)

#define R003_MIX_NONE           0x00000000
#define R003_MIX_1_TO_STEREO    0x18000000
#define R003_MIX_1_TO_1         0x20000000


ISO Channels used: 2
0x0 (recv) = (capture)
0x1 (send) = (playback)

To initialise the device it seems you need to do the following:

Write: R003_BASE_ADDR + R003_STREAMS_W_REG,   R003_STREAMS_INIT

Wait until:

Read:  R003_BASE_ADDR + R003_STREAMS_R_REG 

returns

R003_STREAMS_OFF

Once this is done, the 1394 link light starts flashing on the device.

Then set the samplerate and clock source, eg 48000/internal clock

Write: R003_BASE_ADDR + R003_SAMPLERATE_REG,  R003_SAMPLERATE_48000
Write: R003_BASE_ADDR + R003_CLOCKSOURCE_REG, R003_CLOCK_INTERNAL

Then activate the streams:

Write: R003_BASE_ADDR + R003_STREAMS_W_REG,   R003_STREAMS_ON

Wait until:

Read:  R003_BASE_ADDR + R003_STREAMS_R_REG 

returns

R003_STREAMS_ON

and then read the clocksource register to activate the stream:

Read: R003_BASE_ADDR + R003_CLOCKSOURCE_REG

Now the device expects some playback frames to be sent to it immediately, and once the buffer fills up the capture stream will activate automatically. I am unsure exactly how many frames it requires, although I have observed 4 packets of 540 bytes long in one instance. I do believe overshooting this number will not hurt, it will just play the extra frames of silence.

Iso packets from the device are supposed to look like this:

418922  data_length=0x01d0, tag=0x1, channel=0x00, iso_data, sy=0x0, crc=0xd3082841, data=[00130090 90020000 80000000 40ffffab 4000002b 40fffd57 40ffff3f 40fffff0 40000006 40ffffef 40fffff1 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 80000000 40ffffeb 40ffffdb 4000015a 40ffffae 40ffffee 40fffff8 40fffff5 40fffffe 40000000 40000000 (336 more bytes)], crc=0x8ccc5134, no ack

419029  data_length=0x021c, tag=0x1, channel=0x01, iso_data, sy=0x0, crc=0xf2bcef97, data=[001300bb 90020000 80000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 80000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 (412 more bytes)], crc=0x8414747c, no ack

419045  data_length=0x01d0, tag=0x1, channel=0x00, iso_data, sy=0x0, crc=0xd3082841, data=[00130096 90020000 80000000 40ffffc0 40000048 400005c2 40ffff86 40fffffd 4000000a 40ffffe3 40fffff7 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 80000000 40000073 4000002b 40fffda7 40ffff78 40ffffe5 40ffffe4 40000014 40ffffe9 40000000 40000000 (336 more bytes)], crc=0x24851d3c, no ack

419154  data_length=0x021c, tag=0x1, channel=0x01, iso_data, sy=0x0, crc=0xf2bcef97, data=[001300c2 90020000 80000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 80000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 40000000 (412 more bytes)], crc=0x498d307d, no ack

These are standard CIP packets (with some missing fields) containing standard AMDTP data.

The first two quadlets of each iso packet are the CIP header:

bitsmeaning
31-30 00
29-24 should be source node ID, here 0
23-16 data block size in quadlets
15-8 00000000
7-0 data block count
31-30 10
29-24 format, 010000 = audio/music
23-16 format-dependent field: 00000xxx for "AM824"-labeled data, x = 32/44.1/48/88.2/96/176.4/192/reserved kHz
15-0 should be synchronization timestamp, here 0

A "data block" is all the data of one audio frame; e.g., at a rate of 44.1 kHz, there are 44100 data blocks per second, somehow distributed over 8000 FireWire iso packets.

The data block count is the number of the first data block in the packet, modulo 256; this is intended to help detecting missing packets.

Labeled AM824 data is 40xxxxxx for a 24-bit PCM sample, or 80000000 for no MIDI data, or 81xx0000 for one MIDI byte. Every eighth MIDI quadlet is for one MIDI port, i.e., (up to) eight MIDI channels are multiplexed into one AM824 channel. (The Digi003 is unusual in that the MIDI quadlet is first in the data block, not last.)

FFADO's AMDTP streaming processors should be able to handle this.


Update July 2012: Having done some more bus snooping, I discovered:

The device supports at least 2 main modes: 96/24 with 10 ins and 10 outs and 1 midi. 48/24 with 18 ins and 18 outs and 1 midi.

I modified the experimental DICE driver and this resulted in playback over all channels. Unfortunately the streams are glitching due to some async status packet being sent repeatedly from the device to the host for an unknown reason and causing iso dropouts (i think).


003 Rack Internal Mixer

I have worked out the commands to route audio from any input channel to either Analog 1 out, Analog 2 out or centred over these two channels in a stereo panned mode for zero latency monitoring of any input.

Basically, you set two registers per channel in one of four valid combinations:

Set channel type x, number y to no passthrough:

Write: R003_MIX_x_yL, R003_MIX_NONE
Write: R003_MIX_x_yR, R003_MIX_NONE

Set channel type x, number y to centred stereo over channels 1+2:

Write: R003_MIX_x_yL, R003_MIX_1_TO_STEREO
Write: R003_MIX_x_yR, R003_MIX_1_TO_STEREO

Set channel type x, number y to passthrough to channel 1 only:

Write: R003_MIX_x_yL, R003_MIX_1_TO_1
Write: R003_MIX_x_yR, R003_MIX_NONE

Set channel type x, number y to passthrough to channel 2 only:

Write: R003_MIX_x_yL, R003_MIX_NONE
Write: R003_MIX_x_yR, R003_MIX_1_TO_1

MIDI Control of front panel and solo/mutes

According to the 003 Rack documentation, the device responds to MIDI control messages to drive the switches on the front panel, as well as added features such as software faders and solo/mutes for each channel via MIDI (though I don't know if the latter is just for controlling the software, or if it does it in hardware, although I have noticed channels muting on and off and LEDs going crazy in a semi-Vegas mode when I send audio data down the midi port by mistake!).

Standard MIDI Map Preset
Table 13. Default Standard MIDI Map, presets A1 and B1
Controller MIDI Channel CC# Mode Name LoVal/HiVal
PAGE 1
EQ1 1 122 Latch Local 0–127
Dynmcs1 1 123 Latch AllOff 0–127
Insert1 1 124 Latch OmniOn 0–127
PanSnd1 1 125 Latch OmniOff 0–127
Page <1 1 126 Latch MonoOn 0–127
Page >1 1 127 Latch PolyOn 0–127
MstByp1 1 NoAsgn Latch MstByp N/A
Esc1 1 NoAsgn Latch Esc N/A
Slct 1 1 NoAsgn Latch Slct 1 N/A
Slct 2 1 NoAsgn Latch Slct 2 N/A
Slct 3 1 NoAsgn Latch Slct 3 N/A
Slct 4 1 NoAsgn Latch Slct 4 N/A
Slct 5 1 NoAsgn Latch Slct 5 N/A
Slct 6 1 NoAsgn Latch Slct 6 N/A
Slct 7 1 NoAsgn Latch Slct 7 N/A
Slct 8 1 NoAsgn Latch Slct 8 N/A
Solo 1 1 15 Latch Solo 1 0–127
Solo 2 2 15 Latch Solo 2 0–127
Solo 3 3 15 Latch Solo 3 0–127
Solo 4 4 15 Latch Solo 4 0–127
Solo 5 5 15 Latch Solo 5 0–127
Solo 6 6 15 Latch Solo 6 0–127
Solo 7 7 15 Latch Solo 7 0–127
Solo 8 8 15 Latch Solo 8 0–127
Mute 1 1 14 Latch Mute 1 0–127
Mute 2 2 14 Latch Mute 2 0–127
Mute 3 3 14 Latch Mute 3 0–127
Mute 4 4 14 Latch Mute 4 0–127
Mute 5 5 14 Latch Mute 5 0–127
Mute 6 6 14 Latch Mute 6 0–127
Mute 7 7 14 Latch Mute 7 0–127
Mute 8 8 14 Latch Mute 8 0–127
Encdr1 1 10 N/A Encdr1 0–127
Encdr2 2 10 N/A Encdr2 0–127
Encdr3 3 10 N/A Encdr3 0–127
Encdr4 4 10 N/A Encdr4 0–127
Encdr5 5 10 N/A Encdr5 0–127
Encdr6 6 10 N/A Encdr6 0–127
Encdr7 7 10 N/A Encdr7 0–127
Encdr8 8 10 N/A Encdr8 0–127
Fader1 1 7 N/A Fader1 0–127
Fader2 2 7 N/A Fader2 0–127
Fader3 3 7 N/A Fader3 0–127
Fader4 4 7 N/A Fader4 0–127
Fader5 5 7 N/A Fader5 0–127
Fader6 6 7 N/A Fader6 0–127
Fader7 7 7 N/A Fader7 0–127
Fader8 8 7 N/A Fader8 0–127
REW1 — MMC RW Moment REW N/A
FF1 — MMC FF Moment FF N/A
STOP1 — MMC ST Moment STOP N/A
PLAY1 — MMC PL Moment PLAY N/A
RECORD1 — MMC RC Moment RECORD N/A
RTZ1 — NoAsgn Moment RTZ N/A
Nav Up1 1 102 Moment Nav Up 0–127
Nav Down1 1 103 Moment Nav Dn 0–127
Nav Left1 1 104 Moment Nav L 0–127
Nav Right1 1 105 Moment Nav R 0–127
Rec Arm1 1 106 Latch RecArm 0–127
PanMd1 1 107 Latch Pans 0–127
SndMd1 1 108 Latch Sends 0–127
InsMd1 1 109 Latch Insert 0–127
A/F1 1 110 Latch A/F 0–127
B/G1 1 111 Latch B/G 0–127
C/H1 1 112 Latch C/H 0–127
D/I1 1 113 Latch D/I 0–127
E/J1 1 114 Latch F/J 0–127
Footswitch1 8 11 Moment Footsw 0–127

Damo

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