Version 7 (modified by damo22, 13 years ago)
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Digidesign 003 Rack

This page is to help develop support for the Digidesign 003 Rack.

I have identified the registers below:

#define R003_BASE_ADDR          0xffff00000000ULL[[BR]]

#define R003_STREAMS_W_REG      0xe0000004[[BR]]
#define R003_STREAMS_R_REG      0xe0000000[[BR]]
#define R003_STREAMS_OFF        0x00000000[[BR]]
#define R003_STREAMS_ON         0x00000001[[BR]]
#define R003_STREAMS_INIT       0x00000002[[BR]]
#define R003_STREAMS_SHUTDOWN   0x00000003[[BR]]

#define R003_SAMPLERATE_REG     0xe0000110[[BR]]
#define R003_SAMPLERATE_44100   0x00000000[[BR]]
#define R003_SAMPLERATE_48000   0x00000001[[BR]]
#define R003_SAMPLERATE_88200   0x00000002[[BR]]
#define R003_SAMPLERATE_96000   0x00000003[[BR]]

#define R003_CLOCKSOURCE_REG    0xe0000118[[BR]]
#define R003_CLOCK_INTERNAL     0x00000000[[BR]]
#define R003_CLOCK_SPDIF        0x00000001[[BR]]
#define R003_CLOCK_ADAT         0x00000002[[BR]]
#define R003_CLOCK_WORDCLOCK    0x00000003[[BR]]

ISO Channels used: 2
0x0 (recv)
0x1 (send)

To initialise the device it seems you need to do the following:

Write: R003_BASE_ADDR + R003_STREAMS_W_REG, R003_STREAMS_INIT
Wait until:
Read: R003_BASE_ADDR + R003_STREAMS_R_REG returns R003_STREAMS_OFF

Then set the samplerate and clock source, eg 48000/internal clock.
Write: R003_BASE_ADDR + R003_SAMPLERATE_REG, R003_SAMPLERATE_48000
Write: R003_BASE_ADDR + R003_CLOCKSOURCE_REG, R003_CLOCK_INTERNAL

Then activate the streams:
Write: R003_BASE_ADDR + R003_STREAMS_W_REG, R003_STREAMS_ON
Wait until:
Read: R003_BASE_ADDR + R003_STREAMS_R_REG returns R003_STREAMS_ON

But I have not yet been able to observe iso data on the bus after this is done.

Damo

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